6.002x CIRCUITS AND ELECTRONICS - edX · 2013-02-21 · 2 Real numbers Transistors f P 2.5x10 6 66...
Transcript of 6.002x CIRCUITS AND ELECTRONICS - edX · 2013-02-21 · 2 Real numbers Transistors f P 2.5x10 6 66...
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6.002x CIRCUITS AND
ELECTRONICS
Energy, CMOS
Reading Section 11.4, 11.5 of A&L
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SV +–
1R
C 2R
1S 2S
fTTT
121 =+=
fCVP S
2=
Review
openS
closedS
2
1
t
closedS
openS
2
1
1T 2T
T
Hypothetical example circuit
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2
T
T
2
T
INv
fT
1=
Inverter
Ov
INv C
SV
LR
ONR
Review
SV +–
LR
C
ONR
t
Eqvt. ckt On for T/2Off for T/2
fCVR
VP S
L
S 22
2+=
STATICP DYNAMICP
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6
9
105 gates#
V5
103
k10
F1
×=
=
×=
Ω=
=
S
L
V
f
R
fC
×××+×
×= − 915
4
6 1032510102
25105P
[ ]microwatts75milliwatts25.1105 6 +×=
6.25KW! 375W
STATICP DYNAMICP
fCVR
VP S
L
S 22
2+=One gate:
disaster ! bad
Review Inverter – numbers
How do we get rid of static power?
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How to get rid of static power
Intuition:
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How to get rid of static power when input is high
Intuition:
Ov
SV
ONR
LR
Iv high low
i
Problem case
SV
LR
Ov
Iv low
offMOSFET
high
No problem
highIv I
v low
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New Device PFET
N-channel MOSFET (NFET) P-channel MOSFET (PFET)
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Consider this circuit
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Behavior of the circuit
vI= 0V (input low)v
I= 5V (input high) S
DG
D
SG
OvI
v
+
–
SV
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OvIv
SV
Key: no path from VSto GND! no static power!
Let’s compute DYNAMICP
t
T
Iv
Tf
1=
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Using numbers from our previous example for CMOS
fCVP S
2=
6
9
105 gates#
V5
103
k10
F1
×=
=
×=
Ω=
=
S
L
V
f
R
fC
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Scaling up Increase frequency and number of gates, but if everything else stayed the same
PGates f
106100 MHz
~2.5watts
2x106300 MHz
~15watts
2x106600 MHz
~30watts
5x106 3 GHz~375watts
25x106 3 GHz~1875watts
fCVP S
2=
V5
103
k10
F1
9
=
×=
Ω=
=
S
L
V
f
R
fC
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How to reduce power
V5
103
k10
F1
9
=
×=
Ω=
=
S
L
V
f
R
fC
fCVP S
2
=
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Real numbers
PTransistors f
2.5x106 66 MHz 15WIntel Pentium 700nm, 1993
7.5x106 400 MHz 35WIntel PII350nm, 1997
44x106 1 GHz 15WIntel PIII180nm, 1999
120x106 0.43 GHz 18WMIT Raw processor 16-core180nm, 2002
120x106 3 GHz 75WIntel PIV130nm, 2001
615x106 0.7 GHz 20WTilera Tile64Pro 64-core 90nm, 2007
2300x106 3.6 GHz 75WIntel Nehalem 8-core45nm, 2011
fCVP S
2
=
http://groups.csail.mit.edu/cag/raw
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Scaling up – leakage arises, causes static power dissipation
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CMOS LogicS
DG
onS
DG
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In general, if we want to implement F
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BAF ⋅=e.g.
If we want to implement F
A
B
shortwhen Fis true,else open
SV
Z
shortwhen Fis true,else open
A
SV
B
A B
Z