Non-linear application:schmitt trigger - + Positive Feedback Schmitt Trigger.
6 November 2003Matthew Warren - Trigger Module Update - RAL1 CALICE CERC BE-FPGA Trigger Module...
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6 November 2003 Matthew Warren - Trigger Module Update - RAL 1 CALICE CERC BE-FPGA CALICE CERC BE-FPGA Trigger Module Update Trigger Module Update Matthew Warren University College London 6 November 2003
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6 November 2003Matthew Warren - Trigger Module Update - RAL3 SerIFace Protocol Interfaces RS232 to an A16 D32 bus 7 bytes out, 5 bytes back ALWAYS. Out = cmd, addr1, addr0, data3, data2, data1, data0 reply = cmd*, data3, data2, data1, data0 Addr0(1:0) ignored due to 32 bit bus – we could shift the bits, but 64kB is overkill anyway. Provides means of addressing modules in the cmd byte: - Could be routed in BE-FPGA, or broadcast and only have the correct module reply. Will be coupled with a BE-FPGA trigger pass-through test (When?) - Requires clock fan-out - Requires proper pin-out
Transcript of 6 November 2003Matthew Warren - Trigger Module Update - RAL1 CALICE CERC BE-FPGA Trigger Module...
6 November 2003
Matthew Warren - Trigger Module Update - RAL 1
CALICE CERC BE-FPGACALICE CERC BE-FPGATrigger Module UpdateTrigger Module Update
Matthew Warren University College London
6 November 2003
6 November 2003
Matthew Warren - Trigger Module Update - RAL 2
ProgresProgresssBE FPGA Pin-outs
- Got perl scripts to extract/compare pin-outs from netlists.- Produced quick spreadsheet FED/CERC/FED UCF pins.
“SerIFace”- Robs byte feedback integrated and working- Robs Python scripts adapted and working- Packet based protocol drafted. - FPGA code for protocol works in simulation but still not quite working on dev-board.- Actual internal bus-interface not tested
Became British! Put an offer in on a house in Cape Town (hence lack of progress)
6 November 2003
Matthew Warren - Trigger Module Update - RAL 3
SerIFace SerIFace ProtocolProtocolInterfaces RS232 to an A16 D32 bus
7 bytes out, 5 bytes back ALWAYS.Out = cmd, addr1, addr0, data3, data2, data1, data0reply = cmd*, data3, data2, data1, data0
Addr0(1:0) ignored due to 32 bit bus – we could shift the bits, but 64kB is overkill anyway.
Provides means of addressing modules in the cmd byte:- Could be routed in BE-FPGA, or broadcast and only have the correct module reply.
Will be coupled with a BE-FPGA trigger pass-through test (When?)- Requires clock fan-out- Requires proper pin-out
6 November 2003
Matthew Warren - Trigger Module Update - RAL 4
SerIFace Command SerIFace Command ByteBytecmd bits: 7 6 5 4 3 2 1 0
OP-CODE CMD/REPLY DESTINATION
OP-CODE: Reply = • 000 Test 0xA110A110 ('allo 'allo!)• 001 Write Write Data• 010 Read• 011 Read2• 100 Status• 101 reserved 0xDEADD0D0• 110 reserved 0xDEADD0D0• 111 Trigger 0xEEEEAAAA
DESTINATION: • 0-7 = FE Modules• 8 = Trigger
CMD/REPLY: • 0 = Command sent from controller• 1 = Reply to command (i.e. repliers change this bit)
6 November 2003
Matthew Warren - Trigger Module Update - RAL 5
CALICE Oct Nov Dec Jan6 132025 3 101724 1 8 152229 5 121926
Trigger Interface Test SystemTrigger Pass-through
Internal/Stand Alone Funcs
Main Functions
VME Access
Header Data
Testing
ZEUS, ATLAS, Holiday
SchedulSchedulee
