5.5 Encoders
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5.5 Encoders Retur n Next A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The output code generally has fewer bits than the input code, and there is one-to-one mapping from input code words into output code words. input code word output code word enabl e input s map Encoder
description
input code word. map. output code word. enable inputs. Encoder. Return. Next. 5.5 Encoders. - PowerPoint PPT Presentation
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5.5 Encoders
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A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The output code generally has fewer bits than the input code, and there is one-to-one mapping from input code words into output code words.
inputcode word
outputcode word
enable
inputs
map
Encoder
5.5 Encoders Binary encoder The most common decoder circuit is an 2n-to-n encoder or binary encoder. Such a encoder has an 2n-bit binary input code and n-bit output binary code.
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Binary encoder
I0 Y0I1 Y1 I2 : : : : Yn-1
I2n-1
Write the truth table for 8-to-3 binary encoder and the output logic function expressions.
If multiple requests can be made simultaneously, the encoder gives undesirable results.
5.5 Encoders
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75310 IIIIY
Simulation
76321 IIIIY 76542 IIIIY
Suppose the inputs I2 and I4 are both 1, what is the output ?
Priority Encoders The solution is to assign priority to the input lines, so that when multiple inputs are asserted, the encoding device produces the number of the highest-priority input. Such a device is called a priority encoder.
5.5 Encoders
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The 74x148 Priority Encoders
EI I7 A2 I6 A1I5 A0I4I3 GSI2 EOI1 I0
74X148
67
91
1415
5
4
3
2
13121110
Input data I0-I7 Enable input EI Output GS is asserted when the device is
enabled and one or more of the request are asserted.
Output EO is asserted if EI is assert but no request input is asserted, it designed to be connected to the EI input of another ‘148 that handles lower-priority requests.
5.5 Encoders
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Truth table for a 74x148 8-input priority encoder
5.5 Encoders
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Inputs Outputs
EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS
EO
1 x x x x x x x x0 x x x x x x x 00 x x x x x x 0 10 x x x x x 0 1 10 x x x x 0 1 1 10 x x x 0 1 1 1 10 x x 0 1 1 1 1 10 x 0 1 1 1 1 1 10 0 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1
1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0
Logic diagram for the 74x148 priority encode (p379 Figure 5-50)
5.5 Encoders
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Cascading Binary Encoders (p380 Figure 5-51)
