5 Variable Karnaugh Map Example
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Transcript of 5 Variable Karnaugh Map Example
Five Variable Maps
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 91
Five Variable Maps
b
c
d
1 1
01
1a 1
1
b
c
d
1 1
11
1a 1
1Two methods:
1) 32 squares
2) Enter variables (letters) on the 16 square map
b
c
d
1 1
e
e1a 1
1
This map fore=1
Best for where “e” has simple relations:
Think of two maps on top of each other
1
0This map for
e=0
One can circle squares:on either level,or between levels.
b
c
d
1 1
01
1a 1
1
1b
c
d
1 1
01
1a 1
1
1
1
This is the same as putting a “1” on the e=0 map
Can circle
This is the same as putting a “1” on the e=1 map
e 1 e 1 1 1
e eCannot circle
“e” is in only a few squaresor “e” is in almost all the squares.
Slide 46
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 92
Five Variable Maps Five Variable Maps
Five Variable MapsWrap Around
To circle between layers, the layers must have a “1” in thesame position on both layers.These are the squares which differ by only one input bit.
Use of variable entered maps
For complicated functions using the double map is usuallyeasier.
For many functions one of the variables has a simplerelationship. Then the variable entered map is simpler.
58.• PROBLEM
Plot the variable entered map on the right on the 5-variablemap on its left.
b
c
d
1
1
11a 1
1
1
1
b
c
d
a
b
c
d
1
1a 1
11
b
c
d
a
1
e=1
e=0
e=1
e=0OK
b
c
d
a
b
c
d
a
e=1
e=0b
c
d
a
Variable entered map
11
1e1
e
e
Comment on Slide 46
Five Variable Maps Five Variable Maps
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 93
Five Variable Maps
b
c
d
1 1
01
1a 1
1
b
c
d
1 1
11
a 1
1
Method 1: Dual 4-Variable maps
b
c
d
1 1
e
a 1
e=1 1
0e=0
b
0
ab
0
aMethod 2: Variable Entered Maps
1F = e(b·d)
+ acd + ab
+ e(cd)
1
1
11
1
11
1
1
e
F = e(b·d)
+ acd + ab
+ e(cd)
must also be in another circle“1s” in circles containing e
containing e or all “1s”.
must be in another circle“1s” in circles containing e
containing e or all “1s”.
Terms for circles
containing e are ANDed with e
1 e1
1 ee
1 e1
1 ee
or
or
Terms for circles
containing e are ANDed with e
e=0 map are ANDed with eTerms for circles only on the
Terms for circles only on thee=1 map are ANDed with e
Terms for circles on both mapsdon’t mention e.
CommentonSlide63Slide 47
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 94
Five Variable Maps Five-Variable Maps
Comment on Slide 47
Five-Variable MapsThe “0” is specifically entered on one map, just to remind you that it is a “1” on the other map.
Normally “0” are left blank to reduce the clutter.
59.• PROBLEM
F = (abc + abd + cb)e + (abd + ac + adb)e
= (abc + cb)e + (ac + adb)e +abd
Plot F on the 5 variable map on the right.
Plot F on the variable entered map on the right.
60.• PROBLEM (based on the last problem)
Circle the 5 variable map and reduce F to 12 letters.
Circle the variable entered map and reduce F to 4 terms of 3letters each.
b
c
d
a
b
c
d
a
e=1
e=0b
c
d
a
Variable entered map
Five Variable Maps Five Variable Maps
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 95
Five Variable Maps
1
1
d
11
1
d
1
1
Method 1: Dual maps
e=1 0
e=0
Method 2: Variable entered
1
F = e(abd) + bd + e(abcd)
dd
b
c
d
1
1
a d
1
b
c
d
1
1
d
a 1
1
e=1 0
e=0
ba
ba
1dd
b
c
d
1
1
a d
1
b
c
d
1
1
d
a 1
1
e=1 0
e=0
ba
ba
1dd
F = e(abd) + bd + abcd
John’s solution Tom’s solution
1
e/d1d/e
e
e/d
d/0
1
e/d1d/e
e
e/d
d/0
F = e(abd) + bd + e(abcd)
ba
d
c
Tom says,“The interaction ofd and e is too complex.Use dual maps.”
Slide 48
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 96
Five Variable Maps Five Variable Maps With Don’t Cares
Comment on Slide 48
Five Variable Maps With Don’t CaresMethod 1: Dual 4-variable maps
The extension to 5 variables is straight forward. As before, “d” can be optionally circled like “1”.
Method 2: Variable entered mapsThis is much harder.Some new notation must be devised.
A “d” by itself in a square means a “d” in both the upper and lower levels.
If a “d” is on only one level, the value on the other level must be specified.
“d / e” means “d” on the top level and “1” on the lower (e=1) level.
“e / d” means “1” on the upper level, the e level, and “d” on the lower level.
One must also have “0 / d” and “d /0”
The result is very difficult to circle properly.
However it may be useful if e appears in a very simple way.
Method 3: Split-square mapsA third method for 5 variables would be to use a “/” if thesymbols differed between the levels.
Thus 1/0, 0/1, d/0, d/1, 0/d and 1/d would be introduced.
You can judge if this is an improvement over Method 2. 1
1/d1d/1
1/0
1/d
d/0
ba
cMethod 3 map
Multiple Output Maps Five Variable Maps
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 97
Multiple Output Maps
b
c
d
11
1
1a1
111 b
c
d
11
1
1a1
111
b
c
d
11
1
1a1
111
b
c
d
11
1
1a1
111
Two or more outputsSame inputs
Need two mapsNeed two circuits
Often one can share some gates
ad b
ad
b
c
a
dc
a
dc
ad
c
b
b
b
ad b
ad
c
dc
acb
Map of F Map of G
GF
Find the circuits for F and G
We optimized maps individuallygot one common gate abd.
11 gates37 gate inputs29 letters (literals)
F = a·c·d+bcd
+u+abd+abc
G=b·c·d+acd
+u+abc+acd
u=abd
size measures
13 letters 13 letters
3 letters
Slide 49
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 98
Multiple Output Maps Five Variable Maps With Don’t Cares
Comment on Slide 49
Circuit With Two Outputs
Multiple OutputsThe change between multiple outputs and single outputs
With multiple outputs, one can often find common gates that can be used for both outputs.Often these common gates are not optimum for either individual circuit, but are optimum for the whole circuit.
In the example• In this slide the circuits were optimized individually with a half-hearted effort to find common terms.
• In the next slide, common terms were agressively sought out.
Circuit complexity
There are several ways to estimate the size of the circuit. The same measures also estimate power dissipationwhich is now likely to be more important than size.
• Inverters are not usually counted in the gate count. This is because most will be absorbed when onedoes a AND/OR to NAND/NOR conversion.
• The number of gates.
• The number of gate inputs. This admits that multi-input gates are larger.
• The number of letters on the right hand side of the expressions. This is easy to do, and is usuallyconsidered the best estimate.
Note these are relative estimates; used for estimating if one circuit bigger than another. An exact estimate isusually not needed since modern logic is quite inexpensive. It is like estimating the cost of something as $10.00and quibbiling whether it was really $9.98.
Multiple Output Maps Multiple Outputs, Finding Common Terms
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 99
Multiple Outputs, Finding Common Terms
ad
c
acbc
a
b
c
d
11
1
1a1
111 b
c
d
11
1
1a1
111
b
c
d
11
1
1a1
11
b
c
d
11
1
1a1
111
• Identify common squares on both maps
• Check, sometimes this doesn’t help.
ad b
a
d
b
ca
c
db
b
b
a
c
1
Try to share terms
• Circle common termseven if the individual mapsallow larger circles
• Here changed 3-input AND to 4-inputand removed another 3-input.
Map of F Map of G
F =v+w+u
+abc+abc
G=v+w+u
+acd+ab·c
u=abd
v=a·b·c·d
w=abcd
F
G9 gates33 gate inputs29 letters (literals)
size measuresPrev Thisslide slide293711
acdabc11 gate inputs 11 gate inputs
11 gate inputs
Slide 50
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 100
Multiple Output Maps Multiple Outputs
Comment on Slide 50
Multiple OutputsCollecting the u+v+w terms would reduce the number of letters and gate inputs, but will increase the number ofgates. However the total logic is clearly reduced.
F = abc + abc + x (7 letters, 9 inputs, 3 gates)
G = acd + ab·c + x (7 letters, 9 inputs, 3 gates)
x = a·b·c·d + abcd + abd (11 letters, 14 inputs, 4 gates))
Total: 25 letters, 10 gates, 32 gate inputs
61.• PROBLEM
Find the Σ of Π expressions with minimallogic for the two-output circuit E,F.
Soln has 5 gates.
If it does not have to be pure Σ of Π, it can bedone in 5 two-input gates, or, with factoring,4 gates.
62.• PROBLEM
Find the minimum circuit with the three outputs defined by the maps below. This is a hard problem. You shouldread over the example for the 7-segment display drivers before attempting it. .
X
W
Z
Y
00
01
11
10
00 01 11 10WXYZ
1d1 11
d
d
1
X
W
Z
Y
1 d
00
01
11
10
00 01 11 10WXYZ
1d
d
d1
1
1
E
W
YX
Z
E
F
F
X
W
Z
Y
1
1
X
W
Z
Y
W
Z
Y
11
11 1
11
d1
1
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
1
d11
1
1 1 11
11
1 1
1
1
d
E= F= G=
Multiple Output Maps 7-Segment Display Driver,
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 101
7-Segment Display Driver,
a
b
c
d
e
fg
Digits with “a” lit Digits with “b” lit Digits with “c” lit
Digits with “d” lit Digits with “g” litDigits with “e” lit
ZYXW
WX
Decimal digits displayedDesign this
BCD Digits in binary
00011110
YZWX 00 01 11 10
0000010011001000 1001
110101010001 0011
011111111011 1010
1110011000100000
0100
1000 1001
010100110111 0110
0010
LO
GIC
bafgedc
logic
Digits with “f” lit
Design Driver Logic
YZ
00
01
11
10
00 01 11 10
4 inputs, 7 outputs7 maps, each with 6 don’t cares
Generate MapsChoose segment “a”find all the squareswhere “a” is lit.
Repeat for “b”, “c”, . . .
Slide 51
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 102
Multiple Output Maps Seven-Segment Display Driver
Comment on Slide 51
Seven-Segment Display DriverDesign Example
The slide above, shows the bars in a seven segment display such as is used in many automotive dashboarddisplays, or other bright displays1. All the digits from 0 through nine can be shown by lighting the proper bars.
Design a circuit which takes a binary-coded-decimal (BCD) digit in on leads W,X,Y and Z and sends out theproper signals to light the 7-segment display on leads a, b, c, d, e, f, and g. Binary-coded decimal (BCD) digitsonly go from 0 to 9. The other numbers, 10 through 15 will never be received as inputs. Utilize this fact in yoursolution.
63.• PROBLEM
The digits on the right have a revised form for 1, 7, 6 and 9.
Derive the equations for the display drivers. Keep the same notation for all items thatdo not change.
Minimize the equations for multiple outputs, as is done in the next few pages. If youhave new terms, the letters H, Q, S, T, U and V have not been used.
1. The bright light-emitting diode displays use 7-segments as shown. The dimmer watch and control panel displays are usuallyliquid crystal and have more complex driver logic.
WX\YZ
Revised display
Multiple Output Maps 7-Segment Display Driver,
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 103
Maps for 7-Segment Display Driver
1 1 1 1 1 1 1 1 1 1
1 1 111
11111111
11 1 1 1 1
1
11111
1 1 1 1 1
11 11111
b c
d gfe
a
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1 1 111
1
11111
1 1 1 1 1
11 11111
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1
1
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
Minimization
Digits with “a” lit
Transfer lit segment mapsto Karnaugh maps
Look for isolated “1”s with no neighbors.Look for isolated pairs of “1”s with no neighbors.These will always have to be circled individually.
Expand circles to include “d”
Slide 52
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 104
Multiple Output Maps BCD Display
Comment on Slide 52
BCD Display
Solution to Prob 62.• See also prob 74.• .
1 1 111
1
11111
1 1 1 1 1
11 111111
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1. Locate isolated “1”s.
2. Circle these isolated “1”sIsolated
dd d
ddd
d dddd d
Typical Minimization ProcedureThis should work fairly well as as a general procedure, but a clever person may find more efficient
3. Locate isolated pairs of “1”s in which
procedures for certain problems.
Isolatedpair
These are “1”s in a squarethat cannot be grouped withany other square exceptpossibly a “d” squares.
and expand the circle to include any “d”s.
neither “1” can be paired with another any other square.
4. Circle this pair and expand the circle to include any “d”s.
X
W
Z
Y
1
1
X
W
Z
Y
X
W
Z
Y
11
11 1
11
d1
1
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
1
d11
1
E=W·Y+L G=WX+Z+XYF=WYZ+L
L=YZ+WX·Y+WXZ
1 1 11
11
1 1
1
1 20 letters, 27 gate inputs, 11 gates
d
Multiple Output Maps Maps for 7-Segment Display Driver ,
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 105
Maps for 7-Segment Display Driver ,
1 1 1 1 1 1 1 1 1 1
1 1 111
11111111
11 1 1 1 1
1
11111
1 1 1 1 1
11 11111
b c
d gfe
a
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
MinimizationLook for half-map circles (one letter terms)
These do not require an AND gate.Hence they can always be circled
ZY
fWX
Example: f needs only one AND gatefor three circles
without loss of potential gate sharing.
The green (light) circles are repeats of half-map circles.
On maps “b” and “c”,circle W is redundant
A common error is to add the dashed circle W to the “b” mapand on the “c” map.They are not needed.
Slide 53
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 106
Multiple Output Maps BCD Display
Comment on Slide 53
Maps for 7-Segment Display Driver
5. Locate all circles which, with “d”s if needed, cover half of a map.
Since they only contain a single letter, they do not need an AND gate. The input can feed directly intothe OR gate.There is no advantage to sharing these terms between maps because there is no hardware to share.
1 1 111
1
11111
1 1 1 1 1
11 111111
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1 1 1 1 1 1 1 1 1 111111111
11 1 1 1 1b ca
XW
Z
Y
XW
Z
Y
XW
Z
Yd d
d d
d ddd
ddd d
d dddd d
d dddd d
d dddd d
d dddd d
d dddd d
There are some ten of them in this example.
6. It is easy to overdo this step Two of these circles cover no “1”s that are not covered
Remove such circles. The “b” and “c” maps have such useless circles.by other circles. The only new squares they cover contain “d’s and hence are useless.
Minimization (continued)
Circles that cover half the mapThese are representend by a single letter and are particularly good.
Multiple Output Maps Maps for 7-Segment Display Driver,
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 107
Maps for 7-Segment Display Driver,
1 1 111
1
11111
1 1 1 1 1
11 11111
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1 1 1 1 1 1 1 1 1 111111111
11 1 1 1 1b ca
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
Squares with only one partner: (See arrows )
• Square is isolated on another map.• Square has a different single partner
1
1 111
1
G Hboth partners join other circles.
Single circle if:
Else circle both partners.
on another map, and
They are unlikely to be shareable.
1
1 111
1
G H3 AND gates 4 AND gates
Expand circles to include “d”s; lighter (blue) circles.
“d”s don't count as partners.
One partner squares.
There is no example inthe BCD display maps.
Slide 54
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 108
Multiple Output Maps BCD Display
Display Driver, One Partner Squares
Minimization (continued)
Squares that have one partner
11
11
1
1 1
11 1
1
g
e
X
W
Z
Y
X
W
Z
Y
d dddd d
d dddd d
These squares can be encircled with one and only one other square.
There are two cases, depending on what is at the same position on the other maps“d”s don’t count as a partner.
1 1 111
11
a
XW
Z
Yd dd ddd
1 1 111
1
d
X
W
Z
Yd dddd d
Map “a” has such a square. It can be given a single circleor a double square circle.Looking at map “d” one sees it has to have a singlecircle. It can do double duty if this term, WXYZ,is given a single circle on each map.(
The square matches an isolated square on another map
The pair matches another single partner square.Map “e” has such a square. WXYZ has one possible partner.
Map “g” has such a square. W·XYZ has one possible partner.
On all the other maps where WXYZ =1, it has the samepartner (maps d and g), or is covered already (maps f and c).This means it is not a likely candidate for a single circle.
11
1
1
e
X
W
Z
Y
d dddd d
Circle both partners.Then expand to cover the “d”s.
11
1 1
11 1
g
X
W
Z
Y
d dddd dThe partner works on map “d”, and “b” has another partner.
Circle both partners and expand the circle to cover the “d”s.
There is no example in the BCD display where such term shouldhave only a single circle.
Comment on Slide 54
Multiple Output Maps Maps for 7-Segment Display Driver,
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 109
Maps for 7-Segment Display Driver,
1 1 111
1
11111
1 1 1 1 1
11 11111
d gfe
X
W
Y
X
W
Z
Y
X
W
Y
X
W
Y
1 1 1 1 1 1 1 1 1 111111111
11 1 1 1 1b ca
X
W
Y
X
W
Y
X
W
Y
1
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
Final fill in
11
1
1
e
X
W
Y
3 new AND terms needed
Add terms to cover them
One new term is unique XY
The others (K, L) are reused.
1 1 111
1
11111
1 1 1 1 1
11 11111
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1d d d
ddd
d d dd
dd
d d dd
dd
d d dd
dd
11
1
1
e
X
W
Z
Y
K
1 1 1 1 1 1 1 1 1 111111111
11 1 1 1 1b ca
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
d d dd
dd
d d dd
dd
d d dd
dd
LK
L
Uncovered bits identified as “1”
Slide 55
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 110
Multiple Output Maps BCD Display
Display Driver, Final Fill In
Minimization (continued)
Squares that are left
1 1 111
1
11111
1 1 1 1 1
11 111111
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
1 1 1 1 1 1 1 1 1 111111111
11 1 1 1 1b ca
XW
Z
Y
XW
Z
Y
XW
Z
Yd d
d d
d ddd
ddd d
d dddd d
d dddd d
d dddd d
d dddd d
d dddd d
These squares have little chance of sharing by circling a smaller than optimum circle.
Example: Assume one did not do maps a, b and c, only d, e, f, and g.However keep your eyes open.
Then one would do a two square circle for d, e and f
1 1 111
1
11111
1 1 1 1 1
11 111111
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
d dddd d
d dddd d
d dddd d
d dddd d
For all seven maps, the largest circles appear to be optimum.
If only 4 maps were optimized
However another circling, using smaller circlesmight still be optimum.
1 1 1 111
1 1
b
XW
Z
Yd dddd d
N
R
L
K64.• PROBLEM
Reducing the size of L to L=XYZand adding reusable term R makesall multi-letter terms reusable.
Find the number of letters, gateinputs and gates.
L L
Comment on Slide 55
Multiple Output Maps Maps for 7-Segment Display Driver,
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 111
Maps for 7-Segment Display Driver,
K M 1PN
K
1ML1K
K 1 W W W
11 PXX1P
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
K 1 K 1 X 1 X Y 1 ZX111JLJN
11 1 1 1 1b ca
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
d d dd
dd
Form Equations
1
e
Label AND terms with letters
J = YZ
L = Y·Z
N = XYZ
M = XY
P = YZ
a = J + W + K + N
c = Z + Y + X
d = N + M + P + K
b = J + L + X
e = K + P
f = L + W + X
g = W + M + P + XY
37 letters (literals)
14 gates
38 gate inputs
K = X·Z
Size measures
If one term covers squarereplace “1” by letter
If several terms cover squareleave as “1”.
Only term not reused.
c = f + Z d = e + N + MUsing:
35 letters 14 gates 36 gate inputs
Slide 56
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 112
Multiple Output Maps Display Drivers, Forming Equations
Display Drivers, Forming Equations
J = YZ
L = Y·ZN = XYZ
M = XY
P= YZ
Q M 1PN
Q
1MQPQ
Q 1 W 1 W
11 PXXXXP
d gfe
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
X
W
Z
Y
Q 1 M 1 X 1 X Y Y JX1X1JLJN
W1 1 X Y Yb ca
XW
Z
Y
XW
Z
Y
XW
Z
Y
a = J + W+ Q + M
c = J + Y + Xd = N + M+ P + Q
b = J + L + X
e = Q + Pf = Q + W+ Xg = W+ M + P + X·Y
14+24 literals = 3814 gates16 and gate inputs + 23 or = 39
One way of forming equations is to put a letter like J,K L ... in the square covered by a circle.The one can write the OR inputs for the equation of the map by writing down the letters.
It is very hard to find the optimal circling in a problem of this size.
The equations.
Q = X·Y·Z
To avoid confusion, leave a 1 in squares which are covered by several circles.All letters must appear at least once, or the circle they represent is redundant.
Terms which have only one input like X, do not require a special letter, and we give them the name ofthe input variable.
These maps show a solution which is suboptimal, but you will probably havedifficulty improving without comparing answers.
Comment on Slide 56
Factoring and Multiplying Out Two canonical forms
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 113
Factoring and Multiplying Out
Two canonical formsThese form can represent any Boolean function.
Sum of Products (Σ of Π)abc + ae + ace + abd + . . .
NAND-NAND logic
Product of Sum (Π of Σ) Dual of Σ of Π(a+b+c)(a+e)(a+c+e)(a+b+d)( . . .
NOR-NOR logic
Factoringtransforms Σ of Π → Π of Σ
ab + cad → (a + c)(b + a + d)
Multiplying outtransforms Π of Σ → Σ of Π
(a + c)(b + a + d) → ab + cad
Three Methods of factoring1. Use the 2nd distributive law
x + ab = (x + a)(x + b)
2. Take the dual, multiply out and take the dual again.
3. Plot F on a map and use DeMorgan’s Law
eac
cab
dab
ae
eac
cab
dab
ae
NOR
NAND
Σ of Π(NAND-NAND)
(NOR-NOR)Π of Σ
Slide 57
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 114
Factoring and Multiplying Out Display Drivers, Forming Equations
Factoring and Multiplying Out
Why factor?Often the factored form is about the same complexity as the Σ of Π form, but sometimes it can be much simpler.
Example where the factored form has half the letters and just over half the gate inputs.
a·c·d + a·b·c + abc + acd = (a + c)(b + d)( a + c)
Three methods of factoringUsing (D2)
This is the straightforward way, unfortunately it uses the “unfamiliar” distributive law which makes the algebraharder for many people.
Using duality and (D1)
This is algebraically just as difficult as the previous method. However using the more familiar (D1) makes iteasier for most people.
Using Karnaugh maps
This is quite easy, but is more complex for over five input variables.
Comment on Slide 57
Factoring and Multiplying Out Method 1: Factoring Using (D2) YZ + U =
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 115
Method 1: Factoring Using (D2) YZ + U = (Y + U)(Z + U)
Review
bx + xy + yb
(b + x)(x + y)(y + b)
ExampleABC + X
(AB + X) (C + X)
(A + X)(B + X)(C + X)
ExampleBC + AD
(BC + A) (BC + D)
(B + A) (C + A)(B + D) (C + D)
ExampleBC + BD
(BC + B) (BC + D)
(B + B) (C + B)(B + D) (C + D)
1 (C + B)(B + D) (C + D)
Can reduce further using Consensus (C2)
(C + B)(B + D) (C + D)
= (C + B)(D + B)
BC + BD = (B + C)(B + D)
= bx + yb
= (b + x)(y + b)
Consensus Rules
Use (D2)
Use (D2) again
Use (D2) again
Use (D2) again, twice
Get the Swap Rule
= (B + C)(C + D) (D + B)
ABC + X= (A + X)(B + X)(C + X)
Get extended (D2)
Slide 58
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 116
Factoring and Multiplying Out Factoring Using (D2)
Factoring Using (D2)Review of the thorems that will be used.
The extended (D2) The dual is the extended (D1)
ABC + X = (A + X)(B + X)(C + X) (A + B + C)X = AX + BX + CX
Consensus The dual Consensus
bx + xy + yb = bx + yb (b + x)(x + y)(y + b) = (b + x)(y + b)
Swap rule (Sw) The dual of the Swap rule
BC + BD = (B + C)(B + D) (B + C)(B + D) = BC + BD
65.• PROBLEM
What can you say about the dual of the Swap rule?If you can’t say anything, substitute X for W and X for W.
66.• PROBLEM
Factor AB + BC + CA
Comment on Slide 58
Factoring and Multiplying Out Method 1: Factoring Using (D2) YZ + U =
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 117
Using D2 alone always works, but long!
Review of Rules
xy + x = x
xy + x = y + x
u + yz =
u + xyz =(u + x)(u + y)(u + z)
(u + y)(u + z)Example:ABC + BCD + BF
(B + CD + F)(B + AC)
Simplify (S)
Distributive (D2)
Extended Distributive (D2)
Swap (Sw)
by + bz = (b + y)(b + z)
Shortcut method:(a) Look for common variables and use (D1)
xa + xbc = x(a + bc)(b) Look for complemented variables and use (Sw)
xa + xbc = (x + a)(x + bc)(c) Do simplifications as soon as possible
xa + a = a, x + xy = x + y
BAC + B(CD + F)
Find common variablesChoose B over C
commute Use (D1) with B
Find complimented variablesUse (Sw) with B
(B + F + CD)(B + AC)Ready to use (D2)commute
(B + F + C)(B + F + D)(B + A)(B + C)
(B + C)(B + F + C)= (B + C)(F + C)
This can be reduced
If one expanded using (D2) alone, get(B + A)(F + A + B)(F + A + C)(F + A + D)(B + F + C)(B + F + D)(B + C)(F + C) ugh!
Use (D2) twice
(b + x)(b)=(b + x)
(b + x)(b) = b
(d) Then use (D2)
Reduction (R)
see page below
Slide 59
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 118
Factoring and Multiplying Out Shortcuts for Factoring
Shortcuts for FactoringReason for choosing B over C
There are two common factors B and C.If one factors out C first get C(AB + BD) + BFThen one can only use (Sw) on part of the expression to give C(A + B)(B + D) +BF
This requires about 6 applications of (D2) to get the final result.
Details of the extra reduction
(B + C)(B + F + C)
= C +B(B + F) (D2) (c + x)(c + y) = c + xy
= C + BB + BF (D1)
= (C + B)(C + F) (D2)
The long expression using (D2) alone, except for simplifications
ABC + BCD + BF
= (A + BCD)(B + BCD)(C + BCD) + BF (D2)
= (A + BCD)(B + CD)(C) + BF (Simplification) xy + x = y + x, z + uz = z
= (BF + A + BCD)(BF + B + CD)(BF + C) (extended D2)
= (BF + A + BCD)(F + B + CD)(BF + C) (Simplification) xy + x = y + x
= (B + A + BCD)(F + A + BCD) (F + B + C)(F + B + D) (B + C)(F + C) Use (D2) three times
= (B + A)(F + A + BCD) (F + B + C)(F + B + D) (B + C)(F + C) (Simplification) z + uz = z
= (B + A)(F + A + B)(F + A + C) (F + A + D) (F + B + C)(F + B + D) (B + C)(F + C) (extended D2)
After completing the simplification, you can see why we like the short cuts.
Comment on Slide 59
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 119
Factoring and Multiplying Out Shortcuts for Factoring
Factoring Examples Using Shortcut Methods
67.• PROBLEM:Factor AC + ABD + ABE + A·CDE Five factors, four have 3 letters, one has 2.
Factor WXY + W·XZ + WYZ + WYZ
WXY + WYZ + W·XZ + WYZ
W(XY + YZ) + W(XZ + YZ)
[(W +(Z +Y)(Z + X)][W +Y(X + Z)]
[W +(XZ + YZ)][W +(XY + YZ)]
(W + Z + Y)(W + Z + X) (W + Y)(W + X + Z)
Associative law
(D1) used twice
Swap: w(a) + w(b) = (w + b)(w + a)
Swap on left; (D1) on right
Finally we have to use (D2).
Swap D1
D2 D2
Factor AB·D + ACD + A·C + ABD
A(B·D + CD) + A(C + BD)
[A + (C + BD)][A + (B·D + CD)]
[A + (C + B)(C + D)][A + (B + D)(C + D)]
[A + (C + B)][A + (C + D)][A + (B + D)][A + (C + D)]
(A + C + B)(A + C + D)(A + B + D)(A + C + D)
(D1) on both sides
swap
(D2) on left; swap on right
(D2) on left; (D2) on right
Clean up brackets
Comment on Slide 59
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 120
Factoring and Multiplying Out Shortcuts for Factoring
Example of Multiplying Out
(A + B)(C + D)(F + G + H)
=
All letters are different, no simplification possible
Use (D1)
rewrite
With all the letters different, there is no way to simplify.
= (AC + AD + BC + BD)(F + G + H)
(AC + AD + BC + BD) · F
+ (AC + AD + BC + BD) · G
+ (AC + AD + BC + BD) · H+ (AC + AD + BC + BD) · H
=
ACF + ADF + BCF + BDF
+ ACG + ADG + BCG + BDG
+ ACH + ADH + BCH + BDH
Use (D1)
The expressions get long rapidly.Using (D1) always works, it is easy on the brain, but hard on the pencil.Also the simplifications must be done by other means.
Comment on Slide 60
Factoring and Multiplying Out Multiplying Out
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 121
Multiplying Out
Needed to change Π of Σ to Σ of Π( - - - )( - - - )( - - - ) → ( ) + ( ) + ( )
Multiplying out is the dual operation of factoring.
Multiplying Out Uses (D1)
F BA
D
C
BCD
ABCF
B
A
D
C
BCD
BF
ACD
ACF
ABC
ACD
Example:(B + F + C)(B + C)(B + F + D)(B + A)
= (BB + BC + FB + FC + CB + C)(BB + BA + FB + FA + DB + DA)
= FBBA + FBFB + FBFA + FBDB + FBDA
0
= (FB + C)(BA + FB + FA + DB + DA)
0
+ CBA + CFB + CFA + CDB + CDA)
0
= BF + ABC + ACF + BCD + ACD
= BF + ABC + BCD
x +xy = x
x +xy = x Use D1 twice
Use D1
Put letters in order
Use map
Slide 60
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 122
Factoring and Multiplying Out Shortcuts for Factoring
Example of Multiplying Out
(A + D)(A + C + D)(A + B)(A + B + C)(A + C + D)
= (A + D)(A + B) · (A + C + D )(A + C + D) · (A + B + C)
= (AB + A·D) · [A(C + D) + A(C + D )] · (A + B + C)
= {AB [A(C + D) + A(C + D )] + A·D)[A(C + D) + A(C + D )]} · (A + B + C)
= {AB·C + ABD + A·D·C + A·D)} · (A + B + C)
= {AB(C + D) + A·D(C + D)} · (A + B + C)
BA
D
CAB·C
ABD
A·C·D
{AB·C + ABD + A·D)} · A+ {AB·C + ABD + A·D)} · B+ {AB·C + ABD + A·D)} · C ABDC + A·DC
AB·C + ABD ++ A·DB
ABD
=
= AB·C + ABD + ABD + ACD
=
Arrange terms to ready to use Swap
Use Swap twice
Use (D1)
Use (D1)
xy + x = x
Use (D1)
xy + x = x
Collect terms
Check on mapthat there is no
more simplification
Comment on Slide 60
Factoring and Multiplying Out Multiplying Out
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 123
Using D1 alone eventually works, but long!
Example:
Shortcut method:(a) Look for common variables and use (D2)
(x + a)(x + b) = x + bc(b) Look for complemented variables and use (Sw)
(x + a)(x + bc) = xa + xbc
(c) Do simplifications as soon as possiblexa + a = a, x + xy = x + y
Find common variables
Use (Sw) with B
Use (D2) twice
(d) Then use (D1)
Review of Rules
xy + x = x
xy + x = y + x
u + yz =
u + xyz =(u + x)(u + y)(u + z)
(u + y)(u + z)
Simplify (S)
Distributive (D2)
Extended Distributive (D2)
Swap (Sw)
by + bz = (b + y)(b + z)
(b + x)(b)=(b + x)
(b + x)(b) = b
Reduction (R)
(e) Loop back and try again until done.
(B + F + C)(B + C)(B + F + D)(B + A)
= (B + F + C)(B + F + D) · (B + A)(B + C)
= (B + F + CD) · (B + AC)
= BAC + B(F + CD)
= ABC + BF + BCD
Finally use (D1)
Go back and look at Slide 60
Slide 61
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 124
Factoring and Multiplying Out Shortcuts for Factoring
Multiplying Out
68.• PROBLEM
Multiply out. Remember to check for obvious simplifications before starting.
(W + Y + Z)(X + Y + Z)(W + X)(W + Z)(X + Y + Z)(W + X + Z)
69.• PROBLEM
Multiply out to get four terms of three letters each. The answer should be very symmetric on an AB\CDKarnaugh map.
(B + C)(A + B + C)(A + C + D)(A + B + C)(A + C + D)
Comment on Slide 61
Factoring and Multiplying Out Multiplying Out, Short Cut Method
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 125
Multiplying Out, Short Cut Method
B
A
D
C
CD
BCD
Example:(A + C + D)(B + D)(A + B + C)(C + D)(A + B + D)
= CD + ABD + BCD
0
(x)(x+y) = x
x +xy = x
Rearrange to use (D2) and Swap
Always check for obvious simplifications
= (A + C + D)(B + D)(A + B + C)(C + D)(A + B + D)
= (A + C + D)(A + C + B)(B + D)(C + D)
(A + C + BD) (CD + BD)
(A + C + BD) · CD
+ (A + C + BD) · BD=
Use (D2) and Swap
ACD + CD + BCD
+ ABD + CBD + BDBD
ABD
=Use (D1)
simplifications
Check map for further
= CD + ABD + BC
Collect terms
Slide 62
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 126
Factoring and Multiplying Out Multiplying Out, Short Cuts
Multiplying Out, Short CutsSimplify before you start
You always want to look for (x + ... + y )( x + y) =(x + y)
Reduction and consensus are much harder to spot. Here
(A + C + D)(C + D)
= [C + (A + D)(D)] Using (D2)
= [C + AD]
= (C + A)(C + D)
Further (C + A)(A + B + C) = (C + A)
Hence the expression could be reduced before starting to
(B + D)(C + D)(A + C)
However, it is sometimes easier just to use (D2) and Swap.
Comment on Slide 62
Factoring and Multiplying Out Method 2: Factoring Using Duality
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 127
Method 2: Factoring Using Duality
Recall Factoring Methods:1. Use (D1)
Includes short cuts where one looks for (D2) and Swap first.
2. Use Duality to change factoring to the easier multiplying out.
3. Use Karnaugh Maps and DeMorgan’s Law.
Factoring Using DualitySteps:
(1) The expression to factor is Σ of ΠExample: AB + BC + ACD
(2) Take its dual to get Π of Σ.
(A + B)(B + C)(A + C + D)
(3) Multiply out the dual to get Σ of Π again
BA + BC + BD + AC
(3a) The dual identity is(A + B)(B + C)(A + C + D) = BA + BC + BD + AC
(4) Taking the dual back gives a valid identitywith the desired Π of Σ.
AB + BC + ACD = (B + A)(B + C)(B + D)(A + C)
= (B + AC)(A + C + D)
= BA + BC + BD +ACA + ACC + ACD
= BA + BC + BD + AC
(A + B)(B + C)(A + C + D)(D2)
(D1)
Multiply Out Details
Algebra of one is the
Multiplying out is based on (D1).
Easier than factoring based on (D2).
dual of the other
Slide 63
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 128
Factoring and Multiplying Out Changing Factoring into Multiplying Out
Changing Factoring into Multiplying OutFactoring a Σ of Π is Coverted to Multiplying Out its Dual
We take a factoring problem which is confusing, because factoring is based on (D2). This law is not a normalalgebraic law and is harder to work with.
In the dual space, the dual expression is already factored. The problem is transformed into multiplying out,which is based on the first distributive law (D1). (D1) is more familiar, and hence multiplying out is usuallyeasier than factoring.
Multiplying out in the dual space does not give the answer. One take the dual of the answer. This will then bethe factored form of the original expression.
70.• PROBLEM
Show thatF = A·B·C·D + ABCD +ABCD + ABCD
takes only 8 letters or 12 gate inputs in factored form.
Comment on Slide 63
Factoring and Multiplying Out Factoring Using Duality
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 129
Factoring Using Duality
B
A
D
C
Example:
A·BD + AB·D + ABC + AC
Rearrange to use (D2)
Take dual
Use Swap
Check on map
(A + B + D)(A + B + D)(A + B + C)(A + C)
= [A + (B + D)(B + C)] [A + (B + D)C]
= A (B + D)C) + A(B + D)(B + C)
Use (D2)
= (A + B + D)(A + B + C)(A + B + D)(A + C)
= A (B + D)C) + A(B·C + BD)
= A·BC + A·DC + AB·C + ABD
Use Swap
Use (D1)
(-25% if you say these are equal)
A·BC
AB·C
ABD= A·BC + A·DC + AB·C + ABD
A·DCTake dual
(A + B + C)(A + D + C)(B + C)(A + B + D)
equalequ
al
OK
Slide 64
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 130
Factoring and Multiplying Out Factoring In the Dual Space
Factoring In the Dual SpaceExample
71.• PROBLEM
Factor EF·D + ECD + E·C + EFD
A·BC + ACD + ABC + BCD
BA
D
CAB·C
ABC
(C + A + B)(C + D)(C + B + A)(C + B + A)
To Factor
Note the excess of C and C
Use (D2)
more simplifications
Take the dual
(A + B + C)(A + C + D)(A + B + C)(B + C + D)
rearrange for (D2)= (C + B + A)(C + B + A)(C + A + D)(C + B + D)
= [C + (B + A)(B + A)] · [(C + (A + D)(B + D)]
= C(A + D)(B + D) + C(B + A)(B + A)Use Swap
= C(AB + D) + C(BA + BA)
= CAB + CD + C·BA + CBA
Take the dual ABC
CD
Use Swap
Use (D1)
Check on map forOK
Comment on Slide 64
Factoring and Multiplying Out Method 3: Factoring Using Karnaugh
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 131
Method 3: Factoring Using Karnaugh Maps
Steps:(1) Given F = ( Σ of Π expression)
(2) Plot it on a map.
(3) Make a map for F,It has “1” where F had “0”
(4) Circle the F map
(5) Write out the equation for F
(6) Invert F using DeMorgan’s lawto get F as Π of Σ
F = A·BC + AD + ABC + BCD B
C
D
11 1
1
A1
11
1
Map of F
B
C
D
11
1
1
A
11
11
Map of F
B
C
D
11
1
1
A
11
11
Map of FF = C·D + ABC + AB·D + A·B·C
F = (C + D)(A + B + C)(A + B + D)(A + B + C)
Slide 65
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 132
Factoring and Multiplying Out Method 3: Factoring Using Karnaugh
Method 3: Factoring Using Karnaugh Maps• This method is probably the easiest, and least error prone, for up to 4 variables. Above 4, it gets hard.
• It is very easy to incorporate don’t cares with this method.
72.• PROBLEM
Factor EF·D + ECD + E·C + EFD
Using a Karnaugh map and compare your answer with that from Problem 71.•
73.• PROBLEM
Factor ACD + BD + ABC + CD + ABD
Use a Karnaugh map and obtain the minimum Π of Σ expression.
74.• PROBLEM
Show that Prob 62.• has a slightly simpler solution if you find the Π of Σ expression.
Solution:to Prob 74.•
1
1
X
W
Z
Y
1 1
X
W
Z
Y
1
1
X
W
Z
Y
1 1
1d1
1
1 d
11
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
1
d1
1 1
1
E=YZ+Q+P F=W·Z+Q G=X·Z+M
Q=M+XYZ P=WY
1 111
11
1
E=(Y+Z)Q·P F=(W+Z)Q
M=WXY·Z
G=(X+Z)M
20 letters, 23 gate inputs, 10 gates
X
W
Z
Y
1
1
X
W
Z
Y
W
Z
Y
11
11 1
1
1
d1
1
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
00
01
11
10
00 01 11 10WXYZ
1
d11
1
1 1 11
11
1 1
1
1
d
E= F= G=
Maps from Prob 62.•
Σ of Π solution had 20 letters, 27 gate inputs, and 11 gates.
Comment on Slide 65
Factoring and Multiplying Out Method 3: Factoring Using Karnaugh
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 133
Product of Sum Karnaugh Maps
Simplify the Π of Σ expression
(1) Find Inverse with DeMorgan.
(2) Make a map for F
(3) Simplify the F map
(4) Write out the equation for F
(5) Invert F using DeMorgan’s law
F = ABC + AC·D + BCD + B·D + AC·D B
C
D
1 1
1 1
A1
11
1
Map of F
F = (B + C)(A + B + C)(A + B + D)(B + D)
11
F = (A + B + C)(A + C + D)(B + C + D)(B + D)(A + C + D)
B
C
D
1 1
1 1
A1
11
1
Map of F1
1
F = BC + AB·C + ABD + B·D
to get simplified F
The Σ of Π map for FCan be used as a Π of Σ map for F
Slide 66
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 134
Factoring and Multiplying Out Method 3: Factoring Using Karnaugh
Product of Sum Maps
75.• PROBLEM
Multiply out to get three terms of 2 of three letters, and one of two letters. Use a Karnaugh map.
(B + C)(A + B + C)(A + C + D)(A + B + C)(A + C + D)
00011110
0 1abc
Constructing an AND of ORs map
F = a + b
1
00011110
0 1abc
1
bc
00011110
0 1a
bc
F = c
bc
00011110
0 1abc
F = (a + b)(a + b)c
bc1 11
1 1
11
11
1
11 1
0 0
000
0
F = a + b
00
0 0
00
00
1
The “0”s are the important thing in Π of Σ maps.When one ANDs the three maps, the product map will have a “0” where any of the sum terms have a “0”.The other squares have “1”s.
11
If one multiplies out F = (a + b)(a + b)c, one gets F= abc + abc. 00011110
0 1abc
bc
0 0
000
01
1Which has exactly the same map except now one thinks about the“1”s instead of the “0”s.
Thus the map of F is not quite the Π of Σ map for F.However it can be used as that map.Further using DeMorgan’s theorem on the map of F, is far easierthan twisting ones mind around the Π of Σ maps such as the one above.
True Π of Σ map
Σ of Π map of F
00011110
0 1abc
bc
1 1
111
10
0
Σ of Π map of F
Product map
Comment on Slide 66
Method 3: Factoring Using Karnaugh
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 135
Slide 67
Printed; 11/02/04 Department of Electronics, Carleton UniversityModified; February 11, 2004 © John Knight Digital Circuits p. 136
Method 3: Factoring Using Karnaugh
Solution problem 75
76.• PROBLEM (ACTUALLY SOLN TO 75)
Multiply out to get four terms of three letters each. Use a Karnaugh map.
(B + C)(A + B + C)(A + C + D)(A + B + C)(A + C + D)
B
C
D
11
11
A1
1111
1
F = (B + C)(A + B + C)(A + C + D)(A + B + C)(A + C + D)F = BC + ABC + AC + ABC + A CD
F
B
C
D
11
1
A 1
1
F
1
F = B D + AB C + A B C
Comment on Slide 63