49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions...

25
49 th IEEE Semiconductor Interface Specialists Conference December 5-8, 2018 Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org IEEE SISC 2018 CONFERENCE PROGRAM General Chair: Matthias Passlack Program Chair: Paul McIntyre Arrangements Chair: John Robertson Ex-Officio: Chris Hinkle The abstracts reproduced here are for the use of SISC attendees only. Authors are free to publish any of their work presented in this abstract book. To encourage future participants to submit new and unpublished work, conference policy is that these abstracts may not be referenced. The presentations themselves, which may be significantly different from the associated abstracts, may be cited “as discussed at the 2018 IEEE SISC, San Diego, CA.” © 2018 IEEE SISC SISC 2018

Transcript of 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions...

Page 1: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

IEEE SISC 2018

CONFERENCE PROGRAM

General Chair: Matthias Passlack

Program Chair: Paul McIntyre

Arrangements Chair: John Robertson

Ex-Officio: Chris Hinkle

The abstracts reproduced here are for the use of SISC attendees only. Authors are free to publish any of their work presented in this abstract book. To encourage future participants to submit new and

unpublished work, conference policy is that these abstracts may not be referenced. The presentations themselves, which may be significantly different from the associated abstracts, may be cited “as

discussed at the 2018 IEEE SISC, San Diego, CA.”

© 2018 IEEE SISC

SISC 2018

Page 2: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

Executive Committee

General Chair Program Chair Arrangements Chair Ex-Officio

M. Passlack TSMC

BELGIUM

P. C. McIntyre Stanford U.

CA

J. Robertson Cambridge U.

UK

C. L. Hinkle U. Notre Dame

IN

Secretary: B. Kaczer, imec, BELGIUM

Registration: Suzette Olguin, Hospitality and Conference Services, UCSD, CA

Technical Program Committee

K. S. Chang-Liao, NTHU TAIWAN

E. Lind, Lund U. SWEDEN

C. Fenouillet-Beranger, CEA/LETI FRANCE

T. Oates, TSMC TAIWAN

M. Fischetti, UT Dallas TX

I. Radu, imec BELGIUM

M. M. Frank, IBM NY

M. Reed, Yale U. CT

Y. Kamata, Toshiba JAPAN

P. Stradins, NREL CO

A. C. Kummel, UCSD CA

W.-E. Wang, Samsung TX

V. Le, Intel OR

H. Watanabe, Osaka U. JAPAN

Y.-J. Lee, NAR Labs TAIWAN

J. Wrench, AMAT CA

W. Zhu, U. Illinois IL

SISC 2018

Page 3: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

SISC Ed Nicollian Award for Best Student Paper

In 1995, the SISC began presenting an award for the best student presentation, in honor of

Professor E.H. Nicollian, University of North Carolina at Charlotte. Professor Nicollian was a

pioneer in the exploration of the metal-oxide-semiconductor system, particularly in the area of

electrical measurements. His efforts were fundamental in establishing the SISC in its early years,

and he served as its technical program chair in 1982. With John Brews, he wrote the definitive

book, “MOS Physics and Technology,” published by Wiley Interscience.

The SISC Ed Nicollian Award for Best Student Paper is presented to the lead student author for

either an oral or a poster presentation. The winner is chosen by members of the technical

program committee at the end of the SISC. The award consists of a plaque, an honorarium, and a

permanent mention on the conference web site.

Winner of the 2017 SISC Ed Nicollian Award for Best Student Paper:

Mahmut Sami Kavrik

UCSD

“Ultra-Low Defect Density sub 0.5 nm HfO2/SiGe Interface Formation via Al Gettering Gate”

with E. Thomson, E. Chagarov, A. Betts, K. Tang, P. C. McIntyre, Q. Wang, M. Kim,

and A. C. Kummel

SISC 2018

Page 4: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

Wednesday Evening Tutorial

Wednesday, December 5, 2018, 8:00 PM

First introduced at SISC 2008, the Wednesday evening Tutorial aims to provide a good foundation in a topic frequently covered at the conference, particularly benefiting students and newcomers to the field. The Tutorial is free to all registered SISC attendees.

Prof. Philippe Vereecken, U. Leuven and imec

Solid-state batteries—a story about interfaces

Lithium ion batteries (LIB) dominate the portable electronics market and are the battery technology of choice for hybrid and plug-in electrical vehicles. Lithium ion battery packs have also made their debut for local storage in homes. Currently, the electric vehicle market is the main driver for advancement in LIB technology. Yet, rechargeable batteries in different forms will be a key component and enabler for many future technologies, ranging from small wireless autonomous sensors for the internet of things to storage of renewable energy in the smart grid.

Battery R&D is typically focused on material innovation; i.e. the search for novel cathode and anode chemistries, improvements in design through nanotechnology and optimization of the liquid electrolyte chemistry. However, battery issues such as limited lifetime and charging rates are primarily related to poorly controlled interfaces and to the use of liquid electrolytes. Solid electrolytes are being explored to replace the flammable liquid electrolyte. Next to solving the issues with safety, the transition to a solid-state electrolyte would mean significant improvements in the battery performance as well: higher energy density, longer battery life time and wider temperature range of operation. The solid-state concept allows direct integration of the battery with microsystems such as sensors or implants. For these micro-batteries, CMOS materials and processing can be (re)used. However, ideas for innovation in large scale battery technology can also come from the IC industry, where the downscaling of the transistor has driven tremendous research efforts into new materials and the understanding of charge transport and interfaces. For example, in CMOS technology interfaces are controlled at the atomic scale in contrast to the sometimes micron thick interfacial layers which exist in batteries due to decomposition of electrode and liquid electrolyte.

SISC 2018

Page 5: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

In this tutorial, we will first introduce the main drivers to go solid-state and the projected roadmaps for the introduction of these next generation Li-ion batteries in electric vehicles. We will review the different solid-state battery contenders in the race and differentiate between thin-film micro-batteries and large capacity particle-composite batteries. Thin-film solid-state batteries have been available already commercially for some time as solid electrolyte materials with ionic conductivities in the order of micro-Siemens are sufficient for the short distance across the sub-micrometer thin-films. For large capacity batteries, however, where the distance between the current collectors can be several hundreds of microns, materials with ion conductivities in the range of milli-Siemens are required instead. Solid electrolytes with such high ion conductivities have been discovered only very recently and work on integration of these electrolytes in solid-state cells is currently ongoing. Some of the integration routes, their issues and needed material solutions will be discussed. The use of thin-film coatings and interface engineering will be highlighted. At imec, we are using a thin-film platform to investigate and engineer solutions for interface related issues. We are developing solid nanocomposite electrolytes where the ion conductivity is tailored through interface conduction. Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects but helps us to engineer novel electrolyte materials. Finally, we will look at examples where the solid-state and thin-film know-how is transferred to particle-based systems for large capacity cells.

Page 6: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

Conference Agenda Overview Wednesday, December 5, 2018

Registration ............................................................................................................. 6:00 PM – 8:00 PM Evening tutorial ...................................................................................................... 8:00 PM – 9:30 PM Hospitality room ..................................................................................................... 9:30 PM – 12:00 AM

Thursday, December 6, 2018 Registration ............................................................................................................. 8:00 AM – 5:00 PM Keynote .................................................................................................................... 8:00 AM – 8:45 AM Session 1: Interfaces and Materials for High Performance Devices .................. 8:45 AM – 10:00 AM Session 2: Atomic Layer Deposition & Selective Processes ................................ 10:20 AM – 12:10 PM Session 3: Poster Preview Session I – High-k Dielectrics and

High Mobility Channels .................................................................................... 1:30 PM – 2:05 PM Session 4: Ferroelectrics I: FETs and NC ............................................................ 2:05 PM – 3:40 PM Session 5: Poster Preview Session II: Interfaces, Materials and Devices .......... 4:05 PM – 5:15 PM Poster Session 1 & Reception ................................................................................ 7:00 PM – 10:00 PM Hospitality room ..................................................................................................... 10:00 PM – 12:00 AM

Friday, December 7, 2018 Registration ............................................................................................................. 8:00 AM – 12:00 PM Session 6: 2D Transition Metal Dichalcogenides ................................................. 8:00 AM – 9:40 AM Session 7: Poster Preview Session III: 2D Materials and Ferroelectrics ........... 9:40 AM – 10:15 AM Session 8: Low-D Semiconductors & Novel FETs ............................................... 10:40 AM – 12:00 PM Committee / Invited Speaker luncheon ................................................................ 12:00 PM – 1:30 PM Session 9: SiGe and Ge MOS................................................................................. 1:30 PM – 3:15 PM Poster Session 2 & Coffee break ........................................................................... 3:15 PM – 4:45 PM Session 10: Ferroelectrics II, Materials and Devices ........................................... 4:45 PM – 6:05 PM Conference banquet and Limerick contest .......................................................... 7:00 PM – 10:00 PM Hospitality room ..................................................................................................... 10:00 PM – 12:00 AM

Saturday, December 8, 2018 Session 11: Interfaces in Solar and Optoelectronic Devices ............................... 8:00 AM – 9:55 AM Session 12: Wide Band-Gap Semiconductors ...................................................... 10:20 AM – 12:00 PM Session 13: Memory ............................................................................................... 1:30 PM – 3:15 PM

SISC 2018

Page 7: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

Conference Program

Wednesday, December 5, 2018

Tutorial

Session Chair: P. C. McIntyre

8:00 PM – 9:30 PM Tutorial - Solid State Batteries, P. Vereecken1,2, 1U. Leuven, Belgium, 2imec, Belgium

9:30 PM – 12:00 AM Hospitality room

Thursday, December 6, 2018 8:00 AM Welcome and opening remarks 8:10 AM Keynote - Interfaces for CMOS bioelectronics, K. Shepard, Columbia U.

Session 1: Interfaces and Materials for High Performance Devices

Session Chair: M. Passlack

8:45 AM 1.1 Invited - Future Scaling of Advanced Logic Devices, H. Bu, IBM 9:20 AM 1.2 - GdAlO3: a promising high-k dielectric for reliable gate stacks at low

thermal budget, D. Claes1,2, J. Franco1, N. Collaert1, D. Linten1, and M. M. Heyns1,2, 1imec, Belgium, 2U. Leuven, Belgium

9:40 AM 1.3 - Improvement of InGaAs interface properties by H2O-based La2O3, R. Suzuki1, S. Yoshida1, T. Sasaki1, I. Oshiyama1, T. Hirano1, M. Saito1, K. Ohno1, H. Iwamoto1, J. Franco2, V. Putcha2, D. Cott2, S. Sioncke2, A. Vais2, and N. Collaert2, 1Sony, Japan, 2imec, Belgium

10:00 AM Coffee break

SISC 2018

Page 8: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Session 2: Atomic Layer Deposition & Selective Processes

Session Chair: J. Wrench

10:20 AM 2.1 Invited - ALD for Semiconductor Interfaces, G. Wilk, ASM America 10:55 AM 2.2 Invited - Surface Processes for Selective Atomic Layer Deposition, S. F.

Bent, Stanford U. 11:30 AM 2.3 - Hyper-Selective Co Metal ALD on Cu and Pt Without Passivation, S.

Wolf, M. Breeden, S. Ueda, A. C. Kummel, UCSD 11:50 AM 2.4 - Selective Etching of Native Silicon Oxide and Flowable SiO2 in Preference

to Silicon, Thermal Silicon Oxide and Silicon Nitride, C. F. Ahles1, J. Y. Choi1, R. Hung2, N. Kim2, S. Nemani2, and A. C. Kummel1, 1UCSD, 2Applied Materials

12:10 PM Adjourn for lunch

Session 3: Poster Preview Session I – High-k Dielectrics and High Mobility Channels

Session Chair: A. C. Kummel

1:30 PM 3.1 - Electron Mobility Enhancement by Tensile Strain in Germanium Nanowire NFETs considering surface roughness, channel dopant charge, interface charge, and phonon scattering, Hung-Yu Ye1Chia-Che Chung1, and C. W. Liu1,2, 1National Taiwan U., Taiwan, 2National Nano Device Laboratories, Taiwan

1:32 PM 3.2 - Correlation of interface state generation and InGaAs MOS interface properties, S.-H. Yoon, D.-H. Ahn, C. Yokoyama, M. Takenaka, and S. Takagi, U. Tokyo, Japan

1:34 PM 3.3 - High-mobility P- and N-channel GeSn Thin-film Transistors on Transparent Substrate Fabricated by Nucleation-controlled Liquid-phase Crystallization, T. Hosoi, H. Oka, K. Inoue, Y. Wada, T. Shimura, and H. Watanabe, Osaka U., Japan

1:36 PM 3.4 - Effect of incorporating Hf atoms in AlON gate dielectrics on hole leakage current, T. Nagura1, K. Chokawa1, M. Araidai1, T. Hosoi2, H. Watanabe2, A. Oshiyama1, and K. Shiraishi1, 1Nagoya U., Japan, 2Osaka U., Japan

1:38 PM 3.5 - Investigation of dipole origin at high k dielectric hetero-junction interface, L. Zhou, X. Wang, J. Xiang, C. Zhao, T. Ye, and W. Wang, Chinese Academy of Sciences, China

1:40 PM 3.6 - Simulation of Mobility Degradation by Interfacial Dipole in Gate Stack of Ge pMOSFET, X. Wang, L. Zhou, X. Ma, J. Xiang, and W. Wang, Chinese Academy of Sciences, China

Page 9: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

1:42 PM 3.7 - Modulation of InGaAs MOSCAP Interface State Density across the Band-Gap and Direct Correlation with MOSFET Sub-Threshold Swing down to 65 mV/decade, J. Rozen1, E. A. Cartier1, T. Ando1, M. M. Frank1, K.-T. Lee1, P. Kerber1, J.-B. Yau1, E. P. O’Connor2, Y. Ogawa3, M. Hatanaka3, and V. Narayanan1, 1IBM, 2IBM, Switzerland, 3ULVAC Inc., Japan

1:44 PM 3.8 - Further investigation of Fermi-level pinning on Ge from substrate side, T. Nishimura, X. Luo, T. Yajima, and A. Toriumi, U. Tokyo, Japan

1:46 PM 3.9 - Observation of Anomalous Bias Temperature Instability in Hf0.5Zr0.5O2-based Germanium Ferroelectric Nanowire pFETs, W. Chung, M. Si, and P. D. Ye, Purdue U.

1:48 PM 3.10 - Investigation of post deposition annealing on hole mobility of Ge pMOSFET, L. Zhou, X. Wang, J. Xiang, C. Zhao, T. Ye, and W. Wang, Chinese Academy of Sciences, China

1:50 PM 3.11 - Stabilization of Dielectric Layers on Germanium, L.P. Etcheverry and C. Radtke, UFRGS, Brazil

1:52 PM 3.12 - EOT scaling of MOSCAPs on etched (100)- and (110)-oriented In0.53Ga0.47As layers via a TiN capping layer insertion, Y.-C. Fu1, D. Millar1, X. Li1, M. Steer1, U. Peralagu1, H. Zhou1, R. Droopad2, and I. G. Thayne1, 1U. Glasgow, UK, 2Texas State U.

1:54 PM 3.13 - Transport mechanisms in Al2O3 and HfO2 MIG structures with Si-nanosized electrodes, C. A. Chavarin1, M. Junige2, M. Lukosius1, J. Kitzmann1, M. Albert2, J. W. Bartha2, and C. Wenger1, 1IHP GmbH, Germany, 2TU Dresden, Germany

Session 4: Ferroelectrics I – FETs and NC

Session Chair: P. C. McIntyre

2:05 PM 4.1 Invited - Quasi-Static Negative Capacitance (QSNC): Science Fact or Science Fiction?, T. P. Ma, Yale U.

2:40 PM 4.2 - Sense and non-sense of negative capacitance in ferroelectric devices, J. Van Houdt, 1imec, Belgium, 2U. Leuven, Belgium

3:00 PM 4.3 - On the Diminished Hysteresis Observed in Ferroelectric-gated FET’s (FeFET’s) Attributed to the Negative Capacitance Effect, Z. Liu and T. P. Ma, Yale U.

3:20 PM 4.4 - A Ferroelectric Semiconductor Field-Effect Transistor with ALD Passivation, M. Si and P. D. Ye, Purdue U.

3:40 PM Coffee break

Page 10: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Session 5: Poster Preview Session II – Interfaces, Materials and Devices

Session Chair: J. Robertson

4:05 PM 5.1 - Digital and Analog Resistive Switching Characteristics under 200 nA Current Level using Novel Ni/SiOx/W 16×16 Cross-point Architecture, S. Samanta, K. Han, S. Xu, X. Gong, and X. Fong, NUS, Singapore

4:07 PM 5.2 - Surface and Bulk Carrier Transports in Accumulation-mode GaN MOSFETs, N. Taoka1, N. H. Trung1, H. Yamada1, T. Takahashi1, T. Yamada1, T. Kubo2, T. Egawa2, and M. Shimizu1,3, 1AIST, Japan, 2Nagoya Institute of Technology, Japan, 3Nagoya U., Japan

4:09 PM 5.3 - Electron States in Ovonic Switching GexSe1-x (0.4 < x <0.72) Films, V. V. Afanas’ev1, N. S. Avasarala2, L. Goux2, G. S. Kar2, M. Houssa1, and A. Stesmans1, 1U. Leuven, Belgium, 2imec, Belgium

4:11 PM 5.4 - Applications of amorphous Ga2O3 deposited by pulsed laser deposition and sputtering at room temperature, M. I. Pintor-Monroy1, B. L. Murillo-Borjas1, G. A. Velázquez-Nevárez2, and M. A. Quevedo-Lopez1, 1UT Dallas, 2Instituto Politécnico Nacional, Mexico

4:13 PM 5.5 - DFT Study on Atomic and Electronic Structures of SiC/SiO2 after NO Annealing, T. Ono, U. Tsukuba, Japan

4:15 PM 5.6 - Self-Assembled Monolayers (SAMs) for Hyperselective Silicide, Metal, and Interconnect Diffusion Barrier, M. Breeden, J. Choi, S. Wolf, C. F. Ahles, and A. C. Kummel, UCSD

4:17 PM 5.7 - Storing Electric Charge Mechanism of the Potassium Ion Electret Used for New Types of Vibration Power Generation Devices, T. Miyajima, M. Araidai, and K. Shiraishi, Nagoya U., Japan

4:19 PM 5.8 - One Charge per Cycle Observed in Strong Inversion/Accumulation Charge-Pumping, K. P. Cheung1, C. Wang2, and J. P. Campbell, 1NIST, 2Dalian U. Technology, China

4:21 PM 5.9 - Effects of Forming Gas Anneal on Electrical Properties of ALD-Al2O3/AlGaN/GaN MIS-HEMTs, T. Kubo, K. Furuoka, M. Miyoshi, and T. Egawa, Nagoya Institute of Technology, Japan

4:23 PM 5.10 - Graphene Nanopore Transistor for Damaged DNA Detection, N. B. Athreya, O. Milenkovic, and J.-P. Leburton, UIUC

4:25 PM 5.11 - Formation of Electronically And Chemically Passive Termination on PbSe Quantum Dot Superlattices, S. T. Ueda1, I. Kwak1, S. Wolf1, M. Breeden1, A. Abelson2, C. Qian2, M. Law2, and A. C. Kummel1, 1UCSD, 2UC Irvine

4:27 PM 5.12 - Characterization of excess carbon near 4H-SiC/SiO2 interface and its spatial distribution across the interface, Y. Terao, T. Hirose, H. Teranishi, H. Sato, and A. Takigawa, Fuji Electric Co., Japan

4:29 PM 5.13 - 3D TSV Transistor with Ru Metal Gate, F. Winkler1, S. Killge1, M. Pesic2, and J. W. Bartha1, 1TU Dresden, Germany, 2MDLsoft Inc.

Page 11: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

4:31 PM 5.14 - Breakdown Voltage of AlGaN/GaN HEMTs with Low-k/High-k Double Passivation Layers, K. Nakano, H. Hanawa, and K. Horio, Shibaura Institute of Technology, Japan

4:33 PM 5.15 - Schottky Barrier Height Tuning on Platinum-gated ZnO Metal-Semiconductor Field Effect Transistors by In-Situ Surface Modification, R. A. Rodriguez-Davila, R. A. Chapman, I. Mejia, M. A. Quevedo-Lopez, and C. D. Young, UT Dallas

4:35 PM 5.16 - High Improvement On The Threshold Voltage Of E-Mode GaN HEMTs with AlGaN Buffer Layer, G. Kurt, M. Ozturk, M. E. Gulseren, S. Ural, O. A. Kayal, B. Butun, M. Kabak, and E. Ozbay, Bilkent U., Turkey

4:37 PM 5.17 - Normally-off p-GaN Gate InAlN/GaN HEMT with Gradual p-GaN Surface Etch, M. E. Gulseren, B. Bozok, G. Kurt, O. A. Kayal, M. Ozturk, S. Ural, B. Butun, and E. Ozbay, Bilkent U., Turkey

4:39 PM 5.18 - Microstructure Investigation of SiOx Layer in Poly-Si/SiOx Passivated Contacts for Silicon Solar Cells, A. S. Kale1, B. Nemeth2, S. U. Nanayakkara2, H. Guthrey2, A. Norman2, M. R. Page2, M. Al Jassim2, S. Agarwal1, and P. Stradins2, 1Colorado School of Mines, 2NREL

4:41 PM 5.19 - Eu2O3 dielectric layers on GaN(0001) Controlling the Structural Polymorph – from hexagonal to monoclinic, T. Hadamek1, D. Shin1, P.-Y. Chen1, A. Posadas1, S. Kwon2, Q. Wang2, M. Kim2, J. Ekerdt1, and A. A. Demkov1, 1UT Austin, 2UT Dallas

4:43 PM 5.20 - Internal Photoemission Spectroscopy Study of Barrier Heights between Ta-based Amorphous Metals and Atomic Layer Deposited Insulators, M. A. Jenkins, J. M. McGlone, J. F. Wager, and J. F. Conley Jr, Oregon State U.

4:45 PM 5.21 - Design Considerations with Augmented Spacer Dielectric for Vertically Stacked Gate-All-Around MOSFET, Y.-C. Huang, S.-H. Chen, M.-H. Chiang, and S.-J. Wang, National Cheng Kung U., Taiwan

4:47 PM 5.22 - Suppression of VFB instability in AlSiO/GaN MOS capacitor with crystallized interlayer, D. Kikuta1, K. Mitsuishi2, K. Ito1, T. Narita1, Y. Irokawa2, T. Nabatame2, and T. Kachi3, 1Toyota, Japan, 2National Institute for Materials Science, Japan, 3Nagoya U., Japan

4:49 PM 5.23 - TiO2-IrOx Alloy as a Hole Transport Material for Perovskite Solar Cells, W. Tan, O. L. Hendricks, A. C. Meng, M. Braun, M. D. McGehee, C. E. D. Chidsey, and P. C. McIntyre, Stanford U.

4:51 PM 5.24 - Impact of Interface Roughness on Quantum Transport in Double Gate MOSFETs, P. B. Vyas, M. L. Van de Put, and M. V. Fischetti, UT Dallas

4:53 PM 5.25 - Influence of Deposition Temperature on Passivation and Fixed Charge Stability of Atomic Layer Deposited Aluminum Oxide on Silicon, N. C. Strandwitz, R. J. Marstell, and B. Davis, 1Lehigh U.

4:55 PM 5.26 - The effect of an in-situ atomic layer deposited aluminium nitride interlayer between a N2 treated GaN surface and aluminium oxide on GaN MOS capacitors, D. T. Hemakumara1, X. Li1, K. Floros1, S.-J. Cho1, I. Guiney2, D. Moran1, C. Humphreys2, A. O’Mahony3, H. Knoops3, and I. G. Thayne1, 1U. Glasgow, UK, 2U. Cambridge, UK, 3Oxford Instruments, UK

Page 12: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

4:57 PM 5.27 - Hydrophilic Crystalline Nanoparticles Based Ultrasensitive MRI Contrast Agents, J. Wang, J. Flores, S. L. Blair, W. C. Trogler, and A. C. Kummel, UCSD

4:59 PM 5.28 - Effects of Processing Sequence and Ambient Conditions on Doped Polysilicon / Tunneling SiOx Passivated Contact Stack for Silicon Photovoltaics, B. Nemeth, D. L. Young, M. R. Page, V. LaSalvia, D. Findley, A. S. Kale, S. Theingi, S. P. Harvey, and P. Stradins, NREL

5:01 PM 5.29 - Modification of chemical Si-surface cleaning with vacuum treatment, J.-P. Lehtiö1, Z. J. Rad1, M. Yasir1, J. Mäkelä1, M. Kuzmin1, E. Vuorinen1, M. P. J. Punkkinen1, P. Laukkanen1, K. Kokko1, R. Punkkinen1, H.-P. Hedman1, P. Repo2, and H. Savin2, 1U. Turku, Finland, 2Aalto U., Finland

5:03 PM 5.30 - Hybrid dielectric films containing conducting nanoparticles, M. Wiesinger, T. Welzel, and M. Stutzmann, TU München, Germany

5:05 PM 5.31 - Investigation of the deviation of threshold voltage of low-temperature polycrystalline silicon TFTs depending on the grain configuration and channel length, K.-H. Kim1,2, J.-Y. Lee2, and B.-D. Choi1, 1SKKU, Korea, 2Samsung, Korea

5:07 PM 5.32 - Simulation Study of Channel Length Scaling in Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistors, A. Saadat1, M. L. Van de Put1, H. Edwards2, and W. G. Vandenberghe1, 1UT Dallas, 2Texas Instruments Inc.

5:09 PM 5.33 - Growth of crystalline bismuth oxide thin film on Si(100), M. Yasir1, M. Kuzmin1,2, Z. J. Rad1, M. P. J. Punkkinen1, J. Mäkelä1, P. Laukkanen1, and K. Kokko1, 1U. Turku, Finland, 2Ioffe Physical-Technical Institute, Russia

5:15 PM Adjourn 7:00 PM Poster Session 1 & Reception 10:00 PM – 12:00 AM Hospitality room

Page 13: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Friday, December 7, 2018

Session 6: 2D Transition Metal Dichalcogenides

Session Chair: C. L. Hinkle

8:00 AM 6.1 Invited - Investigating Interface States and Border Traps in the Oxide/MoS2 System, P. K. Hurley1, P. Zhao2, P. Bolshakov2, G. Mirabelli1, E. Caruso1, F. Gity1, S. Monaghan1, J. Lin1, L. Walsh1, K. Cherkaoui1, C. M. Smyth2, A. Khosravi2, A. Azcatl2, C. L. Hinkle2, R. M. Wallace2, and C. D. Young2, 1Tyndall National Institute, Ireland, 2UT Dallas

8:35 AM 6.2 - Contact resistance at 1T-MoS2/2H-MoS2 lateral heterojunctions, M. Houssa1, K. Iordanidou2, A. Dabral3, A. Lu4, G. Pourtois3, V. V. Afanas’ev1, and A. Stesmans1, 1U. Leuven, Belgium, 2U. Oslo, Norway, 3imec, Belgium, 4AIST, Japan

8:55 AM 6.3 - Hole-Injection at WO3-WSe2 Interface Using a Plasma Oxidation Process for Hole Mobility Enhancement and SBH reduction in p- type 2-D WSe2 Nanosheet FET, M. Sivan, Y. Li, Y. Zhao, and A. V.-Y. Thean, NUS, Singapore

9:15 AM 6.4 - Tuning the Electrical Transport Properties of Few-Layer MoTe2 by Phase Engineering, L. Yang, H. Wu, X. Lou, Z. Xie, X. Yu, H. Chang, and W. Zhang, Huazhong U. Science and Technology, China

Session 7: Poster Preview Session III – 2D Materials and Ferroelectrics

Session Chair: W. Zhu

9:40 AM 7.1 - A key role of doping to HfO2 for ferroelectric phase formation, Y. Mori1, T. Nishimura1, S. Migita2, and A. Toriumi1, 1U. Tokyo, Japan, 2AIST, Japan

9:42 AM 7.2 - Synthesis and Characterization of Monolayer WSe2-2xTe2x, A. Sharma, K. Xu, S. Kang, S. Xia, R. Haasch, and W. Zhu, UIUC

9:44 AM 7.3 - Cooling-mediated One-step Synthesis of Monolayer WSe2/WSe2xTe2-2x Lateral Heterostructures for Photodetector Applications, S. Kang, S. Xia, Z. Zhao, A. Sharma, and W. Zhu, UIUC

9:46 AM 7.4 - Contact Engineering for Dual-Gate MoS2 Transistors with O2 Plasma Exposure, P. Bolshakov1, C. M. Smyth1, A. Khosravi1, P. Zhao1, A. Azcatl1, G. Mirabelli2, P. K. Hurley2, C. L. Hinkle1, R. M. Wallace1, and C. D. Young1, 1UT Dallas, 2Tyndall National Institute, Ireland

9:48 AM 7.5 - Understanding Ferroelectricity of doped-HfO2 for the NC-FET, P. Blaise1, B. Sklénard1, N. Vaxelaire1, O. Renault1, T. Miyashita2, K. Wong2, and N. Kim2, 1CEA/LETI, France, 2Applied Materials

9:50 AM 7.6 - Ge 2D Crystal Growth on Hetero-epitaxial Ag/Ge(111) by N2 Annealing, A. Ohta, K. Ito, M. Kurosawa, M. Araidai, M. Ikeda, K. Makihara, and S. Miyazaki, Nagoya U., Japan

Page 14: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

9:52 AM 7.7 - ESR study of transferred MoS2 layers grown by MOCVD: evidence for the Mo vacancy, A. Stesmans1, B. Schoenaers1, A. Leonhardt2, D. Chiappe2, I. Asselberghs2, C. Huyghebaert2, I. Radu2, S. De Gendt2, M. Houssa1, and V. V. Afanas’ev1, 1U. Leuven, Belgium, 2imec, Belgium

9:54 AM 7.8 - Probing the role of substrate chemistry and interface interactions on MoS2, A. Leonhardt1,2, N. Pellens2, D. Chiappe1,3, J. Ludwig1,2, I. Shlyakhov2, V. V. Afanas’ev2, S. Brems1, I. Asselberghs1, C. Huyghebaert1, I. Radu1, and S. De Gendt1,2, 1imec, Belgium, 2U. Leuven, Belgium, 3ASM Microchemistry Ltd., Finland

9:56 AM 7.9 - Modulating the barrier height in 2D materials for reduced contact resistance, S. Suryavanshi1, P. Blaise2, and E. Pop1, 1Stanford U., 2CEA/LETI, France

9:58 AM 7.10 - Ferroelectric Zr-doped Hafnium Oxide for Memory Applications, H. Ryu, K. Xu, D. Kim, F. Rao, and W. Zhu, UIUC

10:00 AM 7.11 - Effects of total ionizing dose radiation on Hf0.5Zr0.5O2-based ferroelectric capacitors, M. A. Bhuiyan1, M. Si2, P. D. Ye2, and T. P. Ma1, 1Yale U., 2Purdue U.

10:02 AM 7.12 - Analog resistance tuning in TiN/HfO2/TiN ferroelectric tunnel junctions, M. M. Frank, E. A. Cartier, K.-L. Lee, A. Carr, C. Lavoie, J. Bruley, and V. Narayanan, IBM

10:04 AM 7.13 - Ferroelectricity in Hafnia: a Molecular Dynamics Study, Z. Song1,Y. Guo2, and J. Robertson1, 1U. Cambridge, UK, 2Swansea U., UK

10:06 AM 7.14 - Fermi level de-pinning of contacts to MoS2 – MIGS or Defects?, S. Zhang1, Y Guo2, and J. Robertson1, 1Cambridge U., UK, 2Swansea U., UK

10:08 AM 7.15 - Graphene-Semiconductor Interface Characterizes via Terahertz 3D Imaging, A. Rahman, Applied Research and Photonics, Inc.

10:10 AM 7.16 - Impact of the Annealing Temperature on C-V Characteristics of Ferroelectric HfZrOx on a p-type Si Substrate, Y.-H. Chen1, C.-J. Su2, C. Hu1,3, and T.-L. Wu1, 1National Chiao Tung U., Taiwan, 2National Nano Device Laboratories, Taiwan, 3UC Berkeley

10:12 AM 7.17 - Ferroelectric Characteristics of Hf0.5Zr0.5O2-based Metal-Ferroelectric-Insulator-Semiconductor Capacitors for Steep-Slope transistor Applications, J. H. Roh, H. W. Park, Y. B. Lee, S. D. Hyun, K. D. Kim, T. H. Moon, Y. H. Lee, B. S. Kim, B. Y. Kim, H. H. Kim, and C. S. Hwang, Seoul National U., Korea

10:15 AM Coffee break

Session 8: Low-D Semiconductors & Novel FETs

Session Chair: I. Radu

10:40 AM 8.1 - High-Mobility (> 700 cm2/V-s) Helical Tellurium Field Effect Transistors Enabled by Transfer-Free, Low-Temperature (120 °C) Direct Growth, G. Zhou1, R. Addou1, Q. Wang1, S. Honari1, C. R. Cormier1, L. Cheng1, R. Yue1, C. M. Smyth1, A. Laturia1, J. Kim1, W. G. Vandenberghe1, M. J. Kim1, R. M. Wallace1, and C. L. Hinkle1,2, 1UT Dallas, 2U. Notre Dame

Page 15: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

11:00 AM 8.2 - High performance black phosphorus top-gate transistors with alucone dielectrics, X. Li, X. Xiong, T. Li, and Y. Wu, Huazhong U. Science and Technology, China

11:20 AM 8.3 - Vertically Stacked Poly-Si Nanosheet P-channel Junctionless Field-Effect Transistors with Gate All Around Structure, Yung-Chun Wu*, Kang-Hui Peng, Meng-Ju, Tsai, Yu-Ru Lin, National Tsing Hua U., Taiwan

11:40 AM 8.4 - EOT scaling of planar-type InGaAs TFETs by using W/ZrO2/Al2O3 gate stacks, D.-H. Ahn, S.-H. Yoon, K. Kato, T. Fukui, M. Takenaka, and S. Takagi, U. Tokyo, Japan

12:00 PM Adjourn for lunch 12:00 PM – 1:30 PM Committee/Invited Speaker luncheon

Session 9: SiGe and Ge MOS

Session Chair: Y.-J. Lee

1:30 PM 9.1 - Selective surface oxidation with periodic ozone dosing into HfO2 on SiGe for SiOx interface, M. S. Kavrik1, V. Hou2, E. Rotenberg3, A. Bostwick3, K. Tang4, Y. Taur1, P. C. McIntyre4, and A. C. Kummel1, 1UCSD, 2TSMC, Taiwan, 3Lawrence Berkeley Laboratory, 4Stanford U.

1:55 PM 9.2 - Reduction in interface trap density of TiN/Y2O3/Si0.62Ge0.38 gate stacks with high temperature PMA, T.-E. Lee, M. Ke, K. Kato, M. Takenaka, and S. Takagi, U. Tokyo, Japan

2:15 PM 9.3 - Notable Difference between Rapid-Thermal and Microwave Annealings on Ge pMOSFETs, S.-H. Yi, K.-S. Chang-Liao, C.-W. Hsu, J.-S. Li, W.-Y. Hsu, and T.-Y. Wu, National Tsing Hua U., Taiwan

2:35 PM 9.4 - Mechanism of Ohmic Contacts on Sb- and Bi-based layers on Si and Ge, Y. Guo1,2, H. Zhang1,3, and J. Robertson1, 1Cambridge U., UK, 2Swansea U., UK, 3Peking U., China

2:55 PM 9.5 - In-situ B-doped Epi-GeSn Layers on Ge-buffered Si by Chemical Vapor Deposition with High Activation (4.9x1020cm-3), High Sn Content(14%), and High Growth Rate Enhancement(24x), F.-L. Lu1, C.-E. Tsai1, S.-Y. Lin1, and C. W. Liu1,2, 1National Taiwan U., Taiwan, 2National Nano Device Laboratories, Taiwan

3:15 PM – 4:45 PM Poster Session 2 & Coffee break

Session 10: Ferroelectrics II, Materials and Devices

Session Chair: T. P. Ma

4:45 PM 10.1 - Ultra-thin ferroelectric HfO2 and its application for ferroelectric tunnel junctions, X. Tian1, S. Migita2, and A. Toriumi1, 1U. Tokyo, Japan, 2AIST, Japan

Page 16: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

5:05 PM 10.2 - Improvement of Ferroelectricity of HfxZr1-xO2 Thin Films by New ZrO2 Nucleation Technique, T. Onaya1,2, T. Nabatame2, N. Sawamoto1, A. Ohi2, N. Ikeda2, T. Nagata2, and A. Ogura1, 1Meiji University, Japan, 2National Institute for Materials Science, Japan

5:25 PM 10.3 - Mechanism of Ferroelectric Phase Stabilization and Phase Competition in Doped HfO2 Films: A First-Principles Study, H. Z. Fang and S. V. Barabash, Intermolecular Inc.

5:45 PM 10.4 - Hysteresis-free internal potential enhancement in ferroelectric/paraelectric capacitors connected in series, X. Li and A. Toriumi, U. Tokyo, Japan

6:05 PM Adjourn 7:00 PM – 10:00 PM Conference banquet and Limerick contest 10:00 PM – 12:00 AM Hospitality room

Page 17: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Saturday, December 8, 2018

Session 11: Interfaces in Solar and Optoelectronic Devices

Session Chair: P. Stradins

8:00 AM 11.1 Invited - Dopant-Free Carrier Selective Contacts for Highly Efficient Si Solar Cells, A. Javey, UC Berkeley

8:35 AM 11.2 - Passivated Selective Contacts for Photovoltaics: Molybdenum Oxide Contacts with Aluminum Oxide Tunnel Layers, N. C. Strandwitz and B. Davis, Lehigh U.

8:55 AM 11.3 - Dopant-free Silicon Solar Cells and need for Fermi Level De-pinning layers, H. Lu1, Y. Guo2, and J. Robertson1, 1Cambridge U., UK, 2Swansea U., UK

9:15 AM 11.4 - >10% Solar-to-Hydrogen efficiency water splitting with interface-engineered silicon heterojunction solar cells, C. S. Tan1, K. W. Kemp1, A. C. Meng1, W. Tan1, C. E. D. Chidsey1, W. Ma2, F. Moghadam2, and P. C. McIntyre1, 1Stanford U., 2Sunpreme Inc.

9:35 AM 11.5 - Ferroelectric Modulation of Optoelectronic Properties in Wse2/In2Se3 Heterostructures, K. Xu1, X. Gao2, Z. Zhao1, and W. Zhu1, 1UIUC, 2Peking U., China

9.55 AM Coffee break

Session 12: Wide Band-Gap Semiconductors

Session Chair: H. Watanabe

10:20 AM 12.1 - A Novel I-V Characterization based on Ultraviolet Light for Quantitative Study of Donor- and Acceptor-like Interface Trap Density over Bandgap Energy in β-Ga2O3 FETs, H. Bae, J. Noh, and P. D. Ye, Purdue U.

10:40 AM 12.2 - Mechanism of Nitrogen Passivation of the SiO2/SiC(4H-0001) MOS structure: Interface Composition, Physical Stress and Electrical Quality, X. Li1, S. S. Lee2, M. Li1, A. Ermakov1, J. Medina-Ramos2, T. Fister2, V. Amarasinghe1, T. Gustafsson1, E. Garfunkel1, P. Fenter2, and L. C. Feldman1, 1Rutgers U., 2Argonne National Laboratory

11:00 AM 12.3 - Scattering mechanisms of free carriers in MOS inversion channel on nitrided 4H-SiC (11-20) a-face investigated by Hall effect measurement, H. Hirai, T. Hatakeyama, M. Sometani, M. Okamoto, S. Harada, and H. Okumura, AIST, Japan

11:20 AM 12.4 - High Resolution Mapping of Subsurface Defects at SiO2/SiC Interfaces by Local Deep Level Transient Spectroscopy Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy, Y. Yamagishi and Y. Cho, Tohoku U., Japan

Page 18: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

11:40 AM 12.5 - Exceptional Crystal and Electrical Properties of Atomic Layer Deposited BeO on 4H-SiC, S. M. Lee1, J. H. Yum2, E. S. Larsen2, C. W. Bielawski2, and J. Oh1, 1Yonsei U., Korea, 2IBS and UNIST, Korea

12:00 PM Adjourn for lunch

Session 13: Memory

Session Chair: P. C. McIntyre

1:30 PM 13.1 Invited - Physics in Charge Injection Induced On-Off Switching Mechanism of Resistive Random Access Memory (ReRAM) and Superlattice GeTe/Sb2Te3 Phase Change Memory (iPCM), K. Shiraishi, Nagoya U., Japan

2:05 PM 13.2 - Experimental and theoretical investigation of RRAM endurance statistical behavior, D. Alfaro Robayo1,2, G. Sassine1, Q. Rafhay2, G. Ghibaudo2, G. Molas1, and E. Nowak1, 1CEA/LETI, France, 2IMEP LAHC CNRS, France

2:25 PM 13.3 - Materials Selection and Non-linear Conduction Mechanism in Chalcogenide Selector Devices, H. Li1 and J. Robertson2, 1Tsinghua U., China, 2Cambridge U., UK

2:45 PM 13.4 - DFT Evidence for a Possible Origin of Switching in Chalcogenide Selector Films, S. V. Barabash, Intermolecular Inc.

3:05 PM Closing remarks and adjourn

Page 19: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

Author Index

Abelson A. 5.11 Addou R. 8.1 Afanas’ev V. V. 5.3, 6.2, 7.7, 7.8 Agarwal S. 5.18 Ahles C. F. 2.4, 5.6 Ahn D.-H. 3.2, 8.4 Al Jassim M. 5.18 Albert M. 3.13 Alfaro Robayo D. 13.2 Amarasinghe V. 12.2 Ando T. 3.7 Araidai M. 3.4, 5.7, 7.6 Asselberghs I. 7.7, 7.8 Athreya N. B. 5.10 Avasarala N. S. 5.3 Azcatl A. 6.1, 7.4 Bae H. 12.1 Barabash S. V. 10.3, 13.4 Bartha J. W. 3.13, 5.13 Bent S. F. 2.2 Bhuiyan M. A. 7.11 Bielawski C. W. 12.5 Blair S. L. 5.27 Blaise P. 7.5, 7.9 Bolshakov P. 6.1, 7.4 Bostwick A. 9.1 Bozok B. 5.17 Braun M. 5.23 Breeden M. 2.3, 5.6, 5.11 Brems S. 7.8 Bruley J. 7.12 Bu H. 1.1 Butun B. 5.16, 5.17

Campbell J. P. 5.8 Carr A. 7.12 Cartier E. A. 3.7, 7.12 Caruso E. 6.1 Chang H. 6.4 Chang-Liao K.-S. 9.3 Chapman R. A. 5.15 Chavarin C. A. 3.13 Chen P.-Y. 5.19 Chen S.-H. 5.21 Chen Y.-H. 7.16 Cheng L. 8.1 Cherkaoui K. 6.1 Cheung K. P. 5.8 Chiang M.-H. 5.21 Chiappe D. 7.7, 7.8 Chidsey C. E. D. 5.23, 11.4 Cho S.-J. 5.26 Cho Y. 12.4 Choi B.-D. 5.31 Choi J. 5.6 Choi J. Y. 2.4 Chokawa K. 3.4 Chung W. 3.9 Claes D. 1.2 Collaert N. 1.2, 1.3 Conley Jr J. F. 5.20 Cormier C. R. 8.1 Cott D. 1.3 Dabral A. 6.2 Davis B. 5.25, 11.2 De Gendt S. 7.7, 7.8 Demkov A. A. 5.19

SISC 2018

Page 20: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Droopad R. 3.12 Edwards H. 5.32 Egawa T. 5.2, 5.9 Ekerdt J. 5.19 Ermakov A. 12.2 Etcheverry L.P. 3.11 Fang H. Z. 10.3 Feldman L. C. 12.2 Fenter P. 12.2 Findley D. 5.28 Fischetti M. V. 5.24 Fister T. 12.2 Flores J. 5.27 Floros K. 5.26 Fong X. 5.1 Franco J. 1.2, 1.3 Frank M. M. 3.7, 7.12 Fu Y.-C. 3.12 Fukui T. 8.4 Furuoka K. 5.9 Gao X. 11.5 Garfunkel E. 12.2 Ghibaudo G. 13.2 Gity F. 6.1 Gong X. 5.1 Goux L. 5.3 Guiney I. 5.26 Gulseren M. E. 5.16, 5.17 Guo Y. 7.13, 9.4, 11.3 Gustafsson T. 12.2 Guthrey H. 5.18 Haasch R. 7.2 Hadamek T. 5.19 Han K. 5.1 Hanawa H. 5.14 Harada S. 12.3 Harvey S. P. 5.28 Hatakeyama T. 12.3 Hatanaka M. 3.7 Hedman H.-P. 5.29 Hemakumara D. T. 5.26 Hendricks O. L. 5.23 Heyns M. M. 1.2 Hinkle C. L. 6.1, 7.4, 8.1 Hirai H. 12.3 Hirano T. 1.3 Hirose T. 5.12

Honari S. 8.1 Horio K. 5.14 Hosoi T. 3.3, 3.4 Hou V. 9.1 Houssa M. 5.3, 6.2, 7.7 Hsu C.-W. 9.3 Hsu W.-Y. 9.3 Hu C. 7.16 Huang Y.-C. 5.21 Humphreys C. 5.26 Hung R. 2.4 Hurley P. K. 6.1, 7.4 Huyghebaert C. 7.7, 7.8 Hwang C. S. 7.17 Hyun S. D. 7.17 Ikeda M. 7.6 Ikeda N. 10.2 Inoue K. 3.3 Iordanidou K. 6.2 Irokawa Y. 5.22 Ito K. 5.22, 7.6 Iwamoto H. 1.3 Javey A. 11.1 Jenkins M. A. 5.20 Junige M. 3.13 Kabak M. 5.16 Kachi T. 5.22 Kale A. S. 5.18, 5.28 Kang S. 7.2, 7.3 Kar G. S. 5.3 Kato K. 8.4, 9.2 Kavrik M. S. 9.1 Kayal O. A. 5.16, 5.17 Ke M. 9.2 Kemp K. W. 11.4 Kerber P. 3.7 Khosravi A. 6.1, 7.4 Kikuta D. 5.22 Killge S. 5.13 Kim B. S. 7.17 Kim B. Y. 7.17 Kim D. 7.10 Kim H. H. 7.17 Kim J. 8.1 Kim K. D. 7.17 Kim K.-H. 5.31 Kim M. 5.19

Page 21: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Kim M. J. 8.1 Kim N. 2.4, 7.5 Kitzmann J. 3.13 Knoops H. 5.26 Kokko K. 5.29, 5.33 Kubo T. 5.2, 5.9 Kummel A. C. 2.3, 2.4, 5.6, 5.11, 5.27, 9.1 Kurosawa M. 7.6 Kurt G. 5.16, 5.17 Kuzmin M. 5.29, 5.33 Kwak I. 5.11 Kwon S. 5.19 Larsen E. S. 12.5 LaSalvia V. 5.28 Laturia A. 8.1 Laukkanen P. 5.29, 5.33 Lavoie C. 7.12 Law M. 5.11 Leburton J.-P. 5.10 Lee J.-Y. 5.31 Lee K.-L. 7.12 Lee K.-T. 3.7 Lee S. M. 12.5 Lee S. S. 12.2 Lee T.-E. 9.2 Lee Y. B. 7.17 Lee Y. H. 7.17 Lehtiö J.-P. 5.29 Leonhardt A. 7.7, 7.8 Li H. 13.3 Li J.-S. 9.3 Li M. 12.2 Li T. 8.2 Li X. 3.12, 5.26, 8.2, 10.4, 12.2 Li Y. 6.3 Lin J. 6.1 Lin S.-Y. 9.5 Linten D. 1.2 Liu C. W. 3.1, 9.5 Liu Z. 4.3 Lou X. 6.4 Lu A. 6.2 Lu F.-L. 9.5 Lu H. 11.3 Ludwig J. 7.8 Lukosius M. 3.13 Luo X. 3.8

Ma T. P. 4.1, 4.3, 7.11 Ma W. 11.4 Ma X. 3.6 Makihara K. 7.6 Marstell R. J. 5.25 McGehee M. D. 5.23 McGlone J. M. 5.20 McIntyre P. C. 5.23, 9.1, 11.4 Medina-Ramos J. 12.2 Mejia I. 5.15 Meng A. C. 5.23, 11.4 Migita S. 7.1, 10.1 Milenkovic O. 5.10 Millar D. 3.12 Mirabelli G. 6.1, 7.4 Mitsuishi K. 5.22 Miyajima T. 5.7 Miyashita T. 7.5 Miyazaki S. 7.6 Miyoshi M. 5.9 Moghadam F. 11.4 Molas G. 13.2 Monaghan S. 6.1 Moon T. H. 7.17 Moran D. 5.26 Mori Y. 7.1 Murillo-Borjas B. L. 5.4 Mäkelä J. 5.29, 5.33 Nabatame T. 5.22, 10.2 Nagata T. 10.2 Nagura T. 3.4 Nakano K. 5.14 Nanayakkara S. U. 5.18 Narayanan V. 3.7, 7.12 Narita T. 5.22 Nemani S. 2.4 Nemeth B. 5.18, 5.28 Nishimura T. 3.8, 7.1 Noh J. 12.1 Norman A. 5.18 Nowak E. 13.2 Ogawa Y. 3.7 Ogura A. 10.2 Oh J. 12.5 Ohi A. 10.2 Ohno K. 1.3 Ohta A. 7.6

Page 22: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Oka H. 3.3 Okamoto M. 12.3 Okumura H. 12.3 Onaya T. 10.2 Ono T. 5.5 Oshiyama A. 3.4 Oshiyama I. 1.3 Ozbay E. 5.16, 5.17 Ozturk M. 5.16, 5.17 O’Connor E. P. 3.7 O’Mahony A. 5.26 Page M. R. 5.18, 5.28 Park H. W. 7.17 Pellens N. 7.8 Peralagu U. 3.12 Pesic M. 5.13 Pintor-Monroy M. I. 5.4 Pop E. 7.9 Posadas A. 5.19 Pourtois G. 6.2 Punkkinen M. P. J. 5.29, 5.33 Punkkinen R. 5.29 Putcha V. 1.3 Qian C. 5.11 Quevedo-Lopez M. A. 5.4, 5.15 Rad Z. J. 5.29, 5.33 Radtke C. 3.11 Radu I. 7.7, 7.8 Rafhay Q. 13.2 Rahman A. 7.15 Rao F. 7.10 Renault O. 7.5 Repo P. 5.29 Robertson J. 7.13, 7.14, 9.4, 11.3, 13.3 Rodriguez-Davila R. A. 5.15 Roh J. H. 7.17 Rotenberg E. 9.1 Rozen J. 3.7 Ryu H. 7.10 Saadat A. 5.32 Saito M. 1.3 Samanta S. 5.1 Sasaki T. 1.3 Sassine G. 13.2 Sato H. 5.12 Savin H. 5.29 Sawamoto N. 10.2

Schoenaers B. 7.7 Sharma A. 7.2, 7.3 Shepard K. Keynote Shimizu M. 5.2 Shimura T. 3.3 Shin D. 5.19 Shiraishi K. 3.4, 5.7, 13.1 Shlyakhov I. 7.8 Si M. 3.9, 4.4, 7.11 Sioncke S. 1.3 Sivan M. 6.3 Sklénard B. 7.5 Smyth C. M. 6.1, 7.4, 8.1 Sometani M. 12.3 Song Z. 7.13 Steer M. 3.12 Stesmans A. 5.3, 6.2, 7.7 Stradins P. 5.18, 5.28 Strandwitz N. C. 5.25, 11.2 Stutzmann M. 5.30 Su C.-J. 7.16 Suryavanshi S. 7.9 Suzuki R. 1.3 Takagi S. 3.2, 8.4, 9.2 Takahashi T. 5.2 Takenaka M. 3.2, 8.4, 9.2 Takigawa A. 5.12 Tan C. S. 11.4 Tan W. 5.23, 11.4 Tang K. 9.1 Taoka N. 5.2 Taur Y. 9.1 Teranishi H. 5.12 Terao Y. 5.12 Thayne I. G. 3.12, 5.26 Thean A. V.-Y. 6.3 Theingi S. 5.28 Tian X. 10.1 Toriumi A. 3.8, 7.1, 10.1, 10.4 Trogler W. C. 5.27 Trung N. H. 5.2 Tsai C.-E. 9.5 Ueda S. 2.3 Ueda S. T. 5.11 Ural S. 5.16, 5.17 Vais A. 1.3 Van de Put M. L. 5.24, 5.32

Page 23: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

Van Houdt J. 4.2 Vandenberghe W. G. 5.32, 8.1 Vaxelaire N. 7.5 Velázquez-Nevárez G. A. 5.4 Vereecken P. Tutorial Vuorinen E. 5.29 Vyas P. B. 5.24 Wada Y. 3.3 Wager J. F. 5.20 Wallace R. M. 6.1, 7.4, 8.1 Walsh L. 6.1 Wang C. 5.8 Wang J. 5.27 Wang Q. 5.19, 8.1 Wang S.-J. 5.21 Wang W. 3.5, 3.6, 3.10 Wang X. 3.5, 3.6, 3.10 Watanabe H. 3.3, 3.4 Welzel T. 5.30 Wenger C. 3.13 Wiesinger M. 5.30 Wilk G. 2.1 Winkler F. 5.13 Wolf S. 2.3, 5.6, 5.11 Wong K. 7.5 Wu H. 6.4 Wu T.-L. 7.16 Wu T.-Y. 9.3 Wu Y. 8.2 Xia S. 7.2, 7.3 Xiang J. 3.5, 3.6, 3.10 Xie Z. 6.4 Xiong X. 8.2 Xu K. 7.2, 7.10, 11.5 Xu S. 5.1 Yajima T. 3.8 Yamada H. 5.2 Yamada T. 5.2 Yamagishi Y. 12.4 Yang L. 6.4 Yasir M. 5.29, 5.33 Yau J.-B. 3.7 Ye P. D. 3.9, 4.4, 7.11, 12.1 Ye T. 3.5, 3.10 Yi S.-H. 9.3 Yokoyama C. 3.2 Yoon S.-H. 3.2, 8.4

Yoshida S. 1.3 Young C. D. 5.15, 6.1, 7.4 Young D. L. 5.28 Yu X. 6.4 Yue R. 8.1 Yum J. H. 12.5 Zhang H. 9.4 Zhang S. 7.14 Zhang W. 6.4 Zhao C. 3.5, 3.10 Zhao P. 6.1, 7.4 Zhao Y. 6.3 Zhao Z. 7.3, 11.5 Zhou G. 8.1 Zhou H. 3.12 Zhou L. 3.5, 3.6, 3.10 Zhu W. 7.2, 7.3, 7.10, 11.5

Page 24: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

49th IEEE Semiconductor Interface Specialists Conference

December 5-8, 2018

Catamaran Resort Hotel, San Diego, CA www.ieeesisc.org

Affiliation Index

Aalto U., Finland 5.29 AIST, Japan 5.2, 6.2, 7.1, 10.1, 12.3 Applied Materials 2.4, 7.5 Applied Research and Photonics, Inc. 7.15 Argonne National Laboratory 12.2 ASM America 2.1 ASM Microchemistry Ltd., Finland 7.8 Bilkent U., Turkey 5.16, 5.17 Cambridge U., UK 7.14, 9.4, 11.3, 13.3 CEA/LETI, France 7.5, 7.9, 13.2 Chinese Academy of Sciences, China 3.5, 3.6, 3.10 Colorado School of Mines 5.18 Columbia U. Keynote Dalian U. Technology, China 5.8 Fuji Electric Co., Japan 5.12 Huazhong U. Science and Technology, China 6.4, 8.2 IBM 1.1, 3.7, 7.12 IBM, Switzerland 3.7 IBS and UNIST, Korea 12.5 IHP GmbH, Germany 3.13 imec, Belgium Tutorial, 1.2, 1.3, 4.2, 5.3, 6.2, 7.7, 7.8 IMEP LAHC CNRS, France 13.2 Instituto Politécnico Nacional, Mexico 5.4 Intermolecular Inc. 10.3, 13.4 Ioffe Physical-Technical Institute, Russia 5.33 Lawrence Berkeley Laboratory 9.1 Lehigh U. 5.25, 11.2 MDLsoft Inc. 5.13 Meiji University, Japan 10.2 Nagoya Institute of Technology, Japan 5.2, 5.9 Nagoya U., Japan 3.4, 5.2, 5.7, 5.22, 7.6, 13.1 National Cheng Kung U., Taiwan 5.21 National Chiao Tung U., Taiwan 7.16 National Institute for Materials Science, Japan 5.22, 10.2 National Nano Device Laboratories, Taiwan 3.1, 7.16, 9.5

SISC 2018

Page 25: 49th IEEE Semiconductor Interface Specialists Conference · 2018. 11. 15. · Diffusion of ions along interfaces is a phenomenon that leads to reliability issues in chip interconnects

National Taiwan U., Taiwan 3.1, 9.5 National Tsing Hua U., Taiwan 8.3, 9.3 NIST 5.8 NREL 5.18, 5.28 NUS, Singapore 5.1, 6.3 Oregon State U. 5.20 Osaka U., Japan 3.3, 3.4 Oxford Instruments, UK 5.26 Peking U., China 9.4, 11.5 Purdue U. 3.9, 4.4, 7.11, 12.1 Rutgers U. 12.2 Samsung, Korea 5.31 Seoul National U., Korea 7.17 Shibaura Institute of Technology, Japan 5.14 SKKU, Korea 5.31 Sony, Japan 1.3 Stanford U. 2.2, 5.23, 7.9, 9.1, 11.4 Sunpreme Inc. 11.4 Swansea U., UK 7.13, 7.14, 9.4, 11.3 Texas Instruments Inc. 5.32 Texas State U. 3.12 Tohoku U., Japan 12.4 Toyota, Japan 5.22 Tsinghua U., China 13.3 TSMC, Taiwan 9.1 TU Dresden, Germany 3.13, 5.13 TU München, Germany 5.30 Tyndall National Institute, Ireland 6.1, 7.4 U. Cambridge, UK 5.26, 7.13 U. Glasgow, UK 3.12, 5.26 U. Leuven, Belgium Tutorial, 1.2, 4.2, 5.3, 6.2, 7.7, 7.8 U. Notre Dame 8.1 U. Oslo, Norway 6.2 U. Tokyo, Japan 3.2, 3.8, 7.1, 8.4, 9.2, 10.1, 10.4 U. Tsukuba, Japan 5.5 U. Turku, Finland 5.29, 5.33 UC Berkeley 7.16, 11.1 UC Irvine 5.11 UCSD 2.3, 2.4, 5.6, 5.11, 5.27, 9.1 UFRGS, Brazil 3.11 UIUC 5.10, 7.2, 7.3, 7.10, 11.5 ULVAC Inc., Japan 3.7 UT Austin 5.19 UT Dallas 5.4, 5.15, 5.19, 5.24, 5.32, 6.1, 7.4, 8.1 Yale U. 4.1, 4.3, 7.11 Yonse U., Korea 12.5