4 - Wishbone
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Transcript of 4 - Wishbone
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WISHBONE
System On Chip Interconnection Architecture
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Uvod
Definiše dva tipa interfejsa: master slave
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Povezivanje
Zajednički signali za master-a i slave-a
CLK_I
Takt Izlazni signali postavljaju se na uzlaznu ivicu Ulazni moraju biti stabilni pre uzlazne ivice.
RST_I Reset signal
TAGN_I Ulazni signali specifični za konkretnu aplikaciju
TAGN_O Izlazni signali specifični za konkretnu aplikaciju
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PovezivanjeSignali specifični za master-a
ACK_I Ulazni signal potvrde, koji označava kraj ciklusa na magistrali
ADR_O(63..0) Adresna magistrala. Širina adrese se može menjati u zavisnosti od aplikacije
CYC_O Cycle izlazni signal koji ukazuje da je u toku transfer podataka na magistrali
DAT_I(63..0) Ulazni podaci. Širina magistrale može se menjati, u korelaciji je sa SEL_O signalima
DAT_O(63..0) Izlazni podaci. Širina magistrale može se menjati, u korelaciji je sa SEL_O signalima
ERR_I Error ulazni signal označava da je došlo da prekida ciklusa na magistrali usled pojave neke greške
RTY_I Retry ulazni signal ukazuje da interfejs nije spreman da prihvati ili pošalje podatke SEL_O(7..0) Select izlazni signal ukazuje gde se nalaze validni podaci na DAT magistrali
STB_O Strobe izlazni signal ukazuje na validni ciklus. Slave uređaj dužan je da postavi ACK, ERR ili RTY signal kao odgovor, na postavljanje STB_O signala.
WE_O Write Enable izlazni ukazuje da li je u toku ciklus upisa ili čitanja
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PovezivanjeSignali specifični za slave-a
ACK_O Ulazni signal potvrde, koji označava kraj ciklusa na magistrali
ADR_I(63..0) Adresna magistrala. Širina adrese se može menjati u zavisnosti od aplikacije
CYC_I Cycle ulazni signal koji ukazuje da je u toku transfer podataka na magistrali
DAT_I(63..0) Ulazni podaci. Širina magistrale može se menjati, u korelaciji je sa SEL_I signalima
DAT_O(63..0) Izlazni podaci. Širina magistrale može se menjati, u korelaciji je sa SEL_I signalima
ERR_OError izlazni signal označava da slave prekida ciklus na magistrali usled pojave neke greške
RTY_O Retry izlazni signal ukazuje da slave nije spreman da prihvati ili pošalje podatke SEL_I(7..0) Select ulazni signal ukazuje gde se nalaze validni podaci na DAT magistrali
STB_IStrobe ulazni signal ukazuje na validni ciklus. Slave postalja ACK, ERR ili RTY signal kao odgovor.
WE_I Write Enable ulazni signal ukazuje da li je u toku ciklus upisa ili čitanja
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Ciklus čitanja U trenutku 0 master postavlja:
ADR_O WE_O SEL_O CYC_O STB_O
Slave asinhrono postavlja ACK_I ukoliko je podatak spreman
U trenutku 1 master lečuje linije DAT_I ako je ACK_I postavljen
Wait stanja se ubacuju tako što slave odloženo postavlja ACK signal
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Blok transfer
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Blok transfer - čitanje
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Blok transfer - upis
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Primer Wishbone porta
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Primer Wishbone portalibrary ieee;use ieee.std_logic_1164.all;
entity WBOPRT08 isport(
-- WISHBONE SLAVE interface:ACK_O: out std_logic;CLK_I: in std_logic;DAT_I: in std_logic_vector( 7 downto 0 );DAT_O: out std_logic_vector( 7 downto 0 );RST_I: in std_logic;STB_I: in std_logic;WE_I : in std_logic;
-- Output port (non-WISHBONE signals):PRT_O: out std_logic_vector( 7 downto 0 )
);end entity WBOPRT08;
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Primer Wishbone portaarchitecture WBOPRT081 of WBOPRT08 is
signal Q: std_logic_vector( 7 downto 0 );begin
REG: process( CLK_I, RST_I )begin
if( RST_I = '1' ) thenQ <= B"00000000";
elsif( rising_edge( CLK_I ) ) thenif( (STB_I and WE_I) = '1' ) then
Q <= DAT_I( 7 downto 0 );end if;
end if;end process REG;ACK_O <= STB_I;DAT_O <= Q;PRT_O <= Q;
end architecture WBOPRT081;
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Primer Wishbone porta
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Primer Wishbone portalibrary ieee;use ieee.std_logic_1164.all;
entity WBOPRT16 isport(
-- WISHBONE SLAVE interface:ACK_O: out std_logic;CLK_I: in std_logic;DAT_I: in std_logic_vector( 15 downto 0 );DAT_O: out std_logic_vector( 15 downto 0 );RST_I: in std_logic;STB_I: in std_logic;SEL_I: in std_logic_vector( 1 downto 0 ); WE_I : in std_logic;
-- Output port (non-WISHBONE signals):PRT_O: out std_logic_vector( 15 downto 0 )
);end entity WBOPRT16;
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Primer Wishbone portaarchitecture WBOPRT161 of WBOPRT16 is
signal QH: std_logic_vector( 7 downto 0 );signal QL: std_logic_vector( 7 downto 0 );
beginREG: process( CLK_I, RST_I )begin
if( RST_I = '1' ) thenQH <= (others => '0');QL <= (others => '0');
elsif( rising_edge( CLK_I ) ) thenif( (STB_I and WE_I) = '1' ) then
if SEL_I(0) = '1' thenQL <= DAT_I( 7 downto 0 );
end if;if SEL_I(1) = '1' then
QH <= DAT_I( 15 downto 8 );end if;
end if;end if;
end process REG;
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Primer Wishbone portaACK_O <= STB_I;DAT_O( 15 downto 8 ) <= QH;DAT_O( 7 downto 0 ) <= QL;PRT_O( 15 downto 8 ) <= QH;PRT_O( 7 downto 0 ) <= QL;
end architecture WBOPRT161;
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Poravnanje – redosled bajtova
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BIG ENDIAN
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LITTLE ENDIAN
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Konverzija BIG » LITTLE
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Barrel pomerač
Primer korišćenja VHDL generičkih struktura
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Opis problema
Realizovati strukturni model višestepenog barrel pomerača koji rotira ulaznu reč u desno.
Širina reči i broj nivoa zadaju se kao generički parametri.
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Blok šema
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VHDL kodlibrary ieee;use ieee.std_logic_1164.all;
entity barrel isgeneric (
depth: natural := 3;width: natural := 8);
port (data_in : in std_logic_vector (width-1 downto
0);shift : in std_logic_vector (depth-1 downto
0);data_out: out std_logic_vector (width-1 downto 0));
end entity barrel;
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VHDL kodarchitecture structural of barrel is
component mux_2 is port (
data_in1,data_in2,sel : in std_logic;
data_out: out std_logic);
end component mux_2;
type array_of_vectors is array (0 to depth-2) ofstd_logic_vector(width-1 downto 0);
signal out_ver_hor: array_of_vectors;
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VHDL kod
begin vertical: for ver in 0 to depth-1 generatebegin
horizontal: for hor in width-1 downto 0 generate begin
. . .
end generate horizontal;end generate vertical;
end architecture structural;
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Uslovne strukture
Razlikuju se prvi, poslednji i redovi u sredini Koristi se uslovno generisanje
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Izgled ćelije u prvom redu
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VHDL kodfirst_line: if ver = 0 generatebegin
mux: mux_2port map (
data_in1 => data_in(hor),data_in2 => data_in((width +
(2**ver + hor)) mod width),data_out => out_ver_hor(ver)(hor),sel => shift(ver)
);end generate first_line;
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Izgled ćelije u sredini
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VHDL kodmiddle_line: if ver > 0 and ver < depth-1
and depth > 2 generatebegin
mux: mux_2port map (
data_in1 => out_ver_hor(ver-1)(hor),data_in2 => out_ver_hor(ver-1)((width +
(2**ver + hor)) mod width),data_out => out_ver_hor(ver)(hor),sel => shift(ver)
);end generate middle_line;
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Izgled ćelije u poslednjem redu
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VHDL kodlast_line: if ver > 0 and ver = depth-1
and depth > 1 generatebegin
mux: mux_2port map (
data_in1 => out_ver_hor(ver-1)(hor),data_in2 => out_ver_hor(ver-1)((width +
(2**ver + hor)) mod width),data_out => data_out(hor),sel => shift(ver)
);end generate last_line;
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