MAHALAKSHMI 3.pdf · 3. Explain the four modes of keyboard operation in 8279. (8) (AUC NOV 2010)...

MAHALAKSHMI

ENGINEERING COLLEGE

TIRUCHIRAPALLI-621213.

EC 2304 – MICROPROCESSOR & MICROCONTROLLER -V SEM ECE

EC2304-Microprocessor & Microcontroller

UNIT- III

PART –A (2 MARK QUESTIONS)

1. Why are the port lines of programmable port devices automatically put in the input

mode when the device is first powered up or reset? (AUC NOV 2012)

When the reset input goes ``high'' all ports will be set to the input mode with all 24

port lines held at a logic``one'' level by the internal bus hold devices . After the reset

is removed the 82C55A can remain in the input mode with no additional initialization

required. This eliminates the need for pullup or pulldown devices in ``all CMOS''

designs.

2. What is the use of „Vref‟ pin in the ADC? (AUC NOV 2012)

Vref, along with the number of bits of accuracy, is the voltage that defines how large

the individual voltage steps are between unique digital inputs.

ADC can work with the Vin between GND and Vref, or -Vref and +Vref or however

the manufacturer decides to make their part.

3. Why a latch is used for an O/P port, but a tri-state buffer can be used for an input

port? (AUC MAY 2012)

The Latch will hold the data until new data will changes from input of Buffer.

4. Mention any two applications that use ADC and DAC. (AUC MAY 2011)

Applications of DAC:

CD players, digital music players, and PC sound cards.

Specialist standalone DACs can also be found in high-end hi-fi systems.

Digital speakers such as USB speakers

Applications of ADC:

Music recording

Digital signal processing

Digital imaging systems

Radar systems

http://en.wikipedia.org/wiki/Hi-fi

http://en.wikipedia.org/wiki/Digital_speakers

http://en.wikipedia.org/wiki/Universal_Serial_Bus

http://en.wikipedia.org/wiki/Digital_imaging

http://en.wikipedia.org/wiki/Radar

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5. List the six modes of timer. (AUC MAY 2012)

Mode 0: Interrupt on Terminal Count Mode 1: Hardware Triggered One-Shot Mode 2: Rate Generator Mode 3: Square Wave Generator Mode 4: Software Triggered Strobe

Mode 5: Hardware Triggered Strobe

6. How many address lines and data lines are necessary for accessing 32Kx8 memory?

(AUC NOV 2011)

12 address lines.

7. Can an input port and an output port have the same port address? Justify. (AUC MAY

2010)

No, an input port and an output port have not the same port address, because for input

port read control signal is acting low and for output port write control signal is acting

low.

8. What are the operating modes of 8255?

1. Bit Set or Reset mode

2. I/O Mode

1.Mode 0

2.Mode 1

3.Mode 2

9. What is strobed IO?

It is another name for mode 1. It is used to interface slow speed device like printers.

Under this mode port A and port B work either input or output port and some of the

port C lines are used to exchange the control signals

10. What are the main blocks of 8279?

Key board section,Display section and Buffers.

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PART- B (16 MARK QUESTIONS)

1. Explain the parallel communication interface with microprocessor. (8) (AUC

NOV 2012)

• It is used to interface to the keyboard and a parallel printer port in PCs (usually

as part of an integrated chipset).

• Requires insertion of wait states if used with a microprocessor using higher that an 8

MHz clock.

• PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three

distinct modes of operation.

• Basic Mode Definitions and Bus

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• Mode 0 (Basic Input/Output).

• This functional configuration provides simple input and output operations for each of

the three ports.

• No “handshaking” is required, data is simply written to or read from a specified port.

• Mode1: Two Groups (Group A and Group B).

• Each group contains one 8-bit data port and one 4-bit control/data port.

• The 8-bit data port can be either input or output Both inputs and outputs are latched.

• The 4-bit port is used for control and status of the 8-bit data port.

• Mode 2 Bi-directional Operation

• This functional configuration provides a means for communicating with a peripheral

device or structure on a single 8-bit bus for both transmitting and receiving data

(bidirectional bus I/O).

• “Handshaking” signals are provided to maintain proper bus flow discipline in a

similar manner to MODE 1.

• Interrupt generation and enable/disable functions are also available.

• Used in Group A only.

• One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C).

• Both inputs and outputs are latched.

• The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-

directional bus port (Port A).

• Mode 2 Bi-directional Operation

• INTR : Interrupt request is an output that requests an interrupt.

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• ~OBF : Output Buffer Full is an output indicating that that output buffer contains data

for the bi-directional bus.

• ~ACK : Acknowledge is an input that enables tri-state buffers which are otherwise in

their high-impedance state.

• ~STB : The strobe input loads data into the port A latch.

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2. Draw the control word format of 8254 programmable interval timer and explain.

(AUC MAY 2012)

This is an important register used to determin and set the operation modes for the controller.

This is accessed by enabling the RD, A0, and A1 lines. This register can only be written to,

not read from.

The control word register uses a simple format. At first I was thinking of using a table here,

but it may be easier in a list format so here it is:

Bit 0: (BCP) Binary Counter

o 0: Binary

o 1: Binary Coded Decimal (BCD)

Bit 1-3: (M0, M1, M2) Operating Mode. See above sections for a description of each.

o 000: Mode 0: Interrupt or Terminal Count

o 001: Mode 1: Programmable one-shot

o 010: Mode 2: Rate Generator

o 011: Mode 3: Square Wave Generator

o 100: Mode 4: Software Triggered Strobe

o 101: Mode 5: Hardware Triggered Strobe

o 110: Undefined; Don't use

o 111: Undefined; Don't use

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Bits 4-5: (RL0, RL1) Read/Load Mode. We are going to read or send data to a

counter register

o 00: Counter value is latched into an internal control register at the time of the

I/O write operation.

o 01: Read or Load Least Significant Byte (LSB) only

o 10: Read or Load Most Significant Byte (MSB) only

o 11: Read or Load LSB first then MSB

Bits 6-7: (SC0-SC1) Select Counter. See above sections for a description of each.

o 00: Counter 0

o 01: Counter 1

o 10: Counter 2

o 11: Illegal value

3. Explain the four modes of keyboard operation in 8279. (8) (AUC NOV 2010)

Keyboard Interface of 8279

Features:

It is designed by Intel

It is support 64 contact key matrix with two more keys “CONTROL” and “SHIFT”

It provides 3 operating modes

It provides 16 byte display RAM to display 16 digits and interfacing 16 digits.

It provides two output modes:

1.Left entry (Typewriter type).

2.Right entry (Calculator type).

Simultaneous keyboard and display operation facility allows to interleave keyboard and

display software.

The interrupt output of 8279 can be used to tell CPU that the key press is detected, this

eliminates the need of software polling.

Operating modes

It is two types,

1. Input modes.

2. Display modes.

INPUT MODES:

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It is basically 3 types,

1. Scanned keyboard.

2. Scanned sensor matrix.

3. Strobed mode.

SCANNED KEYBOARD:

Key board can be scanned in two ways.

1.Encoded Scan 2.Decoded Scan.

ENCODED SCAN:

In this scan, scan lines (SL2-SL0) are decoded externally to provide 8 scan lines.

Additionally it provides 8 return lines.

So the size of matrix keyboard is 8*8 (i.e Scan * Return)=64.

When the key is pressed , it is stored the status of return lines , Scan lines ,SHIFT and

CNTL/STB keys into FIFO RAM.

DECODED SCAN:

In this mode ,internal decoder decodes the least significant bits of scan lines (SC3-SC0).

That is provide the four combination such as 1110,1101,1011 and 0111.

So the maximum size of keyboard is 8*4=32.

The key code is similar to encoded code , only bit 5 (B5) is always zero.

2-KEY LOCKOUT:

In this mode, the two key depression is not allowed.

When any key is depressed, the debounce logic is set and 8279 checks for any key depress

next two scans.

Three possible condition to avoid debouncing:

Condition 1:

If other key depression is not found during next two scan, it is a single key is depressed .Then

the status of key code is entered into FIFO RAM along with the status of CNTL and SHIFT

linesIf FIFO RAM is empty , The CPU is entry the data.

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If FIFO RAM is full , The CPU does not entry the data.

Condition 2:

If any other key depress is encountered , no entry to the FIFO can occur.

When the key is released after that only Entry will be allowed.

Condition3:

If the two key is pressed in simultaneously in a debounce cycle, both depression is not

considered.

N-KEY ROLLOVER:

Each key is depression is treated as independently from all others.

SCANNED SENSOR MATRIX:

In this mode , image of the sensor matrix is kept in the sensor RAM.

The status of sensor switches are input directly to the sensor RAM.

8279 scans row one by one and store the status of each row in the corresponding memory

location.

STROBED INPUT MODE:

The data is entered from Returned lines.

Display modes

It is basically two types,

1. Left entry (Type writer mode).

2. Right entry (Calculator mode).

LEFT ENTRY:

In this mode , 8279 display characters from left to right.

Like a typewriter.

AUTOINCREMENT IN LEFT ENTRY:

In left entry mode , Autoincrement flag is set after each operation display RAM address is

incremented.

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RIGHT ENTRY:

In this mode , 8279 display characters from Right to left.

Like a Calculator.

AUTOINCREMENT IN RIGHT ENTRY:

In right entry mode , Auto increment flag is set after each operation display RAM address is

incremented.

MMM field: DD Function

000 Encoded keyboard with 2-key lockout

001 Decoded keyboard with 2-key lockout

010 Encoded keyboard with N-key rollover

011 Decoded keyboard with N-key rollover

100 Encoded sensor matrix

101 Decoded sensor matrix

110 Strobed keyboard, encoded display scan

111 Strobed keyboard, decoded display scan

Encoded: Sl outputs are active-high, follow binary bit pattern 0-7 or 0-15.

Decoded: SL outputs are active-low (only one low at any time).

Pattern output: 1110, 1101, 1011, 0111.

Strobed: An active high pulse on the CN/ST input pin strobes data from the RL pins into an

internal FIFO for reading by micro later.

2-key lockout/N-key rollover: Prevents 2 keys from being recognized if pressed

simultaneously/Accepts all keys pressed from 1st to last.

4. Draw the block diagram of 8279 keyboard/ Display controller and explain how to

interface the Hex Key pad and 7- segment LEDs using 8279. (16) (AUC MAY

2010)

It consists 4 main section.

1. CPU interface and control section.

2. Scan section

3. Keyboard Section

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4. Display section.

CPU INTERFACE AND CONTROL SECTION:

It consists of

1. Data buffers

2. I/O control

3. Control and timing registers.

4. Timing and control logic.

Data Buffers:

8-bit bidirectional buffer.

Used to connect the internal data bus and external data bus.

I/O control:

I/O control section uses the A0,CS,RD and WR signals to controls the data flow.

The data flow is enabled by CS=0otherwise it is the high impedance state.

A0=0 means the data is transferred.

A0=1 means status or command word is transferred.

TIMING AND CONTROL REGISTERS:

Store the keyboard and display modes and others operating condition programmed

by the CPU.

The modes are programmed by sending proper command A0=1.

TIMING AND CONTROL:

It consist timing counter chain.

First counter is divided by N prescalar that can be programmed to give an internal

frequency of 100 KHz.

Display section

It consists of,

1. Display RAM.

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2. Display Address registers.

3. Display registers.

DISPLAY RAM:

It is a 16*8 RAM.

Which stores 16 digits display codes.

It can be accessed by CPU directly.

In Decoded mode,8279 uses only first four location of Display RAM.

In Encoded mode,8279 uses only first eight location of Display RAM.

And all 16 location for 16 digits display.

Keyboard section

This is consist of,

Return buffers.

Keyboard debounce control.

FIFO / sensor RAM.

FIFO / sensor RAM status.

RETURN BUFFERS:

8 return lines(RL7-RL0) are buffered and latched by when each row scan in scanned

keyboard or sensor matrix mode.

In strobed mode ,the contents of return lines are transferred to FIFO Ram.

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5. Draw the functional block diagram of 8254 timer and explain the different

modes of operation. (AUC MAY 2010) (AUC NOV 2012)

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Counter Registers

Each counter register holds the COUNT value used by the PIT to count down from. They

are all 16-bit registers. When writing or reading from these registers, you must first send

a control word to the PIT. You might wonder why we cannot just do it directly. There is a

reason for this, and it has to do with the size of the data. The PIT only has 8 data lines

(Pins D0-D7). However, the counter registers are all 16 bits, not 8.

Because of this, how does the PIT know what data you are writing to its counter register? How does it know what byte within the counter registers 16 bits are you setting? It doesn't. Sending a command word allows you to let the PIT know to expect incoming data, and what to do with it. We will look at that next.

8253 Hardware: Counters

The 8253 consists of three counters: Counter 0, Counter 1, and Counter 2. Each counter

has 2 input pins: CLK (Clock Input) and GATE, and one pin for output--OUT.

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As there are three counters, they are used for different purposes within the system. Each counter are 16 bit down counters.

Typical computers connect the first timer's OUT pin to a Programmable Interrupt Controller (PIC) to generate an interrupt for every clock tick. This is useually used as the System Timer. The second counter was used for generating a timing signal to the Memory Controller to refresh DRAM memory. The third counter is used to generate tones to the PC speaker.

As you can probably guess, the PIT uses the OUT pins to signal these devices when its counter reaches 0. When the PIT's counter reaches 0, it simply wraps around and starts again.

CLK is the clock input for the timer. It may be used with the GATE pin depending on the current mode of operation. The following table describes the operation depending on if the current in GATE is low, rising, or high.

The 8253 Counters are also known as Channels. Knowing that the 8253/8254 PITs contain three channels, lets look at each of them more closer.

Channel 0

Channel 0 is connected to the 8259 PIC to generate an Interrupt Request (IRQ). The

PITs OUT pin connects to the PIC's IR0 pin. Typically the BIOS configures this channel

with a count of 65536, which gives an output frequency of 18.2065 Hz. This fires IRQ 0

every 54.9254 ms.

The is the primary timer used on almost all x86 machines. the clock rate (Signalled through Counter 0's CLK pin) is at 1193181.6666... Hz, one third of the NTSC subcarrier frequency. This was required do to backward compatability with the older CGA PC's.

Channel 0 is typically programmed in most systems to act as the System Clock. This is made possible do to channel 0's OUT pin indirectly connecting to the PIC's IR0 line. Depending on the mode that we set it in, we can set the timer to a good frequency, and have it enable the PIC's IR0 line at a constant rate. Afterwords, reseting itself and starting over again. Because the PIC is used to handle hardware interrupts, we will need to first reprogram the PIC.

Because it is connected to the interrupt with the lowest number (IR0), it also has the highest priority over all other hardware interrupts.

Its lowest frequency rate is normally used for computers running the old DOS systems (Are there any left?) at about 18.2 Hz. Its highest frequency rate is a little over a megahertz.

In real mode operating systems, the BIOS normally increments the number of times IRQ0 is fired to 0000:046C, which can be read by any running program.

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Channel 1

Many video cards and the BIOS may reprogram the second channel for their own uses.

This channel was originally used for generating a timing pulse signal to signal the

memory controller to refresh the DRAM memory. In modern times, this is no longer

needed as the refresh is done by the memory controller. Because of this, there is no

guarantee at what devices may use this counter.

Channel 2

This channel is connected to the PC Speaker to generate sounds. the PC speaker is

normally meant to produce a square wave with two levels of output. However, it is

possible to go between the two true defined sound square levels. This is called Pulse-Width Modulation (PWM)

8253 Channel Modes

Remember that each counter can be programmed in 1 of 6 modes. This is done by

sending an Initialization Control Word (ICW) to the controller. We will look at the format

of this command word later. For now, lets look at each mode.

Mode 0: Interrupt on Terminal Count

In this mode, the counter will be programmed to an initil COUNT value and afterwords

counts down at a rate to the input clock frequency (The CLK signal). When COUNT is

equal to 0, and after the Control Word is written, the counter enables its OUT pin (by

setting its line high) to signal the device it is connected to. Counting starts one clock

cycle after the COUNT is programmed. The OUT line remains high until the counter is

reloaded with a new value or the same value or until another control word is written to

the controller.

What this mode basically does is allow us to set a timer that counts down to 0. After which, we will need to reload a new count number to it, or a new control word to re-initialize the counter.

Mode 1: Hardware Triggered One-Shot

In this mode, the counter is programmed to give an output pulse every certain number

of clock pusles. The OUT line is set to high as soon as a Control Word is written. After

COUNT is written, the counter waits until the rising edge of the GATE input. If the trigger

occurs during the pulse output, the 8253 will be retriggered again. One clock cycle after

the rising edge of GATE is detected, OUT will become and remain low until COUNT

reaches 0. OUT will then be set high until the next trigger and wait again until the rising

edge of the GATE input is detected.

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Mode 2: Rate Generator

This mode configures the counter to be a "divide by n" counter, which is commonly used

to generate a real-time system clock.

The counter is programmed to an initial COUNT value. Counting starts at the next clock cycle. OUT remains high until COUNT reaches 1. Afterwords, OUT will be set low for one clock pulse. OUT is then set back high, and COUNT is reset back to its initial value. This process repeats until a new control word is sent to the controller.

The time between the high pulses depends on the current value in COUNT, and is calculated using the following formula:

COUNT = input (Hz) / Frequency of output

COUNT never reaches 0. It only ranges from n to 1, where n is the initil COUNT value.

Okay, lets stop for a moment. Remember that Counter 0 is connected to the PIC? Counter 0's OUT line indirectly connects to the PIC's IR0 line. Knowing that, when the IR0 line is low, the PIC will call the IRQ 0 handler defined by us.

If we set the counter to Mode 2, we can set up the timer to fire off our interrupt at a constant rate. All we need to do is determine what the COUNT value should be based off of the above formula. This is used very often in setting up the System Timer for the operating system. After all, IRQ 0 is now being called for every clock tick at a frequency rate that we defined.

Mode 3: Square Wave Generator

This mode is quite similar to Mode 2. However, OUT will be high for half of the period,

and low for the other half. If COUNT is odd, OUT will be high for (n+1)/2 counts. If

COUNT is even, OUT will be low for (n-1)/2 counts.

Everything else is the same from Mode 2. We will need to use the formula from Mode 2 to set up the initial COUNT value.

If the speaker is configured to use the PIT, the channel that it uses typically should be set to use this mode.

Mode 4: Software Triggered Strobe

The counter is programmed to an initial COUNT value. Counting starts at the next clock

cycle. OUT remains high until COUNT reaches 0. The counter will then set OUT low for

one clock cycle. Afterwords, it resets OUT to high again.

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Mode 5: Hardware Triggered Strobe

The counter is programmed to an initial COUNT value. OUT remains high until the

controller detects the rising edge of the GATE input. When this happens, the

counting starts. When COUNT reaches 0, OUT goes low for one clock cycle.

Afterwords, OUT is set high again. This cycle repeats when the controller detects

the next rising edge of GATE.

6. Explain the function of CRT interface mdule.

CRT Controller intended to provide capability for interfacing CRT or TV-type raster

scan displays.

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MPU INTERFACE SIGNAL DESCRIPTION

cp2 (Clock) The input clock is the system cp2 clock and is used to trigger all data

transfers between the system microprocessor and the SY6545. Since there is no

maximum limit to the allowable cp2 cycle time, it is not necessary for it to be a

continuous clock.

RIW (ReadIWrite) The RiW signal is generated by the microprocessor and is used to

control the direction of data transfers. A high on the R.iW pin allows the processor to

read the data supplied by the SY6545; a low on the RiW pin allows a write to the

SY6545.

CS (Chip Select) The Chip Select input is normally connected to the processor

address bus either directly or through a decoder.

RS (Register Select) The Register Select input is used to access internal re· gisters. A

low on this pin permits writes into the Address Register and reads from the Status

Register. The contents of the Address Register is the identity of the register accessed

when RS is high.

DBO-DB7 (Data Bus) The DBO·DB7 pins are the eight data lines used for transfer of

data between the processor and the SY6545. These

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lines are bi-directional and are normally high-impedance except during read cycles

when the chip is selected.

7. Explain briefly about the ADC interface module.

8255 is used for interfacing the analog to digital converters with microprocessor.

• We have already studied 8255 interfacing with 8086 as an I/O port, in previous

section. This section we will only emphasize the interfacing techniques of analog to

digital converters with 8255.

• The analog to digital converters is treaded as an input device by the microprocessor,

that sends an initialising signal to the ADC to start the analogy to digital data

conversation process. The start of conversation signal is a pulse of The process of

analog to digital conversion is a slow process, and the microprocessor has to wait for

the digital data till the conversion is over. After the conversion is over, the ADC sends

end of conversion EOC signal to inform the microprocessor that the conversion is

over and the result is ready at the output buffer of the ADC. These tasks of issuing an

SOC pulse to ADC, reading EOC signal from the ADC and reading the digital output

of the ADC are carried out by the CPU using 8255 I/O ports. a specific duration. The

time taken by the ADC from the active edge of SOC pulse till the active edge of EOC

signal is called as the conversion delay of the ADC.

It may range any where from a few microseconds in case of fast ADC to even a few

hundred milliseconds in case of slow ADCs.

The available ADC in the market use different conversion techniques for conversion

of analog signal to digitals.

Successive approximation techniques and dual slope integration techniques are the

most popular techniques used in the integrated ADC chip.

General algorithm for ADC interfacing contains the following steps:

1. Ensure the stability of analog input, applied to the ADC.

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2. Issue start of conversion pulse to ADC

3. Read end of conversion signal to mark the end of conversion processes.

4. Read digital data output of the ADC as equivalent digital output.

Analog input voltage must be constant at the input of the ADC right from the start of

conversion till the end of the conversion to get correct results. This may be ensured by

a sample and hold circuit which samples the analog signal and holds it constant for a

specific time duration. The microprocessor may issue a hold signal to the sample and

hold circuit.

• If the applied input changes before the complete conversion process is over, the

digital equivalent of the analog input calculated by the ADC may not be correct.

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If one needs a sample and hold circuit for the conversion of fast signal into equivalent

digital quantities, it has to be externally connected at each of the analog inputs.

Vcc Supply pins +5V

GND GND

Vref + Reference voltage positive +5 Volts maximum.

Vref_Reference voltage negative 0Volts minimum.

I/P0–I/P7 Analog inputs

ADD A,B,C Address lines for selecting analog inputs.

O7– O0 Digital 8-bit output with O7 MSB and O0LSB

SOC Start of conversion signal pin

EOC End of conversion signal pin

OE Output latch enable pin, if high enables output

CLK Clock input for ADC

8. Explain with the suitable blocks the functions of DAC interface mdule.

• A fairly common and low-cost digital-to-analog converter is the DAC0830.a product

of National Semiconductor Corp .An 8-bit converter that transforms an 8-bit binary

number into an analog voltage. Other converters are available that convert from 10-,

12-, or 16-bit binary numbers into analog voltages. The number of voltage steps

generated by the converter is equal to the number of binary input combinations.

– an 8-bit converter generates 256 voltage levels

– a 10-bit converter generates 1024 levels

• The DAC0830 is a medium-speed converter that transforms a digital input to an

analog output in approximately 1.0 µs.

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• The device has eight data bus connections for the application of the digital input code.

• Analog outputs labeled IOUT1 & IOUT2 are inputs to an external operational

amplifier.

• Bcause this is an 8-bit converter, its output step voltage is defined as –VREF (reference

voltage), divided by 255.

• the step voltage is often called the resolution of the converter

• This device contains two internal registers.

• the first is a holding register

• the second connects to the R–2R internal ladder converter

• The two latches allow one byte to be held while another is converted.

• The first latch is often disabled and the second for entering data into the converter.

• Both latches within the DAC0830 are transparent latches.

– when G input is logic 1, data pass through

– when G input becomes logic 0, data are latched

• The output of the R–2R ladder within the converter appears at IOUT1 and IOUT2.

• These outputs are designed to be applied to an operational amplifier such as a 741

or similar device.

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