3D IC-Package-Board Co-analysis using 3D EM … 2 A 3D INTEGRATION... · 4/25/2014 1 CST –...

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CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com ECTC 2013

3D IC-Package-Board Co-analysis using

3D EM Simulation for Mobile Applications

Darryl Kostka, CST of America

Taigon Song and Sung Kyu Lim, Georgia Institute of Technology


Introduction

TSV Array Cross Talk Analysis

Return Path Discontinuity Modeling

2.5D Link Analysis

3D IC Link Analysis

Conclusion

Outline

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Introduction to 3D Integration

Source: Cadence Design Systems, Inc. “3D ICs with TSVs—Design Challenges and

Requirements”

3D IC

System-on-

Chip (SoC)

System-in-

Package (SiP)

2.5D

Stacking


D=100μm, R=15μm, L=100μm, dox=0.1μm, εSiO2=3.9 (tand=0.001),

εSi=11.9 (cond=10S/m)

TSV Signal-Ground Pair

Sharp slope due to

transition from slow wave

to quasi-TEM mode

Losses due to

displacement

currents in Si

Insertion Loss (dB)

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Cross Talk: TSV Array

Baseline: D=100μm, R=10μm, L=200μm,

dox=1μm, εSiO2=3.9 (0.001), εSi=11.9 (10S/m)

1

2

3

Aggressor via

Neighboring Victim via

Shielded Victim via

Return vias

Victim vias

5x5 TSV array with 1 driven aggressor and two

victim vias;

Aggressor (TSV1) is driven with a pulse

(risetime=100ps, amplitude=2V) using a 50Ohm

source resistor.

Far end of aggressor TSV and both sides of all other

signal TSVs are terminated in 50Ohms


Cross Talk: TSV Array NEXT – Frequency domain

Neighboring victim

Shielded victim

NEXT – Time domain

Thicker oxide liners help reduce cross talk for low resistivity substrates

High resistivity substrates act as low loss dielectrics and therefore help reduce cross talk

Low resistivity substrate has a larger peak voltage and longer coupled noise duration (ISI)

Chip-package co-design since TSV response in the chip stack can propagate into package

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Interposer: Return Path Discontinuities

Surface current distribution (Glass) @30GHz showing cavity resonance

Microstrip-to-microstrip transition causes

a change in the reference plane (RPD)

Results in large SSN voltage induced

between planes at resonance frequencies

Increased insertion loss


Eye Diagrams for Silicon and Glass Interposers

Glass Silicon

282.6ps

0.29V 17.89ps

295.2ps

0.31V 6.7ps

3.2 Gbps 210-1 PRBS stream

Jitter and eye opening are considerably improved in the Silicon interposer, in

comparison with the Glass interposer

Performance of glass interposer can be improved by using decoupling capacitors

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2.5D Link Test Case

Die size: 1 mm x 1 mm, 250 um thickness (Die 1 is identical to Die 2)

Double Sided Silicon Interposer size: 40 mm x 40 mm, 300 um thickness

u-bump dimensions: 60 um diameter, 52 um height, 200 um pitch

TPV dimensions: 40 um diameter, 300 um height, 200 um pitch

Signal

Signal


IC Design I/O Pad Map

GDSII Import from

Cadence Virtuoso

Silicon IC BEOL

NCSU FreePDK 45nm technology library

10 metal layers, 12um thick Cu backend

11 signals total

M1

M10

u-bump

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Double Sided Silicon Interposer Design

IC 1 IC 2

Interposer

(Eps = 2.51, tanD = 0.004)

20mm

Microstrip-to-microstrip signal

routing used to maximize RPD

effects (worst case scenario) 40mm


Method 1: Complete chip-interposer-chip link co-simulation

2.5D Link: Analysis Methodology I

Pos: Highest level of accuracy since all 3D coupling effects between the ICs and

interposer are captured

Neg: Not computationally feasible (3D full-wave analysis) due to the complexity of the

IC design and the aspect ratios involved

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Method 2: Decoupling / Cascading approach

2.5D Link: Analysis Methodology II

Reference

Plane

Electric Wall used as

Discrete Port Reference

Electric Wall used as Discrete Port Reference

+ port

Center of the u-bump array is used as the reference plane (electric wall)

All signal, power and ground nets need to be terminated to maintain

return current path continuity

S-parameters

(Die 1)

S-parameters

(Interposer)

S-parameters

(Die 2)


2.5D Link: Analysis Methodology II

IC

Interposer

PEC sheet

reference

PEC sheet

reference

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2.5D Link: Analysis Methodology III Method 2: Decoupling / Cascading approach

Reference Plane

Reference

Plane

The reference plane is selected along a

uniform section of the signal traces to

ensure TEM propagation mode.


Excitation Port Definition Die 1

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Die 2

Die 1 and Die 2 are identical

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IC: Surface Current Distribution

Coupling to surrounding (non neighboring) nets can be observed at higher frequencies

100 MHz 2 GHz

Signal Excitation Port Signal Excitation Port


S-Parameter Results Port 5

Port 1

Port 6

FEXT

NEXT

IL

RL …

…

…

…

Port 2

Port 7

Port 3

Port 8

Port 4

For the “fewer pins” case,

only the PWR/GND pins

neighboring the signal pins

were included

Results demonstrate that

good correlation can be

achieved provided the return

current path continuity is

preserved

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3D IC Link Test Case

Signal

Signal

Die size: 1 mm x 1 mm, 250 um thickness

Tier 3 = Signal I/Os, PDN distributed between Tier 2 and Tier 1

Double Sided Silicon Interposer size: 40 mm x 40 mm, 300 um thickness

u-bump: 36 um diameter, 200 um pitch flip-chip bump: 60um diameter

TSV: 12 um diameter, 50 um height TPV: 40 um diameter, 300 um height


3D IC Link: Analysis Methodology

Method A

Method B

Method C

Full 3D link

Center of the u-bump and flip-chip bump arrays are used for the reference plane locations

All signal, power and ground nets are terminated to maintain return current path continuity

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S-Parameter Results

Stronger coupling between

TSV’s is observed in 3D IC’s

and therefore using a

decoupling simulation strategy

provides inaccurate results

especially for cross talk. FEXT

NEXT

IL RL


Demonstrated 3D full-wave electromagnetic analysis of a chip to

chip channel using a simple IC (few I/O’s) and Si interposer prototype

TSV’s demonstrate high levels of cross talk due to the conductive

Silicon substrate

For 2.5D applications, it is possible to decouple the IC from the

interposer and obtain accurate results up to around 20 GHz

For 3D IC applications, the strong coupling between the TSV’s in the

IC stack makes it impossible to perform a decoupled analysis

Conclusion

3D IC-Package-Board Co-analysis using 3D EM … 2 A 3D INTEGRATION... · 4/25/2014 1 CST –...

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Transcript of 3D IC-Package-Board Co-analysis using 3D EM … 2 A 3D INTEGRATION... · 4/25/2014 1 CST –...