3.155J/6.152J Lecture 2: IC Lab Overview Lecture 2: IC Lab Overview Prof. Martin A. Schmidt ... 2.6...
Transcript of 3.155J/6.152J Lecture 2: IC Lab Overview Lecture 2: IC Lab Overview Prof. Martin A. Schmidt ... 2.6...
3.155J/6.152J Lecture 2:IC Lab Overview
Prof. Martin A. SchmidtMassachusetts Institute of Technology
9/12/2005
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 2
Outline
The MOSFET StructureSemiconductor DopingThe MOSFET as a SwitchA MOSFET ProcessThe MOS Capacitor ProcessRecommended reading
Plummer, Chapters 1 and 2
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 3
MOSFETG
Source Drain
OxideGate
Bulk
DSD
G
S
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 4
N-Channel MOSFET
n-type n-type
OxideGate
p-type
+VG
0 V +VD
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 5
A Word About Doping….Silicon has four valence electrons
It covalently bonds with 4 adjacent atoms in the crystal lattice
Si
Si
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 6
Intrinsic SemiconductorIncreasing Temperature Causes Creation of Free Carriers
1010 cm-3 free carriers at 23C (out of 2x1023 cm-3)Intrinsic Conductivity
Si
Si
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 7
N-type DopingPhosphorus has 5 valence electrons
‘Donates’ one conduction electron – n-typeOur substrate has 1015 cm-3 phosphorus (1 in 108)
Si
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
P
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 8
P-type DopingBoron has 3 valence electrons
‘Accepts’ one electron from latticeCreates a ‘hole’ – p-type
B
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
Si
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 9
Counter DopingThe addition of one more B than P causes thedoping type to change from n-type to p-type
Si
Si Si Si Si
Si Si Si Si
Si Si Si Si
SiSiSiSi
SiSiSiSi
SiSiSiSi
SiSiSiSi Si Si Si SiSi
SiSiSiSi Si Si Si SiSi
P
B
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 10
Counter Doping Process
n-type (1015 cm-3)
Concentration1015
Depth
n-type (1015 cm-3)
p-type (>1015 cm-3)
Implant Boronand Anneal
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 11
P/N Junction+ - + - + - +
+ - + - + --+ - + - + - +
+ - + - + --+ - + - + - +
+ - + - + --+ - + - + - +
+ - + - + - +- + - + - + -+ - + - + - +- + - + - + -+ - + - + - +- + - + - + -+ - + - + - +
p-type n-typeDepletion Region
-----
+++++p-type n-type
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 12
P/N Junction - Diode
-----
+++++p-type n-type
+ V -
I I
V
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 13
N-Channel MOSFET Operation
0 V +VG
n-type- - - - - - - - - - - - - - - -
n-type
Oxide
p-type
+++++++++++++++++
0 V +VD
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 14
MOSFET as a Switch
n-type n-typeOxideGate
p-type
+VD0 V0 V
n-type n-typeOxideGate
p-type
+VD0 V+VG
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 15
Microfabricated Devices
Starting MaterialSingle crystal silicon
Mask SetContains x,y info
(Top View)
Process SequenceContains z info
(Cross Section)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 16
Sample Mask Set
Four Levels (Masks)
Mask
1
2
3
4
Definition
Active Area
Polysilicon
Contact Cuts
Aluminum
PolysiliconResistor
MetalResistor
DiffusionResistor(Diode)
Transistor(MOSFET)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 17
Our Processp-channel
Poly Gate pMOS
Polycrystaline SiliconMetal-Oxide-Semiconductor (MOSFET)
polysilicon
n-silicon
p p-------+++++++
Source DrainGate
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 18
Starting Material
6” (150mm) Diameter Silicon Wafer30 +/- 1 mil thick (~750 µm)n-type (doped with Phosphorus)
1.5 Ω-cm resistivity (1015 cm-3 Phos)
<100> crystal orientation
<110>
Major Flat
Minor Flat<100>
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 19
FET Process Steps
1. Characterize the wafer (resistivity, orientation, and type)2. Grow 5000A ‘Field Oxide’ for device isolation
Typically at 800-1100C for 1 hour in O2 or steam
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 20
Process Steps3. Pattern Active Area (Mask #1)
Coat withphotoresist
ExposeMask
Develop
Etch*
Strip resist
*Wet etch
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 21
Process Steps
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 22
Process Steps4. Grow 500A Gate Oxide
5. Deposit 5000A Polysilicon by LPCVD (low pressurechemical vapor deposition)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 23
Process Steps6. Pattern Polysilicon (Mask #2)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 24
Process Steps7. Etch Gate Oxide
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 25
Process Steps8. Ion Implantation of Boron
B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+
9. Drive-In (950C in O2)
Note self alignment
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 26
Process Steps10. Strip Backside
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 27
Process Steps11. Pattern Contact Cuts (Mask #3)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 28
Process Steps12. Evaporate Aluminum
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 29
Process Steps13. Pattern Aluminum (Mask #4)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 30
Process Steps14. Sinter (400C – N2:H2)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 31
Process Results
The Four Mask Process YieldsResistors
MetalPolysiliconDiffusion
CapacitorsMetal-SiliconMetal-PolysiliconPolysilicon-Silicon
Gate OxideField Oxide
DiodeMOSFETBipolar Junction Transistor (low quality)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 32
Our LabsLab Session 1
1.1 Lab Safety and Cleanroom Orientation 1.2 RCA (ICL RCA) 1.3 Gate Oxidation
Thermco Atmospheric Furnace (5D-FieldOx) Dry Oxidation, 1000°C 60 minutes
1.4 Doped Polysilicon Deposition Thermco LPCVD (6A-Poly)
1.5 AnnealThermco Atmospheric Furnace (5B-Anneal)
Lab Session 22.1 Measure oxide and polysilicon thickness (UV1280) 2.2 Etch oxide in BOE (Buffered Oxide Etch) until de-wet2.3 HMDS, Photoresist Application, Postbake (SSI coater track) 2.4 Dry etch backside polysilicon (LAM490B) 2.5 Etch backside oxide in BOE until de-wet (OxEtch-BOE) 2.6 Strip frontisde resist with Matrix System One Stripper (Asher)
Lab Session 33.1 HMDS, Photoresist Application, Pre-bake (SSI coater track) 3.2 Exposure, Development, and Inspection (I-Stepper) 3.3 Dry-etch polysilicon (LAM490B) 3.4 Strip photoresist with Matrix System One Stripper (Asher) T.1 Device characterization: MOS Capacitor
Determine oxide capacitance. Determine bulk dopant concentration. Determine fixed interface charge.
T.2 Sheet resistance measurement: Van der Pauw structure
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 33
Lab Session 11.1 Lab Safety and Cleanroom Orientation 1.2 RCA (ICL RCA) 1.3 Gate Oxidation
Thermco Atmospheric Furnace (5D-FieldOx) Dry Oxidation, 1000°C 60 minutes
1.4 Doped Polysilicon Deposition Thermco LPCVD (6A-Poly)
1.5 AnnealThermco Atmospheric Furnace (5B-Anneal)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 34
Lab Session 22.1 Measure oxide and polysilicon thickness (UV1280) 2.2 Etch oxide in BOE (Buffered Oxide Etch) until de-wet2.3 HMDS, Photoresist Application, Postbake (SSI coater track) 2.4 Dry etch backside polysilicon (LAM490B) 2.5 Etch backside oxide in BOE until de-wet (OxEtch-BOE) 2.6 Strip frontside resist with Matrix System One Stripper (Asher)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 35
Lab Session 3
3.1 HMDS, Photoresist Application, Pre-bake (SSI coater track) 3.2 Exposure, Development, and Inspection (I-Stepper) 3.3 Dry-etch polysilicon (LAM490B) 3.4 Strip photoresist with Matrix System One Stripper (Asher)
Fall 2005 – M.A. Schmidt 3.155J/6.152J – Lecture 2 – Slide 36
Lab Session 3 (Testing)
T.1 Device characterization: MOS Capacitor Determine oxide capacitance. Determine bulk dopant concentration. Determine fixed interface charge.
T.2 Sheet resistance measurement: Van derPauw structure