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International Journal of Computer Applications (0975 8887)Volume 3 No. ! June "0#0

2.8 Cloc, Select Adder with Sharin" CSAS/

ns ead o( !sing wo se"ara e adders in conven ional CSA, one(or he Cs9 79 and ano her (or he Cs979 and ano her (or heCs97= $9=&' ?ne adder is !sed o red!ce he area and "ower cons!m" ion' Each o( he wo addi ions is "er(ormed in one cloc/ c.cle' *he #loc/ diagram o( CSAS is shown in (ig!re ' *his is a0-6#i adder in which leas signi(ican #i :LSB; adder is a ri""lecarr. adder :RCA; adder, which is -- #i s wide' *he !""er hal( o( he adder i'e' mos signi(ican "ar is 9= #i s wide' *his "arwor/s according o cloc/' 2henever cloc/ goes high addi ion (or he carr. in"! one is "er(ormed' And when cloc/ goes low hencarr. in"! is ass!med as +ero and addi ion is s ored in adder i sel(' As can #e seen (rom he (ig!re la ch is !sed o s ore hes!m and carr. (or Cin79' Carr. o! (rom he "revio!s s age i'e' Fi"ure 9+ Simulation wave-orm o- carry select adderleas signi(ican #i adder is !sed as con rol signal (or m!l i"le4er o selec he (inal o! "! carr. and s!m o( he adder'( ac !al carr. in"! is one hen (or com"! ed s!m and carr. la chis accessed and (or carr. in"! +ero MSB adder is accessed' Co!is he o! "! carr.' Similarl., we can design CSAS adders o( more s ages o red!ce area and "ower cons!m" ion'

Fi"ure :+ Simulation wave-orm o- 4 sta"e carry select adder

Fi"ure 8+ The architecture o- CSAS %73

4. SI;*LATI)( R!S*LTSFi"ure

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International Journal of Computer Applications (0975 8887)Volume 3 No. ! June "0#0

Ga e co!n red!c ion is a sign o( area red!c ion' Ga e co!n o( csas - s age is 99 less han carr. selec , = less han 0 s age carr.selec and 99= han 1 s age carr. selec adder' For (!r her o

Ta#le 2+ Comparison o- ripple carry= carry select= 4 sta"eand 5 sta"e carry select adders

Ripple Carry 4 sta"e 5 sta"ecarry select carry carryadder select select

L*T>s - %9 %1

I)B>s % % % %

&ate Count 0%= 1%- 1 %9

' 01 0%'% 0 '%1 0 '=00elay ns/Fi"ure %%+ Simulation wave-orm o- 8 sta"e CSAS

*a#le9 shows he com"arison o( 0-6#i carr. s/i" adder and 0-6 -'=9 ' '0- '%9ynamic #i varia#le carr. s/i" adder' *a#le- re"resen s he com"arison powero( area, "ower and dela. o( ri""le carr., carr. selec , 0 s age and

mw/1 s age carr. selec adders' *a#le 0 "rovides he res!l s o# aineda( er design and im"lemen a ion o( - s age CSAS and s ageCSAS

Ta#le4. Comparison o- CSAS 2 sta"e and CSAS 8 sta"eTa#le%. Carry S,ip and 6aria#le Bloc, Carry S,ip desi"n

CSAS 2 sta"e CSAS 8 sta"ecomparison -or area= delay and power

L*T>s %%@ 9 99Carry s,ip 6aria#le carry

s,ipI)B>s %%@9 0 %%@9 0

L*T>s 9@ 9 @ 9

1 9 9,9%9&ate CountBonded I)B>s % @9 0 % @9 0

10' = -1'1%elay ns/01 0%=&ate Count

-%'= - - '= 1elay ns/ ynamic Power 1 '%1 9 ' 0

mw/ynamic Power -'= -'90mw/

e4"lore in his wor/ is o design he adder in a wa. o red!ce he5. C)(CL*SI)(dela. as he area and "ower red!ces' 2herever here is need o( smaller area and low "ower cons!m" ion, while some increase inAll he adders designed are 0-6#i s wide' CSAS s age consis sdela. is olera ed, s!ch designs can #e !sed' *hese adders areo( s ages wi h each #loc/ (rom LSB #loc/ o MSB #loc/s are(as er han RCA and slower han CSA'$ 6 6 6 69=& #i s wide' *hese adders are (as er han ri""le carr.

adders #! slower han carr. selec adders' All he adders are

8. R!F!R!(C!Sdesigned !sing VHDL :Ver. High S"eed n egra ion HardwareDescri" ion Lang!age;, Kilin4 Pro)ec 3aviga or %'9i is !sed as a

$9& ' Rawwa , *' Darwish, and M' Ba.o!mi, 'A low "ower s.n hesis ool and ModelSim KE '-g (or sim!la ion' FPGAcarr. selec adder wi h red!ces area , Proc' ?( MidwesS"ar an0 is !sed (or im"lemen ing he designs'S.m"osi!m on Circ!i s and S.s ems, ""' -9 6 --9, -==9'

$-& A' *.agi, A red!ced area scheme (or carr.6selec adders ,EEE *rans' on Com"! er, vol' 1-, ""' 99 06 99 =, 9%%0

$0& 2' Neong and ' Ro., Ro#!s high6"er(ormance low "ower adder , Proc' o( he Asia and So! h Paci(ic DesignA! oma ion Con(erence, ""' =06 = , -==0

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International Journal of Computer Applications (0975 8887)Volume 3 No. ! June "0#0

$1& O' im and L6S im, 16#i carr.6selec adder wi h red!ced $ & ' A#id, H' El6Ra+o!/ and D'A' El6Di#, Low "ower area , Elec ronics Le ers, vol' 0 , ""' 916 9 , Ma. -==9' m!l i"liers #ased on new h.#rid (!ll adders , Microelec ron ics

$ & ?' won, E' Swar +lander, and ' 3ow/a, A (as h.#rid No!rnal, Vol!me 0%, ss!e 9-, Pages 9 =%69 9 , -== 'carr.6loo/ahead@carr.6selec adder design , Proc' o( he 99 h $%& Hasan rad and Aws Oo!si( Al6*aie, Per(ormance Anal.sisGrea La/es s.m"osi!m on VLS , ""'91%69 -, March -==9' o( a 0-6Bi M!l i"lier wi h a Carr.6Loo/6Ahead Adder and a

& B' Parhami, Com"! er Ari hme ic, Algori hm and Hardware 0-6#i M!l i"lier wi h a Ri""le Adder !sing VHDL , No!rnal$Design, ?4(ord Iniversi . Press, 3ew Oor/, ""'%9699%, o( Com"!er Science 1 :1; 0= 60= , -== '-===' $9=& Behnam Ameli(ard, Far+an Fallah, and Masso!d Pedram,

QClosing he ga" #e ween carr. selec adder and ri""le carr.$ & 2ang, O' Pai, C'Song, K', *he design o( h.#rid carr.adder a new class o( low6"ower high6"er(ormance addersQ,loo/ahead@ carr.6selec adders , Circ!i s and S.s ems in Proc' o( EEE n erna ional S.m"osi!m on !ali . Elec ronicAnalog and Digi al Signal Processing, EEE *ransac ions onDesign : S ED;, -== 'Vol!me 1%, ""'9 6-1, -==-

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