3 3 3 8 - INSA [email protected] tanguy Lab CITI, INSA de on Ly ersion V du August 30,...
Transcript of 3 3 3 8 - INSA [email protected] tanguy Lab CITI, INSA de on Ly ersion V du August 30,...
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
ARC: Computer Ar hite ture
tanguy.risset�insa-lyon.fr
Lab CITI, INSA de Lyon
Version du August 30, 2018
Tanguy Risset
August 30, 2018
Tanguy Risset ARC: Computer Ar hite ture 1
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Table of Contents
1
Introdu tion
2
The �Von Neumann� y le (Instru tion stages)
3
Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 2
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Toward a Von Neumann omputer
What you have seen:
How to build an ALU with transistors ( ombinatorial ir uit)
How to build a ontroller with transistor (automate)
Basi Von Newmann behavior:
Registers
ALU (or datapath)
ontrol unit (automaton)
Memory (and bus)
Lets re all the basi Von Neumann behavior
Tanguy Risset ARC: Computer Ar hite ture 3
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
Mémoire
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
16 adresse de boot
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
load R0,[36]
16
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
7
16
load R0,[36]
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
20
load R1,[40]
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
load R1,[40]
20
10
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
add R3,R0,R1
24
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
add R3,R0,R1
24
7
+
10
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
add R3,R0,R1
24
17
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
28
store R3,[44]
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Program exe ution on a Pro essor (8 general purpose
registers)
8
3
33
RI
décodeur
MémoirePC
16
20
8
4
0
24
28
32
36
40
44
48
52
56
60
64
68
72
76
load R0,[36]
load R1,[40]
add R3,R0,R1
store R3,[44]
xx
7
10
store R3,[44]
28
17
17
Tanguy Risset ARC: Computer Ar hite ture 4
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Let's study in more details the instru tion exe ution:
instru tion exe ution y le (Von Neumann y le)
Instru tion pipeline
ISA de�nition
RISC instru tion set
Tanguy Risset ARC: Computer Ar hite ture 5
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Table of Contents
1
Introdu tion
2
The �Von Neumann� y le (Instru tion stages)
3
Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 6
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
The �Von Neumann y le�
The so- alled Von Neumann y le is simply the de omposition of the
exe ution of an instru tion in several independent stages.
The number of stages depend on the pro essor, usually 5 stages are
ommonly used as example:
Instru tion Fet h (IF)
Reads the instru tion from memory (at address $PC) and write it in $IR.
Instru tion De ode (ID)
omputes what needs to be omputed before exe ution: jump address
destination, a ess to register, et .
Exe ute (EX)
exe utes the instru tion: ALU omputation if needed
Memory A ess (MEM)
Loads (or stores) data from memory if needed
Write Ba k (WB)
Writes the result into the register �le if needed
Tanguy Risset ARC: Computer Ar hite ture 7
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
The MIPS example
The RISC paradigm was invented by Berkeley and popularized by
Henessy and Patterson in the book on MIPS
MIPS stands for Mi ropro essor without Interlo ked Pipeline Stages
and propose and ar hite ture to exe ute ea h stage independently
from MIPS website https://www.mips. om/
Tanguy Risset ARC: Computer Ar hite ture 8
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Christian Wolf's slides
Use Christian Wolf slides for explaining MIPS instru tion pipeline
Here
Tanguy Risset ARC: Computer Ar hite ture 9
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
example of MIPS pipeline CPU ar hite ture
Taken from Henessy/patterson book
Tanguy Risset ARC: Computer Ar hite ture 10
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Illustration of bubble on MIPS
When next instru tion annot be fet hed dire tly (be ause it need
the result of previous instru tion for instan e) it reates a �bubble�
For instan e: an addition using a register that was just loaded
The value of the register will be available after the MEM stage of
�rst instru tion, hen e we an delay on only on y le, provided there
is a short ut.
Tanguy Risset ARC: Computer Ar hite ture 11
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Another illustration of instru tion pipeline
Go ba k to our previous representation of the pro essor and memory:
Von Neumann omputer= Memory + CPU
CPU= = ontrol Unit + Datapath
Datapath= ALU + Register �le
PC IR
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
Tanguy Risset ARC: Computer Ar hite ture 12
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
A pipeline example from MIPS
Exe ute the sequen e of assemby instru tion:
load value at address 500 in register R0
Add 1 to R0 and put result in R1
store value of Register R1 at address 500
(Think of i=i+1)
Code:
la R0,500
add R1, R0, 1
sw R1,500
Tanguy Risset ARC: Computer Ar hite ture 13
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
First possible exe ution: without pipeline
Before exe ution starts, $PC ontains the address of the �rst
instru tion: 100
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
100
Tanguy Risset ARC: Computer Ar hite ture 14
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 1
Instru tion Fet h
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
100 la R0,500
Tanguy Risset ARC: Computer Ar hite ture 15
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 2
Instru tion De ode
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
100 la R0,500
Tanguy Risset ARC: Computer Ar hite ture 16
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 3
Exe ute (nothing for load)
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
100 la R0,500
Tanguy Risset ARC: Computer Ar hite ture 17
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 4
Memory a ess
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
100 la R0,500
Tanguy Risset ARC: Computer Ar hite ture 18
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 5
Write Ba k
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
100 la R0,500
10
Tanguy Risset ARC: Computer Ar hite ture 19
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 6
in rement $PC
Fet h next instru tion
et . et .
Processor
Memory
Control unitALU
Datapath
Register Filecontrol/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
104 add R0, R1,1
Tanguy Risset ARC: Computer Ar hite ture 20
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Counting CPI for non-pipelined ar hite ture
CPI= Cy le per instru tion
5 y les for exe uting on instru tion
⇒ 15 y les for 3 instru tions.
Example of non-pipelined ar hite ture: the MSP430 mi ro- ontroller
(use further in ARC) has a simpler RISC CPU ar hite ture, ea h
instru tion takes 2 y les, no pipelined is implemented.
Tanguy Risset ARC: Computer Ar hite ture 21
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Example of pipelined exe ution
Instru tion Fet h (for 'load' instru tion)
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
100 la R0,500
Tanguy Risset ARC: Computer Ar hite ture 22
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 2
Instru tion De ode (for load)
Instru tion Fet h (for 'nothing' be ause of a bubble: instru tion
'add' delayed)
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
104
load
Tanguy Risset ARC: Computer Ar hite ture 23
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 3
Exe ute (for load: nothing to do)
Instru tion De ode (for 'nothing')
Instru tion fet h (for 'add')
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
104
10
add R1,R0,1
Tanguy Risset ARC: Computer Ar hite ture 24
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 4
Memory a ess (for load)
Exe ute (for 'nothing')
Instru tion De ode (for add)
Instru tion fet h (for store)
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR
108
add
load
add
sw R1,500
Tanguy Risset ARC: Computer Ar hite ture 25
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 5
Write Ba k (instru tion load)
Memory a ess (for 'nothing')
Exe ute (instru tion add: bypass)
Instru tion De ode store
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500 10
PC IR10
116
sw
load
Tanguy Risset ARC: Computer Ar hite ture 26
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 6
Write Ba k (for 'nothing')
Memory a ess (instru tion add, nothing to do)
Exe ute (instru tion store: nothing to do)
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500
PC IR10
120
add
sw
10
Tanguy Risset ARC: Computer Ar hite ture 27
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
y le 7
Write Ba k (instru tion add)
Memory a ess (instru tion store: bypass)
Processor
Memory
Control unit
ALU
Datapath
Register File
control/Status
R0 R1
R2 R3
100
104
108
add R1,R0,1
la R0,500
sw R1,500
500
PC IR10
124
add
sw
11
11
Tanguy Risset ARC: Computer Ar hite ture 28
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Counting CPI for both ar hite tures
Non-pipelined ar hite ture:
5 y les for one instru tion
⇒ 15 y les for 3 instru tions.
Pipelined ar hite ture:
5 y les for one instru tion
8 y les for 3 instru tions.
⇒ without bubbles, one instru tion per y le
A 'jump' instru tion interrupt the pipeline (need to wait for the address
de oding to fet h next instru tion) ⇒ pipeline stall
Some ISA allow to use these delay slots: one or two instru tion after the
jump are exe uted before the jump o urs.
Tanguy Risset ARC: Computer Ar hite ture 29
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Table of Contents
1
Introdu tion
2
The �Von Neumann� y le (Instru tion stages)
3
Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 30
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Set Ar hite ture Statement (ISA)
The instru tion set (Set Ar hite ture statement: ISA) is of
paramount importan e
It determines the basi instru tions exe uted by the CPU.
It's a balan e between the hardware omplexity of the CPU and the
ability to express the required a tions
It is represented in a symboli way: the assembly ode/language (ex:
ADD R1,R2)
The tool that translates symboli assembly ode in binary ode (i.e.
ma hine ode) is also alled the assembler
Two types of ISA:
CISC: Complex Instru tion Set Computer
RISC: Redu e Instru tion Set Computer
Tanguy Risset ARC: Computer Ar hite ture 31
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
CISC: Complex Instru tion Set Computer
An instru tion an ode several elementary operations
Ex: a load, an add and a store (in memory operations)
Ex: omputer a linear interpolation of several values in memory
Need a mode omplex hardware (spe i� ally hardware a elerators)
High variability in size and exe ution time for di�erent instru tions
Produ e a more ompa t ode but more omplex to generate
Vax, Motorola 68000, Intel x86/Pentium
Tanguy Risset ARC: Computer Ar hite ture 32
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Example: instru tions ISA of Pentium
JE EIP + displacement
JE Condition Displacement
4 8
Call
CALL Offset
8 32
Mov $EBX, [EDI+displacement]
MOV
6 1
wd r−m postbyte
8
Displacement
8
Push ESI
PUSH Reg
5
Add $EAX, Immediate
4
ADD
Test $EDX, Immediate
1
17 32
ImmediatePostBytewTEST
4
32
Immediate
13
Reg w
8
3
Tanguy Risset ARC: Computer Ar hite ture 33
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
RISC: Redu ed Instru tion Set Computer
Small simple instru tions, all having the same size, and (almost) the
same exe ution time.
no omplex instru tion
Clo k speed in rease with pipelining (between 3 and 7 pipeline
stages)
Code simpler to generate but less ompa t
Every modern pro essor use this paradigm: SPARC, MIPS, ARM,
PowerPC, et .
Tanguy Risset ARC: Computer Ar hite ture 34
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Example: instru tions of MSP430 ISA
15 13 12 11 1014 9 8 7 6 5 4 3 2 1 0
0 0 1 condition PC offset (10 bits)
relative Jumps
15 13 12 11 1014 9 8 7 6 5 4 3 2 1 0
opcode Dest reg. Ad Dest reg.B/W As
2 operands instruction
15 13 12 11 1014 9 8 7 6 5 4 3 2 1 0
1 operand instruction
0 0 0 00 1 opcode B/W Ad Dest reg.
Examples:
PUSB.B R4
JNE -56
ADD.W R4,R4
Tanguy Risset ARC: Computer Ar hite ture 35
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Exemple of Pentium ISA
Write a simple C program toto.
Type g -S toto. and get the
toto.s �le
you an also use the ompiler
explorer:
https://g .godbolt.org/
main() {
int i=17;
i=i+42;
printf("%d\n", i);
}
⇒
(... instru tions ...)
movl $17, -4(%rbp)
addl $42, -4(%rbp)
(... printf params... )
all printf
(... instru itons ...)
Tanguy Risset ARC: Computer Ar hite ture 36
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Disassemby
ompile the assembly ode: g toto.s -o toto
disassemble with objdump:
objdump -d toto
Adresses Instru tions binaires Assembleur
(...)
40052 : 55 push %rbp
40052d: 48 89 e5 mov %rsp,%rbp
400530: 48 83 e 10 sub $0x10,%rsp
400534: 7 45 f 11 00 00 00 movl $0x11,-0x4(%rbp)
40053b: 83 45 f 2a addl $0x2a,-0x4(%rbp)
40053f: 8b 45 f mov -0x4(%rbp),%eax
400542: 89 6 mov %eax,%esi
% (...)
Tanguy Risset ARC: Computer Ar hite ture 37
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
ARM like ISA
Let's study a generi RISC ISA, lose to ARM ISA
ISA �rst de�nes the types of data on whi h the pro essors an
ompute
Memory addresses (32-bit, or 64-bit re ently)
Bit �elds (to do bitwise logi al operations)
Integers of di�erent sizes (8,16,32, 64) signed or unsigned
Floating-point numbers (32-bit single pre ision or 64-bit double
pre ision)
Various proprietary extensions (small integer MMX, small SSEx �oats,
et .)
Tanguy Risset ARC: Computer Ar hite ture 38
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
ISA omputation instru tion
Instru tion dedi ated to omputations: arithmeti s, logi al, shift et .
let's take the example of addition
Computation instru tion operate on register (if 16 registers are
available, 4 bits are su� ient to identify them).
Possible mnemoni for addition:
add R0 R1 → R3
in general op Rx, Ry → Rd, where op an be add, mul, sub,
or, and et .
Operands an be values instead of register. In general the instru tion
name hanges: add R0, #4 → R3.
How to ode the instru tion in binary:
3 registers to name ⇒ 3× 4 = 12 bits
A given number of bits to ode the operation (8bits: 256 operations)
Some bits left for oding onstants if needed
Tanguy Risset ARC: Computer Ar hite ture 39
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Number of operand
We have de�ned a so- alled three-operands addition sin e the three
operands used. There are other solutions :
2-operands instru tions: op Rd, Rx → Rd. One of the operands is
overwritten.
1-operand instru tions: same idea, but Rd is �xed and impli it. It's
usually alled the a umulator.
Sta k based instru tions (0 operand): the pro essor has a sta k (like
al ulators HP), and an add statement takes its two operands to the
top of the sta k and stores the result.
Tanguy Risset ARC: Computer Ar hite ture 40
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Memory addressing operation
Basi read/write:
Read [R2℄ → R5
reads the ontent of address ontained in R2, pla e the result in R5
onversely: Write R3 → [R6℄
With a onstant: Read [#46℄ → R5
indire t addressing:
Read [R2+R3℄ → R5
with auto-in rement
Read [R2+℄ → R5
(R5← [R2℄; R2=R2+1)
Tanguy Risset ARC: Computer Ar hite ture 41
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Sta k management instru tion
High-level languages use a lot of Sta ks (last in, �rst out, used for
managing the alls of pro edures).
The sta k is stored in memory
A spe i� register is used to a ess the top of sta k: $SP for Sta k
Pointer
instru tion Push R1 sill push R1 on sta k i.e.:
Write R1 → [SP℄
Add SP, 1 → SP
SP+1 means �add to SP the size of the word� (32 or 64 bits)
Instru tion Pop R1 will do the opposite: Read [SP℄ → R1
Sub SP, 1 → SP
Tanguy Risset ARC: Computer Ar hite ture 42
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Flow ontrol instru tions
The main �ow ontrol instru tion (to implement loops and ifs) are
the jumps:
Relative Jumps
GoForward #123 (jump to urrent address+123)
GoBa kward #123
Warning: less than 32 bits for the onstant!
Absolute jumps
Jump #1234
Conditional jumps
GoForward #123 IfPositive (i.e. if last operation's result was
positive)
ne essitates the presen e of �ags
Usually at four �ags: C ( arry), N (negative), Z (Zero), V (over�ow)
In some ISA, �ags are repla ed by predi ates (any ondition an be used
as �ag).
Tanguy Risset ARC: Computer Ar hite ture 43
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Subroutine Calls
The all (i.e. jump at the �rst instru tion) of a pro edure is done
with the instru tion all
all Label
The label is a symboli way to indi ate where is stored the ode of
the pro edure
The all instru tion performs a jump and keep tra ks of the urrent
address in order to be able to ome ba k here after the exe ution of
the instru tion Return (usually use the sta k for that)
The Return instru tion does not returns values (su h as the result of
fun tions),
results and parameter of fun tions are transmitted either on the
sta k or in spe i� register. This is de�ned by the ABI (Appli ation
Binary Interfa e).
The ABI allow fun tions produ ed from di�erent ompiler to all
themselves (i.e. library)
Tanguy Risset ARC: Computer Ar hite ture 44
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Interruption
The instru tion �ow an be interrupted at any time by an interrupt:
Pa ket arrived on network ard
Sound ard required more samples to play
a hara ter has been stroked on the keyboard
et .
Interrupt are almost equivalent of fun tion alls:
They interrupt the urrent instru tion �ow to exe ute the interrupt
handler
Then they ontinue the exe ution where is has been stopped
Ideally they have no impa t on the fun tion being exe uted, hen e all
registers are saved on the sta k before jumping to interrupt handler
Interrupts and Interrupts handler will be studied in more details in
CRO ourse
Tanguy Risset ARC: Computer Ar hite ture 45
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Other ISA instru tions
Change mode instru tions
modes interrupt, user, supervisor et .
Syn hronization instru tions
for multi- ore systems
Tanguy Risset ARC: Computer Ar hite ture 46
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
ISA Example: MSP430
MSP430 ISA is an instru tion set for mi ro- ontroller very low
onsumption (smart ards, RFID tags).
16-bit RISC instru tion set with 16-bit registers .
There are instru tions of one and two operands.
If these operands are registers, the instru tion holds in one word of
16 bits.
The operands an also be a memory box whose address (on 16 bits)
is oded in one of the words following the instru tion. In this ase
the instru tions are 32 or 48 bits.
Some registers are spe ial: the $PC is R0,
the �ags are in the register R1, and the register R2 an take di�erent
values useful onstants (0, 1, -1 ...).
the number of y les that ea h instru tion takes is exa tly equal to
the number of memory a esses that it makes.
Tanguy Risset ARC: Computer Ar hite ture 47
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Example: instru tions of MSP430 ISA
15 13 12 11 1014 9 8 7 6 5 4 3 2 1 0
0 0 1 condition PC offset (10 bits)
relative Jumps
15 13 12 11 1014 9 8 7 6 5 4 3 2 1 0
opcode Dest reg. Ad Dest reg.B/W As
2 operands instruction
15 13 12 11 1014 9 8 7 6 5 4 3 2 1 0
1 operand instruction
0 0 0 00 1 opcode B/W Ad Dest reg.
Exemples:
PUSB.B R4
JNE -56
ADD.W R4,R4
Tanguy Risset ARC: Computer Ar hite ture 48
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
ISA example: ARM
ARM ISA is a 32-bit RISC instru tion set with 16 registers found
among other things in all mobile phones.
All the instru tions are oded in exa tly one memory word (32 bits).
The instru tions are 4 operands: the fourth is an o�set that an be
applied to the se ond operand.
The se ond operand, and the o�set an be onstants. For example,
add R1, R0, R0, LSL #4 al ulates in R1 the multipli ation of R0
by 17, without using the multiplier (slow, and sometimes otherwise
absent).
For embedded systems, ARM produ ed the THUMB ISA
(instru tions with 2 operands on 16 bits)
In re ent ARM system, instru tion of 16 and 32 bits an be mixed
Tanguy Risset ARC: Computer Ar hite ture 49
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 50
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 51
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 52
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 53
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 54
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 55
Introdu tion The �Von Neumann� y le (Instru tion stages) Instru tion Set Ar hite ture (ISA)
Tanguy Risset ARC: Computer Ar hite ture 56