2nd International Conference on Nano-electronics, Circuits ...

IETE Ranchi ARTTC BSNL Ranchi ISVE Ranchi

1

2nd

International Conference on Nano-electronics, Circuits & Communication Systems (NCCS-2016) 25

th -26

th Dec. 2016 at ARTTC BSNL Ranchi-835217 Jharkhand India, [email protected]

2nd

International Conference on

Nano-electronics, Circuits & Communication

Systems(NCCS-2016)

Advanced Regional Telecom Training Center BSNL, Near Jumar River Bridge, Hazaribag Road, Ranchi-835217, Jharkhand, India Tel: 0651-2273260(BO), Mob. 9973886214(GC), 8877101225(OS), 9431259955(CO)

Web:www.ieteranchi.org, / www.isve.in, E-mail: [email protected],

[email protected]

Organizer: INSTITUTION OF ELECTRONICS & TELECOMMUNICATION

ENGINEERS & INDIAN SOCIETY FOR VLSI EDUCATION

--------------------------------------------------------------------------------------------------------------------- Dear Sir/Madam,

We are glad to inform you that IETE & ISVE Ranchi Centre is organizing two days 2nd

International Conference on Nano-electronics, Circuits & Communication Systems (NCCS-

2016) on 25-26th

Dec-2016 at ARTTC, BSNL near Jumar River, Hazaribag Road, Ranchi.

Prospective authors are invited to submit full papers describing original, previously

unpublished, complete work (not currently under review by any another conference/ journal) up

to six pages in IEEE double column format including figure, results and references. All papers

send on conference e-mail:[email protected], [email protected],

[email protected], [email protected] . Papers will be accepted in word format only. The

accepted papers will be published in conference proceedings by reputed international publisher

Springer with ISBN number and extended versions of papers will be published in SCOPUS, SCI

and some other indexed journals. (Name of Journals: 1-IETE Journal of

Research (http://mc.manuscriptcentral.com/tijr), 2-IETE Technical Review, 3- JOLPE, 4-IETE

Journal of Education, 5-Microsystem Technologies, 6-Analog Integrated Circuits and Signal

Processing, 7- IJCA, 8-TELKOMNIKA, etc ).

NCCS-2016 will includes oral sessions and poster sessions, tutorials, invited talks,

keynote address by renowned Scientists, Professors and Industry persons from India and Abroad

on topics related to the conference. Original theoretical, practical, experimental, simulations,

development, application, measurement, and testing based papers are invited for presentation in

the conference. All submitted papers will go through rigorous plagiarism checking, language

http://www.isve.in/

mailto:[email protected]


mailto:[email protected],%[email protected]

mailto:[email protected],%[email protected]


http://mc.manuscriptcentral.com/tijr


2

2nd


th -26


checking by expert’s reviewers. Details review comments will be sending to communicating

authors in the form of Accepted, Accepted with changes, and rejected.

About NCCS-2015: 1st International Conference on Nano-electronics, Circuits &

Communication Systems (NCCS-2015) has been organized by ISVE & IETE at ARTTC BSNL

Ranchi on 9-10th

May-2015. A list of peer reviewed and plagiarism free papers have been

accepted for publication in SCOPUS book series LNEE (Lecture Notes on Electrical

Engineering) of Springer :

http://www.isve.in/ContentUploaded/adminisve/file/Final%20Paper%20list%20to%20be%20pub

lished%20in%20Proceeding%20of%20ICNCCS%20in%20Springer%20book%20series%20LN

EE.pdf and see www.springer.com/gp/book/9789811029981 and extended version of papers

have been published by SCI Journals: http://link.springer.com/article/10.1007/s00542-016-2873-

8 and some other extended version papers are in queue for publications in above listed journals.

Theme of the Conference: International conference focused on the frontier issues in the

Electrical, Electronics, Computer, Communication and Information Technology and their

applications in business, academic, industry and other allied areas. This international conference

main aim to bring together scientists, researchers, engineers from academia and industry. It will

provide an international forum to exchange and share their knowledge, experiences,

technological developments, and researches in current trends.

Topics of Conference:

Nanoelectronics Devices

Micro Electro Mechanical System

VLSI Design & IC Technology

IC Fabrication and Testing

Device, Circuit & Systems

CMOS Sensors

VLSI for Wireless Communications

VLSI for Bioengineering

VLSI for Instrumentations & Controls

VLSI for ESDM

Image Processing

VLSI Signal Processing

Digital Signal Processing

Embedded System

Real Time Embedded System

Robotics & Applications

Electric Power System

Hybrid Vehicles

ICT Applications

Computer Architecture

Information Security

Knowledge and Data Mining

Software Engineering

Image Sensing & Processing

Brain Computer Interface

Parallel, Grid and Cloud Computing

Mobile Communication and Computing

Adhoc Networks, Pervasive Computing

Wireless Sensor Networks

Body Sensor Network

Sensor Network Applications in Mines

Antennae and Diversity

EMI & EMC

Satellite Communications

Fibre Optics Communications

Optical Networks

http://www.isve.in/ContentUploaded/adminisve/file/Final%20Paper%20list%20to%20be%20published%20in%20Proceeding%20of%20ICNCCS%20in%20Springer%20book%20series%20LNEE.pdf



http://www.springer.com/gp/book/9789811029981

http://link.springer.com/article/10.1007/s00542-016-2873-8

http://link.springer.com/article/10.1007/s00542-016-2873-8


3

2nd


th -26


Renewable Energy

Green Energy

Cloud Computing

Algorithm Development and

Implantation

Computer Networks

Intelligent Instrumentation

Quantum Dots

Bioengineering & Telemedicine

RFID & Telemetry Systems

Environmetal Science & Engineering

Urban Planing

Sensors, Actuators & Transducers

Patron:

Dr. A.K.S. Chandele, President IETE, New Delhi

Chairman:

Sh. Ajay Kumar, ARTTC, BSNL Ranchi & Chairman IETE Ranchi

Sh. Vijay Bhushan Pandey, Chairman ISVE Ranchi & Director TERM A1, Dept. of Telecom

Ranchi, Jharkhand, India

Co-chairman:

Sh. Sanjay Kumar Jha, Past Chairman IETE Ranchi & Executive Engineer Govt. of

Jharkhand

Organizing Secretary:

Dr. Anand Kr. Thakur, SSMC RU Ranchi & Honorary Treasurer IETE Ranchi

General Chair:

Dr. Vijay Nath, BIT Mesra Ranchi & Honorary Secretary IETE Ranchi

Convener:

Dr. Raj Kumar Singh, RLSYC RU Ranchi & Executive Member IETE Ranchi

International Advisory Committee:

Dr. A.A. Khan, Former VC, RU, Ranchi& Fellow Member of IETE New Delhi

Dr. M.K. Mishra, VC, BIT Mesra, Ranchi

Dr. Ramesh K. Pandey, VC, RU, Ranchi

Dr. K.K. Thakur, CGM, ARTTC, BSNL, Ranchi

Dr. Surendra Pal, Professor & Senior Adviser, Satellite Navigation, ISRO Bangalore

Dr. M.S. Kori, Chairman IETE, Technical Program & Publication Committee, New Delhi

Sh. R.K. Gupta, Former President, IETE, New Delhi

Dr. P.K. Barhai, Former VC, BIT Mesra, Ranchi

Dr. Rajendra Prasad, Professor, IIT Roorkee

Sh. R. Mishra, Former CMD, HEC, Ranchi

Dr. S. N. Verma, Former CMD, Energy Development Corporation, Ltd. Jharkhand


4

2nd


th -26


Sh. S.C. Thakur, Chief Engineer, Rural Electrification Energy Distribution Corporation

Limited Jh.

Sh. Ravindra Kr. Rakesh, Editor, Dainik Bhasker, Jharkhand

Sh. Gopal Jha, Journalist, New Delhi

Dr. A.N. Mishra, Former VC, Central University, Jharkhand

Dr. A. Chakrabarty, Professor, IIT Kharagpur

Dr. B.K. Mishra, Professor, BIT Mesra Ranchi

Dr. S. Banerjee, Professor, IIT Kharagpur

Dr. Nandidta Das Gupta, Professor, IIT Chennai

Dr. L.K. Singh, Former Professor, Dr. RML AU, Faizabad

Dr. B.S. Rai, Former Professor, MMMUT, Gorakhpur

Dr. D. Samathanam, Former Adviser & Head TDT, DST New Delhi

Dr. P. Chakrabarty, Professor, IIT BHU

Dr. G. A. Murthy, Scientist-G, DRDO Hyderabad

Dr. N. Gupta, Professor, BIT Mesra, Ranchi & Fellow Member of IETE New Delhi

Dr. M. Srinivasa, Scientist-G, DRDO Hyderabad

Dr. S.C. Bose, Scientist-G, CEERI Pilani

Dr. Arokiaswami ALPHONES, Vice–Chairman, IEEE Singapore Section & Professor, NTU

Singapore

Dr. K. Rajasekhar, Dy. Director General, NIC, DEIT, MoCIT, Govt. of India, Hyderabad

Dr. N.V. Kalyankar, Vice-Chancellor, Gondwana University, Maharastra

Dr. R.P. Panda, Professor, VSSUT, Burla, Odissa

Dr. Allen Klinger, Professor, University of California

Dr. Hisao Ishibuchi, Professor, Osaka Prefecture University, Japan

Dr. T.K. Bhattacharya, Professor, IIT Kharagpur

Dr. V.R. Gupta, Professor, BIT Mesra, Ranchi & Fellow Member of IETE New Delhi

Dr. M. Chakrabarty, Professor, IIT Kharagpur

Dr. A.S. Dhar, Professor, IIT Kharagpur

Dr. D.K. Sharma, Professor, IIT Bombay

Dr. Swaroop Gosh, Assistant Professor, University of South Florida

Dr. S.K. Ghorai, Professor, BIT Mesra, Ranchi & Executive Member of IETE Ranchi

Dr. M. Bhuyan, Professor, Tejpur University, Assam

Dr. S. Hosimin Thilangar, Associate Professor, Anana University, Chennai

Dr. V.N. Mani, Senior Scientist, CMET, Hyderabad

Dr. D. Pal, BITs Pilani Goa Campus, Goa

Dr. V. Kumar, Professor, ISM Dhanbad

Dr. Subir Kumar Sarkar, Professor, Jadavpur University

Dr. Abhijit Bishwas, Professor, Kolkata University


5

2nd


th -26


Dr. D.K. Singh, Professor, NIT Patna, Bihar

Dr. R. Jayavel, Professor, Anna University, Tamilnadu

National Advisory Committee:

Dr. Gaurav Trivedi, Associate Professor, IIT Gwohati.

Dr. B.K. Kaushik, Associate Professor, IIT Roorkee

Dr. M. Bhaskar, Associate Professor, NIT Tirchy

Dr. P. Kumar, Associate Professor, IIT Patna

Dr. K.B. Raja, Professor, Bangalore College of Engineering, Bangalore

Dr. P.R.Thakura, Associate Professor, BIT Mesra, Ranchi & Executive Member of IETE

Ranchi

Dr. S.S. Solanki, Professor, BIT Mesra, Ranchi

Dr. Mahesh Chandra, Professor, BIT Mesra, Ranchi & Executive Member of IETE Ranchi

Dr. S. Kumar, Associate Professor, BIT Mesra, Ranchi & Executive Member of IETE Ranchi

Dr. D.K. Malik, Associate Professor, BIT Mesra, Ranchi

Dr. K.K. Senapati, Assistant Professor, BIT Mesra, Ranchi

Dr. K.K. Patnaik, Associate Professor, IIIT Gwalior

Dr. M. Goswami, Associate Professor, IIIT Allahabad

Dr. Lallan Yadav, Associate Professor, DDU University Gorakhpur

Dr. S. Chakrabarty, Associate Professor, BIT Mesra, Ranchi

Dr. D. Devraj , Professor, Kalasalingam University, Tamilnadu

Dr. J.S. Roy, Professor, KIIT Bhubaneswar

Dr. N.K. Kamila, Professor, CV Raman College of Engineering, Bhubaneswar, Orissa

Dr. B.K. Ratha, Associate Professor, Utkal University, Odessa

Dr. A. Srinivasulu, Professor, Vignan University, Andhra Pradesh

Dr. Manish Prateek, Associate Professor, Petroleum University, Dehradun

Dr. Vijay Laxmi, Associate Professor, BIT Mesra, Ranchi

Dr. V.K. Jha, Associate Professor, BIT Mesra, Ranchi

Dr. N. Chattoraj, Associate Professor, BIT Mesra, Ranchi

Dr. S. K. Vishwakerma, Associate Professor, IIT Indore

Dr. R.K. Lal, Associate Professor, BIT Mesra, Ranchi

Technical Programme Committee:

Dr. J.K. Mandal, Professor, Kalyani University, WB

Dr. Kota Solomon Raju, Scientist-F, CEERI Pilani

Dr. Amalin Prince, Associate Professor, BITS Pilani Goa Campus


6

2nd


th -26


Dr. M. Mishra, Associate Professor, DDU University Gorakhpur

Dr. J. B. Sharma, Associate Professor, Rajasthan Technical University, Kota.

Dr. Umesh Yadav, Associate Professor, DDU University, Gorakhpur

Dr. Prabir Saha, Assistant Professor, NIT Meghalaya

Dr. S.P. Tiwari, Assistant Professor, IIT Jodhpur

Dr. S. N. Shukla, Professor, Dr.RML Avadh University, Faizabad

Dr. B.N. Sinha, Associate Professor, SSMC, Ranchi

Dr. V. S. Rathore, Assistant Professor, BIT Mesra, Ranchi

Dr. S.K. Vishwakerma, Associate Professor, IIT Indore

Dr. P.K. Upadhyay, Assistant Professor, IIT Indore

Dr. Sweta Srivastva, Professor, JIIT, Noida

Dr. Manish Kumar, Associate Professor, MMMUT, Gorakhpur

Dr. A. Arokiasamy, Professor, EGSEC, Nagappattinum

Dr. S. Sriram, Associate Professor, Sastra University,Tamilanadu

Joint Secretary:

Prof. D. Acharya, ISTM Kolkata

Prof. Rajeev Ranjan, ISM, Dhanbad

Prof. Amar Prakash Sinha, BIT Sindri

Prof. Jayant Pal, NIT, Agarpara, Kolkata

Prof. Adesh Kumar, Petroleum University, Dehradun

Prof. J. Dinesh Reddy, BMS College of Engineering, Bangalore

Prof. N. Srinivasa Rao, BMS College of Engineering, Bangalore

Prof. P. Kumar, CIT Ranchi

Sh. A. K. Pandey, BIT Mesra Ranchi

Sh. Dipayan Gosh, GM Aircel Kolkata

Sh. R.K. Kundu, GM IBM Bangalore

Prof. G. S. Gupta, BIT Mesra Ranchi & Co-opted Member IETE Ranchi

Prof. G.K. Mishra, BIT Mesra Ranchi & Co-opted Member IETE Ranchi

Smt. Saroj, Honorary Treasurer ISVE Ranchi

Prof. Jyoti Singh, Joint Secretary, ISVE Ranchi

Prof. Mamta Singh, CIT Ranchi

About ARTTC, Ranchi:- This is a Advanced Regional Telecom Training Centre of BSNL.

It is 12 Km from Ranchi Railway station and 16 Km from Ranchi Airport. Ranchi is surrounded

by hills, waterfalls, forests, and the other places of scenic beauty. Ranchi has a pleasant weather

throughout the year. It is well connected by road, rail and air routes with all the major cities of


7

2nd


th -26


India. The nearest airport and the railway station are in Ranchi. It has regular flight connectivity

with New Delhi, Kolkata, Mumbai and Patna.

About ISVE & IETE: ISVE is non profitable registered society dedicated to serve the

nation. It makes a bridge between industry and academia for organizing the workshops,

summer/winter schools, short term courses, conferences, symposiums and seminars by which

students, research scholars, faculties and scientists come together, work together and share their

knowledge in recent development in engineering, science & technology[www.isve.in]. The IETE

is the National Apex Professional body of Electronics and Telecommunication, Computer and IT

Professionals. The IETE focuses on advancement of the Science and Technology of Electronics,

Telecommunication, Computers, Information Technology and related areas. Towards this end

the Institution promotes and conducts basic engineering and continuing technical education

programmes for human resource development. Both are together committed to innovative

reseacrh, publications in recent trends in electronics & communication engineering

[www.ieteranchi.org]/[www.iete.org].

Registration:

1. Registration fee includes conference kit, breakfast, lunch, dinner and accommodation

charges for two days.

2. Please download the Registration Form from the mail-attachment/website and send scan

copy of filled Registration Form with NEFT receipt through e-mail for early registration. A/C

Name: INDIAN SOCIETY FOR VLSI EDUCATION, A/C Number: 01670110061831, IFSC

Code: UCBA0000167, Bank: UCO Bank, Branch: Mesra Ranchi, Address: BIT Main

Building Mesra, Dist: Ranchi, State: Jharkhand, Contact No: 0651-2275829.

or

A/C Name: I.E.T.E. Ranchi Centre, A/C Number: 31048137361, IFSC Code: SBIN0006951,

Bank: State Bank of India, Branch: Harmu Housing Colony (Ranchi), PO: Harmu, Dist:

Ranchi, State: Jharkhand.

Categories of

Delegates

Before 20th

Dec. 2016

Indian Rs

After 20th

Dec.

2016

Indian Rs

Overseas

USS

Academia 10000 11100 1000

Students 8000 9000 900

Corporate Member 12000 13000 1200

Participants other than

Communication

Authors

2500 3000 50


8

2nd


th -26


3. 10% discount who will not be avail the accommodation & kit facility/ member of

IETE/ISVE. Please inform before the conference & send your membership proof with

your registration form details.

Important Dates:

Conference Schedule Old date Extended date

Paper Submission

Open

5th

Sept.2016 5th

Sept.2016

Paper Submission

Deadline

30th

Oct. 2016 30th

Nov.2016

Author Notification 15th

Nov.2016 10th

Dec. 2016

Registration date 20th

Nov. 2016 15th

Dec.2016

Camera Ready Paper 30th

Nov. 2016 20th

Dec.2016

Conference date 10-11th

Dec. 2016 25-26th

Dec.2016

Accommodation:

Accommodations will be providing in BSNL Guest House, near Jumar River, Hazaribag

Road, Ranchi and in some other Hotels in Ranchi for two days. Accommodation details will be

communicated to the participants after his/her acceptance of papers and papers registration.

Sponsorship Opportunities:

We welcome sponsorship from companies and organizations who wish to show case their

products and services and have the opportunities of networking with academics and practitioners

in the field. With a truly global audience the conference provides an excellent opportunity for

you to show your support for ongoing research and academic excellence by being involved with

such important event. Academic institutions may choose to use sponsorship as a vehicle to

promote their Masters and Ph.D. programmes. We also welcome sponsorship of specific

activities in the conference programme. We believe that sponsoring a conference provides a

superb vehicle to showcase your commitment to academic excellence and pursuit of knowledge.

Your company will benefit from interaction with a highly focused, motivated, engaged and

respective audience in a relaxed environment.


9

2nd


th -26


Sponsorship Type and

Facility

Diamond

Rs. 1,00000/-

Platinum

Rs.

70000/-

Gold

Rs.

50000/-

Silver

Rs.

20000/-

Acknowledge at all events Yes Yes Yes

Complementary booth

space

Yes Yes Yes

List of sponsored displayed

on conference webpage

Yes Yes Yes Yes

Demo slot/Advertisement 20 Min 15

Min

10

Min

5 Min

Logo in proceeding and

distributed to all authors

Yes Yes Yes Yes

Memento & Standee Logo Yes Yes Yes Yes

Banner displayed during

conference

12’x5’ 8’x5’ 6’x4’ 3’x2’

Complementary conference

Registrations with Kit

6 4 3 3

Organizing Secretary

Dr. Anand K. Thakur

2nd

International Conference on Nano-electronics, Circuits & Communication Systems

(NCCS-2016)

ARTTC, BSNL, Near Jumar River Bridge,

Hazaribag Road, Ranchi-835217, Jharkhand, India

Tele No. 0651-2273260, 8877101225, E-mail: [email protected],

[email protected] , [email protected]

Convener

Dr. Raj Kumar Singh

2nd

International Conference on Nano-electronics, Circuits & Communication Systems

(NCCS-2016)

ARTTC, BSNL, Near Jumar River Bridge,

Hazaribag Road, Ranchi-835217, Jharkhand, India

Tele No. 0651-2273260, 9431359955, E-mail: [email protected],

[email protected], [email protected]






10

2nd


th -26


Registration Form

2nd International Conference on

Nano-electronics, Circuits & Communication

Systems

Advanced Regional Telecom Training Center BSNL, Near Jumar River Bridge, Hazaribag Road, Ranchi-835217, Jharkhand, India

Tel: 0651-2273260(BO), Mob. 9973886214(GC), 8877101225(OS), 9431259955(CO)

Web:www.ieteranchi.org,/ www.isve.in, E-mail: [email protected],

[email protected]

Organizer: INSTITUTION OF ELECTRONICS & TELECOMMUNICATION

ENGINEERS & INDIAN SOCIETY FOR VLSI EDUCATION

1. Name of Participant :_______________________________________________________________________

2. Categories (UG/PG/Faculty/Industry) :__________________________________________________________

3. Contact No. :______________________ E-mail ID:__________________________________________

4. Organization :__________________________________________________________________________

________________________________________________________________________

5. Address for Communication:________________________________________________________________

_________________________________________________________________________

_________________________________________________________________________

6. Paper ID:________________________________________________________________________________

7. Paper Title:______________________________________________________________________________

_____________________________________________________________________

8. Name of Authors:_________________________________________________________________________

_______________________________________________________________________

9. Payment:

RTGS / NEFT

Transaction No.

Name of Account Date Amounts Drawee

Bank

Signature of Participant with date: _________________

BO: BSNL Office, GC: General Chair, OS: Organizing Secretary, CO: Convener

http://www.isve.in/



11

2nd


th -26


Paper ID Corresponding

Authors

Paper Title Page

Number

1

NCCS16001

Om Prakash

Fuzzy Prediction Model For Water

Temperature In Scheffler Solar

Reflector

36

2

NCCS16006

Anil Pinapati, R.

Padmavathy

A Reversible Data Hiding Using

Difference-Histogram Modification

On Multi-Directional In Two-

Dimensional Histogram

37

3

NCCS16007

Chandan Kumar, Tanmoy

Maity, K.C. Jana

A Novel Single-Phase Multilevel

Inverter Topology With Reduced

Component Count

38

4

NCCS16008

Aditya Sankar Sengupta,

Ajoy K Chakraborty,

B.K.Bhattacharyya

Designing Of Buck Converter Solely

Powered By Supercapacitors For

Hand-Held Devices

39

5

NCCS16009

K.Srilakshmi,

AVN.Tilak, K.Srinivasa

Rao, Y. Syamala

Energy Efficient 64-Bit

Asynchrobatic Adder

40

6

NCCS16011

Gourab Das,Meenakshi

De,K.K.Mandal

Pv Array’s Resistance &

Temperature Sensitivity Analysis

With Shading Effects

41

7

NCCS16014

Sukesha, Manu

Sharma

Effect Of Location Of Piezoelectric

Sensor Over A Smart Structure

42

8

NCCS16015

Dipti Kumari & Kumar

Rajnish

A Systematic Approach Towards

Development Of Universal Software

Fault Prediction Model Using Object-

Oriented Design Measurement

43

9

NCCS16016 Nivedita Laskar and

Impedance Profile Measurement Of

Integrated Circuit Packages

44


12

2nd


th -26


Bidyut K. Bhattacharyya

10

NCCS16017

Omkar Yadav, Sumit

Singh, Vijay Nath

Design And Implementation Of A

Reaction Timer Using CMOS Logic

45

11

NCCS16018

Shubham Goswami,

Sagnik Mukherjee, Iti

Saha Misra, Deepan

Mukherjee and

Biswanath Chakraborty

A Novel Hybrid Resource Allocation

Scheme For Maximum Fairness

Among Multiple Services

46

12

NCCS16019

Aditya S Sengupta,

Anandita Goswami, Ajoy

K Chakraborty, Bidyut K

bhattacharyya

Modelling Equivalent Circuit For

Supercapacitor Module Voltage

Decay

47

13

NCCS16020

Rajinder Tiwari, Ankita

Tiwari2

An Innovative Design Approach Of

Soc Based Smart Cmos Sensor For

Mixed Signal Processing Based

Applications

48

14

NCCS16029

Priyanka Parihar1, Neha

Gupta2, Vaibhav

Neema3*

, Praveen Singh4

Investigation Of Mtcmos 6t Sram

Cell For Ultra Low Power

Application

49

15

NCCS16030

Neha Gupta1, Priyanka

Parihar2, Vaibhav

Neema3*

, Praveen Singh4

Novel Approach For Sleep Transistor

Sizing To Suppres Power And

Ground Bouncing Noise In Mtcmos

Clustering Technique

50

16

NCCS16031

Suchismita Tewari1,

Suchismita De1, Abhijit

Biswas1 and Abhijit

Mallik2

Investigations On Logic Performance

Of P-Ge/N-Si Hybrid Cmosfets For

Digital Applications

51

17

NCCS16032

S.MUTHUMANICKAM†

and C.ARUN‡

An Efficient Blind Detection

Watermarking Algorithm Using

Range Conversion Method

52


13

2nd


th -26


18

NCCS16033

Mukesh Patidar, Namit

Gupta

Efficient Design And Simulation

Of Novel Exclusive-Or Gate Based

On Nano-Electronics Using Quantum

Dot Cellular Automata

53

19

NCCS16036

Varun Bohra, Soumendra

Kumar Dash, Kripa

Singh Munda, Deepak

Prasad, Vijay Nath

Design Strategy To Smart Toll And

Billing System

54

20

NCCS16037

Sanket P. Singhania1,

Smita A. Lonkar2, K T V

Reddy3

Novel Cell Search Method In Long

Term Evolution System

55

21

NCCS16038

Dalvir Kaur1, Sukesha

Sharma2

Various Feature Extraction And

Classification Techniques

56

22

NCCS16039

Abhinav Kumar1, Mrs.

Sushma Kamlu2

Path Tracking Method Of Alv Model

Based On Adrc Strategy And

Differential Flatness Theory

57

23

NCCS16040

Ravneet Kaur1, Garima

Joshi2, Maninder Kaur

Saggu3, Vishal Sharma

4

Performance Analysis Of

Conventional Sram With Higher

Order Sram Topologies

58

23

NCCS16041

Shashank Shekhar1,

Shanidul Hoque2, Ashraf

Hossain3, and Wasim

Arif4

Performance Analysis Of Time-

Reversal Division Multiple Access

Under Multi-Path Rician Fading

Channels

59

24

NCCS16042

Amninder Singh, Puneet

Jai Kaur

Analysis Of Software Development

Life Cycle Models

60

23

NCCS16043

Sumit Singh1, Abhishek

Pandey2, Vijay Nath

3

Design Of Narrowband 2.69ghz

Cmos Low Noise Amplifier For

Wimax Application

61

24

NCCS16044

Sarita Kumari and

Sarbani Chakraborty

Sensitivity Analysis Of Various

Magneto-Optic Materials Based On

Faraday Rotation Principle

62


14

2nd


th -26


25

NCCS16045

Anil kumar, Partha Paul

A Secure Three - Way Handshake

Authentication Process In Ieee

802.11i

63

26

NCCS16046

Gireesh Joshi1, R.

Padmavathy2, Anil

Pinapati3, Mani Bhushan

Kumar4

Browserguard2: A Solution For

Drive-By-Download Attacks

64

27

NCCS16047

Nishat Aafreen1, Partha

Paul2

Ga Based Energy Optimization In

Traffic Grooming Wdm Optical

Mesh Network

65

28

NCCS16048

Oshin Garg, Sukesha

Sharma, Preeti, Pardeep

Kaur

Piezoelectric Energy Harvesting: A

Developing Scope For Low Power

Applications

66

39

NCCS16049

Deepak Prasad1 & Vijay

Nath2

An Overview Of Temperature

Sensors

67

30

NCCS16050

Abhishek Pandey, Vijay

Nath

A 3.65mw, Op-Amp Based Up-

Conversion Mixer For Zigbee Front-

End Transmitter

68

31

NCCS16051

Vijay Kumar Karan,

Parshuram Thakura,

Amarnath Thakur

Adaptive Compensation Algorithm For

Flux Estimation Of PM BLDC Motor

Drives

69

32 NCCS16052 70


15

2nd


th -26


MESSAGE

I am happy to know that IETE and ISVE Ranchi chapter is organizing two days

International Conference on Nanoelectronics, Circuits and Communication Systems (NCCS-

2016) on 25 -26th

Dec. 2016 at ARTTC, Ranchi. Filling more privileged that it is happening at

ARTTC BSNL Ranchi. I appreciate this initiative and I also believed that the outcomes of this

conference would be very useful for the science fraternity.

Nano technology is continually playing vital role to improve the capability of electronic

products. Nano technology is going to play vital role in make in India dream project. Technology

also made the devices very light & making the product easy to carry. Parallel processing is also

empowered by Nanoelectronics. Nano technology is going to serve the humanity and

environment in positive manner in days to come.

I convey my best wishes for success of the conference and hope the deliberations in the

conference will provide researchers, scientist and engineers the ability to excel in their work. I

also convey my best wishes to the organizers and all delegates coming from different corners of

the country


16

2nd


th -26


MESSAGE

I am delighted to note that IETE Ranchi Centre together with Indian Society for VLSI

Education is organizing a two-day 2nd

International Conference on “Nano-electronics, Circuits

& Communication Systems (NCCS-2016)” on December 25-26, 2016 at ARTTC, BSNL,

Harzaribagh Road, Ranchi.

The increasing needs of present and future computation-intensive applications have

stimulated research in new and innovative high-performance computing systems. Nano-

electronic systems are one such new and exciting area of R&D that promises huge opportunities

in today’s market. The boundaries between state-of-the-art and innovation constituting the

computing frontiers must be pushed forward to provide the support required for the advancement

of all science domains and applications.

I hope that this conference focuses on a wide spectrum of advanced technologies and

radically new solutions; foster communication among many scientific and technological

disciplines and transfers the knowledge to the students, educators, researchers, scientists and

engineers alike, working at the interface of nanotechnology and the many fields of electronic

materials, photonics, bio-and medical devices, alternative energy, environmental protection, and

multiple areas of current and future electrical and electronic applications.

I am sanguine that this international event will provide a platform to academic and

industry to disseminate their latest innovations and practices and help the engineering

community to collaborate and create new and innovative technologies.

I convey my best wishes for the success of the International Conference.

(Lt Gen (Dr) AKS Chandele, PVSM, AVSM (Retd)

President, IETE


17

2nd


th -26


MESSAGE

It gives me great pleasure to know that Indian Society for VLSI Education (ISVE) and

IETE, Ranchi is organizing two days International Conference on Nano-electronics, Circuits &

Communication Systems (NCCS-2016) on 25 -26th

Dec 2016.

Nanoelectronics technology has dramatically improved the capabilities of computers and

communication systems, while also fuelling the growth of completely new applications such as

personal computers. Growing extremely fast and providing exceptionally powerful and

inexpensive tools to manipulate electronic signals, microelectronics has become the cornerstone

of information technologies. These computer and communications technologies are the basis for

changes such as automation, energy conservation, and pollution control in offices, factories,

automobiles, and homes; supercomputers for applications from weather prediction to

computational research; new capabilities in financial services; advanced telephone and television

systems; and complex weapons systems for national defence. Therefore, each of these areas is

critically dependent on nano-electronics technology.

The dramatic growth of technology has prompted observers to describe it as a nano-

electronics revolution. Continuing to shrink the dimensions of electronic devices is important in

order to further increase processor speed, reduce device switching energy, increase system

functionality, and reduce manufacturing cost per bit.

I convey my best wishes for the success of the Conference and I am sure that it will bring

together the brightest engineers and scientists from all over the world, through collaboration and

exchange of ideas.

( Smriti Dagur )


18

2nd


th -26


MESSAGE

I am glad to learn that a two-day 2nd

International Conference on “Nano-electronics,

Circuits & Communication Systems (NCCS-2016)” is being organized under the aegis of IETE

& ISVE on December 25-26, 2016 at ARTTC, BSNL, Ranchi.

The advances in the Electrical & Electronic engineering sector i.e., sensors and

instrumentation, control, photonics, sustainable power systems, telecommunications, intelligent

systems, medical systems, integrated circuits and embedded systems have been remarkable. The

future belongs to nano-electronics.

These technological advances are fundamental ingredients of a global knowledge economy,

which are not only challenging the nature of engineering practice but also, seek profound skills.

The growing awareness of the importance of technological innovation in achieving

economic competitiveness and national security is demanding a new priority for basic engineering

research not only for our country but world at large.

The topic chosen is of great interest and I am certain that the International Conference will

provide the perfect platform to bring together subject matter experts and researchers to discuss and

debate relevant issues and make useful contributions to the knowledge of participants.

I wish this event all the very best and grand success.

(Maj Gen P K Jaggia, VSM (Retd))

Secretary General


19

2nd


th -26


MESSAGE

I come to know that the Institution of Electronincs & Telecommunication

Engineers(IETE) and Indian Society for VLSI Education(ISVE) Ranchi are organizing two days

second International Conference on Nanoelectronics, Circuits and Communication

Systems(NCCS-2016) on 25-26th

Dec 2016 at ARTTC BSNL near Jumar River H.B. Road

Ranchi. I appreciate this initiative and believe that outcome of this conference would be useful

for the technology fraternity.

Nano technology is a rapidly growing branch of modern science & technology field.

Which is going to serve the humanity and enviroment in very frontier manner. I being a Botanist,

I know that the living world is constituted by Nano-biomolecules like DNA, RNA, Protiens,

Amino acids, Sugars, liquids etc.

I coney my good wishes to the organizers and all delegates coming from different corners of

India and abroad.


20

2nd


th -26


Professor Anwar A. Khan Ph.D., FIETE (India), SMIEEE (USA)

Former Professor of Physics(Electronics) &

Former Vice Chancellor

Ranchi University

Hera Apartment, Flat # 2A,

Behind Capitol Hill,

Main Road, Ranchi‐834001, India

Email: [email protected]

Email: [email protected]

Tel: +91 651 2330674

Mob: +91 9431108830

Message

I am happy to learn that IETE & ISVE Ranchi Centre is going to organize 2nd

International Conference on “Nano‐electronics, Circuits & Communication Systems” during

December 25‐26, 2016 at ARTTC, BSNL, Ranchi. The theme selected for the conference is of

great global concern as the innovative researchers in different areas of Electronics, Devices and

Communication play a pivotal role in improving the quality of human life on this planet. I

believe that in India, a new evolutionary vision is taking shape and that young innovators may

now be our most precious resource. I trust that the Conference will resonate with the theme of

Cultural digital evolution and the transformational dynamics of the people of India. The

Conference inspires the young innovators which may nicely be expressed in a quote of Mahatma

Gandhi: “In a gentle way, you can shake the world."

Wishing you all a very fruitful and rewarding Conference.

Anwar A. Khan


21

2nd


th -26


MESSAGE

I am delighted to see that our IETE Ranchi centre and ISVE is organizing international

conference on Nano-electronics, Circuits & Communication Systems (NCCS-2016).In recent

years science and Technology which are hand in glove , are advancing at a very past pace. In the

modern world only those notations which can keep abreast of science and Technology can

progress.

I sincerely hope this conference provides the apt platform for exchange of knowledge and

for identifying newer emerging research facilities.

Here , I acknowledge the hard work put in by my Ranchi chapter team members. Best

wishes and heartiest gratitude to on and all , wish you an enjoyable and fruitful experience

during the conference.

(Dr. R K Singh)

Founder Chairman, IETE Ranchi Chapter


22

2nd


th -26


University of Calcutta

UNIVERSITY COLLEGE OF TECHNOLOGY

INSTITUTE OF RADIOPHYSICS AND ELECTRONICS

Telephone: (+91) (33) 2350-9115/9116/9413

Telegram: INRAPHEL

Fax: (+91) (33) 2351-5828

E-mail : [email protected]

SISIR MITRA BHAVAN

92, Acharya Prafulla Chandra Road

Kolkata – 700009, INDIA

Message

I am very glad to note that Indian Society for VLSI Education, Ranchi is organizing two

days International Conference on Microelectronics, Computing & Communication Systems

(MCCS-2015) on November 14-15, 2015 at Advanced Regional Telecom Centre, BSNL

Hazaribag Road Ranchi-835217. Research, development and innovations in the broad areas of

Microelectronics, Computing & Communication Systems have revamped new heights during the

last few decades. Remarkable advancements in these areas with the cutting-edge technologies

have entered every phase of our societal, professional and personal life. With the continued

contributions by the academic and industrial personnel in the areas of micro- and nano-

electronics, computing algorithms and computer networks, and also communication circuits and

systems, novel and attractive technologies are coming up, achieving many more milestones and

meeting the challenges ahead for the welfare of mankind.

I sincerely hope, with multitude of exciting research area coverage, MCCS-2015 would

be able to provide an appropriate platform for experts, academic and industrial people, and

researchers to share and exchange their knowledge.

Abhijit Biswas

Department of Radio Physics and Electronics

University of Calcutta


23

2nd


th -26


Kalyani-741235, Nadia

West Bengal, India

Phone: (033) 25809617 (O)

Mobile: +91- 9434352214

e-mail: [email protected]

Univers i ty o f Kalyani FACULTY OF ENGINEERING, TECHNOLOGY & MANAGEMENT

1) Prof. J. K. Mandal 2) DEPT. OF CSE, FACULTY OF ENGINEERING,

TECHNOLOGY & MANAGEMENT UNIVERSITY OF KALYANI

B.

MESSAGE

I am glad to learn that IETE & ISVE Ranchi Centre is organizing two days Second

International Conference on Nano-electronics, Circuits & Communications Systems (NCCS

2016) on 25th and 26th December 2016 at ARTTC, BSNL, near Jumar River, Hazaribag Road,

Ranchi

In my opinion this is a very good platform to share the current trend of technology among

researchers, scholars and industry people.

My best wishes for NCCS 2016.

Prof.(DR.) J. K. Mandal

Professor & Former Dean, FETM

Kalyani University


24

2nd


th -26


INDIAN INSTITUTE OF TECHNOLOGY

JODHPUR Old Residency Road, Ratanada, Jodhpur - 342011, Rajasthan, India

Shree Prakash Tiwari, Ph.D., Senior Member, IEEE Assistant Professor, Electrical Engineering

Message

Dear Organizers, Participants, and Other Stakeholders of NCCS-2016,

It is great to know that IETE & ISVE Ranchi Centre is organizing International

Conference on Nano-electronics, Circuits & Communication Systems (NCCS-2016) during

December 25th to 26th, 2016. Ranchi itself has been a hub for learning and education, and home

for many Institutes and Institutions of great repute for last many decades. This event being

organized in Ranchi consecutively on second time is a wonderful step. The broad theme of the

conference in various areas of Electrical Engineering, Electronics & Communication

Engineering, and Computer Science & Engineering will certainly provide an excellent platform

for the researchers to showcase their work through oral and poster sessions and listen to their

peers from academia and industry working in similar areas. This international conference will

also bring together the various stake holders of academia and industry, and offer an opportunity

to all to collaborate and network.

I heartily congratulate the Conference Organizers for organizing NCCS-2016, and wish

all the best to all the Members and Volunteers for making this conference a successful and

fruitful event.

Best wishes

Shree Prakash Tiwari


25

2nd


th -26


MESSAGE

It is indeed a great occasion for everyone who is part of second International Conference on

Nanoelectronics, Circuits and Communication Systems(NCCS-2016) the great scientific

event organized by IETE & ISVE Ranchi on 25-26th

Dec 2016 at ARTTC BSNL near Jumar

River H.B. Road Ranchi.

The theme of Nanoelectronics, Circuits and Communication Systems chosen for conference

is very apt. in order to expedite the process of develoment and take our nation towards new

height to excellence. It is essential that we take to a process of massive applications of

Nanoelectronics.


26

2nd


th -26


MESSAGE

I come to know that Indian Society for VLSI Education, Ranchi and Institution of

Electronics & Telecommunication Engineers (IETE) Ranchi is organizing two days 2nd

International Conference on Nanoelectronics, Circuits and Communication Systems (NCCS-

2016) on 25 -26th

Dec, 2016 at ARTTC, Ranchi. I appreciate the theme of this event and

participation of the delegates. I think that outcomes of this conference will add in the

development of our country.

I congratulate the members of organizing committee for their effort in the organization of

the event and wish a great success of the conference.

Sh. Sanjay Kumar Jha

Executive Engineer, Govt. of Jharkhand

Past Chairman, IETE, Ranchi Centre.


27

2nd


th -26


Pandey Vijay Bhushan Prasad

I.T.S. D.G.M. (Term Cell1) DOT,

BSNL, Ranchi.

BHARAT SANCHAR NIGAM LIMITED

(A Government of India Enterprise)

Office of the Deputy General Manager (Mtce)

Eastern Telecom Region

4th

Floor, ARTTC BSNL Ranchi-835 217

MESSAGE

It is my pleasure that Indian Society for VLSI Education (ISVE) Ranchi & Institution

of Electronics & Telecommunication Engineers (IETE) Ranchi is organizing two days 2nd

International Conference on Nanoelectronics, Circuits & Communication Systems (NCCS-

2016) with some other National & International Societies on 25-26th

Dec-2016 at ARTTC, BSNL

near Jumar River Bridge, Hazaribag Road, Ranchi. It is my pleasure to welcome all of you who

participate in the journey of Advances in Nanoelectronics, Circuits & Communication Systems

and their technologies have led to many challenging problems that require new performance

evaluation tools and methods to keep up with their rapid evolution and increasing complexity.

This Conference is intended to provide an international forum for scientists, engineers,

practitioners, network and communication users and students from Academia and Industry to

share and exchange their experiences, discuss challenges, present original ideas, and report state-

of-the-art and in-progress research results on all aspects of performance evaluation of


28

2nd


th -26


Nanoelectronics, Circuits & Communication Systems in the field of Electrical, Electronics,

Computer, Communication and Information Technology, Mechatronics, Environmental Science

& Engineering, Bioengineering and their applications in business, academic, industry and other

allied areas .

This international Conference attracted research papers from various countries across the

world, which was rigorously reviewed by the National & International Advisory Committee

members and Subject Experts. I take this opportunity to thank them for their professionalism and

valuable comments made to the authors. The accepted papers will be published in conference

proceedings by Springer with ISBN number and extended versions of papers will be published in

SCOPUS, SCI and some other indexed journals.

Many people have kindly helped us to prepare and organize the NCCS-2016 Conference.

First of all, I would like to thank Chairman Committee, Co-chairman Committee, Organizing

Secretary, General Chair, International Advisory Committee, National Advisory Committee,

Technical Programme Committee, and Joint Secretary for their support, guidance, and help for

making the Conference a successful event. Also, I would like to give my special thanks to all

who helped and contributed to the success of this Conference. Finally, I would also like to thank

all the authors and participants for selecting the NCCS-2016 Conference to submit their

contribution.

(Pandey Vijay Bhushan Prasad )

Chairman ISVE


29

2nd


th -26


MESSAGE

With extreme humility and great pleasure, I take this opportunity to welcome you all for

this 2nd international conference on nano-electronics, circuit and communication systems

(NCCS-2016). The Facets of science and technology are changing very fast. Engineering and

Technology are becoming increasingly inter and multi-disciplinary and it calls for multi-

institutional, multi-country participation.

The main objective of this conference is to provide a diverse yet comprehensive forum to

deliberate on the recent advances and futuristic trend in various fields of engineering and

technology. I sincerely hope this conference provides the apt platform for exchange of

knowledge and for identifying newer emerging research facilities.

Here, I acknowledge the hard work put in by my Ranchi chapter team members. Best

wishes and heartiest gratitude to on and all, wish you and enjoyable and fruitful experience

during the conference.


30

2nd


th -26


MESSAGE

It is eminence pleasure for us that Indian Society for VLSI Education (ISVE) Ranchi

& Institution of Electronics & Telecommunication Engineers (IETE) Ranchi centre gives

me the opportunity for General Chair in two days 2nd

International conference on

Nanoelectronics Circuits and Communication Systems (NCCS-2016) organised at Advanced

Regional Telecom Training Centre BSNL near Jumar River Hazaribag Road Ranchi on 25-26th

Dec -2016. Really this conference will provide the international forum to exchange research

ideas in the area of VLSI Design, Nanoelectronics, Circuits, Computing, Communication

Systems, Analog and Digital Signal Processing, Embedded System Design, Robotics, Intelligent

Instrumentation, Green Energy, Smart Power Plants, Smart Grid, Space Mission, Biomedical

Instrumentation, Bio-Engineering, Image Processing, Civil and Environmental Science, E-

governance, etc. I hope this conference will give the platform for the researchers to exchange

their ideas and publish his article in highly reputed publications. The main focus of this

conference is to enhance the feasibility of electronic system design and manufacturing in the

country. As everybody know my Country is good consumers of electronics goods, but

production is approx 5 to 10% of total consumptions. Now, Indian Govt has taken very good

initiatives for Cashless India, Digital India. But systems are not so easy it is little bit


31

2nd


th -26


sophisticated but this forum will trend to people for achieving his/her target. Surely this

conference will provide the guidance by expert researchers how to develop electronic goods in

enough amounts in the country and support the cashless systems. On behalf of the general chair

& Hon. Secretary, IETE Ranchi I welcome to all the participants, expert speakers, session chairs,

international and national advisory board members, technical program committee members,

expert reviewers, technical and nontechnical persons, media persons, intellectual persons of India

and abroad for his/her constant support and inspiration for conducting this conference

successfully. These societies are continuously support to government activity to trend the young

engineers, researchers, professors by organising conference, symposium, workshop, short term

courses, summer and winter schools in VLSI design for electronic system design and

manufacturing(ESDM). Once again I heartily welcome to all associated members from district,

state, country and abroad who are directly and indirectly supporting to this conference for grand

success.

Dr. Vijay Nath

BIT Mesra Ranchi

Hon. Secretary, IETE Ranchi

General Chair_NCCS-2016


32

2nd


th -26


MESSAGE

It is a matter of extreme pleasure that Indian Society for VLSI Education, Ranchi &

Institution of Electronics & Telecommunication Engineers (IETE) Ranchi is organizing two

days 2nd International Conference on Nanoelectronics, Circuits and Communication Systems

(NCCS-2016) on 25 -26th

Dec 2016 at ARTTC, Ranchi. The “Digital India” and “Skilled India”

are the vision of our Hon’ble Prime Minister Sri Narendra Modi. So, the theme and sub-themes

of this conference is designed to come out with the authentic research works in the field of

Electronics and Telecommunication.

I welcome all delegates from International arena as well as the different corners of the

country for their active participation in the conference. I also appreciate the executive capacity of

Dr. Vijay Nath and all the best to the members of the organizing committee.

Dr. Anand Kumar Thakur

OrganizingSecretary_NCCS-2016 Hon. Treasurer, IETE, Ranchi Centre


33

2nd


th -26


MESSAGE

With immense pleasure, I welcome you all in the second edition of International

Conference on Nano-electronics, Circuits & Communication Systems on Dec. 25-26, 2016,

in Ranchi, the capital city of Jharkhand organized by Institution of Electronics and

Telecommunication Engineers and Indian Society for VLSI Education. The conference aims

to bring together scientists, researchers, engineers, and students from the academia and industry

to an international platform to share and exchange their ideas, experiences, knowledge and

technological advancements primarily in the field of Nano-electronics, Circuits &

Communication Systems and others. The conference will see, from inaugural session to technical

sessions including oral presentation, poster presentation and online presentation spread over two

days, the experts, participants and delegates discussing and exploring new avenues in the focal

theme field of the conference. Due care has been observed to ensure better comfort to all the

participants in all capacity during their stay for the conference.

My best wishes to all the participants for the success of the conference.

Raj Kumar Singh


34

2nd


th -26


List of Messages of Eminent Persons

Message of CGMT BSNL Ranchi Sh. K. K. Thakur

Message of President IETE New Delhi Dr. A. K. S. Chandele

Message of Former President IETE New Delhi Smt. Smiriti Dagur

Message of Secretary IETE New Delhi Sh. P. K. J. Jaggia

Message of Vice Chancellor, RU Dr. R. K. Pandey

Message of Former Vice Chancellor, RU Dr. A.A. Khan

Message of Founder Chairman, IETE Ranchi Dr. R K Singh

Message of Keynote Speaker Dr. Abhijit Biswas, University of Calcutta

Message of Expert Invited Lecture Dr. J.K. Mandal, Kalyani University

Message of Expert Invited Lecture Dr. S.P. Tiwari, IIT Jodhpur

Message of Expert Invited Lecture Dr. Manish Mishra, DDU University

Gorakhpur

Message of Past Chairman, IETE Ranchi Sh. Sanjay Kumar Jha, Executive Engineer

Govt. of Jh.

Message of Chairman IVSE, Ranchi Sh. Pandey Vijay Bhushan Prasad, DGM

Term cell 1, DOT Ranchi

Message of Chairman IETE, Ranchi Sh. Ajay Kumar AGM (HR) ARTTC BSNL

Ranchi

Message of General Chair NCCS 2016 Dr. Vijay Nath, BIT Mesra, Ranchi

Message of Organizing Secretary NCCS 2016 Dr. Anand Kr. Thakur SSMC, RU

Message of Convener NCCS 2016 Sh. Raj Kumar Singh

List of Session Chair Persons

S.N. Name of Chair Persons Institute/ University

1 Dr. A. A. Khan Ranchi University

2 Dr. Abhijit Biswas University of Calcutta

3 Dr. P.K. Barahi Former VC BIT Mesra

4 Dr. J.K. Mandal Kalyani University

5 Dr. J.S. Roy KIIT Bhubaneswar

6 Dr. S.P. Tiwari IIT Jodhpur

7 Dr. K. Khatua NIT Rourkela

8 Dr. Mahesh Chandra BIT Mesra

9 Dr. P.R. Thakura BIT Mesra

10 Dr. R.K. Lal BIT Mesra

11 Dr. S.S.Tripathi BIT Mesra

12 Dr. K.K. Senapati BIT Mesra

13 Dr. V.K. Jha BIT Mesra

14 Dr. Vijay Nath BIT Mesra

15 Dr. Anand K. Thakur SSMC RU

16 Dr. I. Mukherjee BIT Mesra

17 Dr. A. Islam BIT Mesra

18 Dr. Dileep Kr. Upadhyay BIT Mesra


35

2nd


th -26


19 Dr. K. Solomon Raju CEERI Pilani

20 Dr. Manish Mishra DDU GU

21 Dr. Gaurav Trivedi IIT Guwahati

22 Dr. P. Kumar IIT Patna

23 Prof. Richa Pandey BIT Mesra

24 Dr. Umesh Yadav DDU GU

25 Dr. Vijay Laxmi BIT Mesra

26 Dr. A.K. Tiwari BIT Mesra

27 Dr. N. Chattoraj BIT Mesra

28 Dr. Sukalayan Chakraborty BIT Mesra

29 Dr. Rajeev Agarwal BIT Mesra

30 Dr. D. Devraj KLU Tamilnadu

31 Dr. Manish Mishra DDU GU

32 Dr. S.S. Sahu BIT Mesra

33 Dr. Sanjeet Kumar BIT Mesra

34 Sh. Vijay Bhusan Pandey ARTTC, BSNL Ranchi

35 Sh. Ajay Kumar ARTTC, BSNL Ranchi

36 Dr. S. K. Mahapatra BIT Mesra

37 Dr. R. K. Sinha BIT Mesra

38 Dr. Soma Berman University of Calcutta

39 Prof. D. Acharjee ISTM Kolkata

40 Prof. Shahiruddin BIT Mesra, Patna Campus

41. Dr. Vinay Gupta Delhi University


36

2nd


th -26


NCCS16001

FUZZY PREDICTION MODEL FOR WATER TEMPERATURE IN

SCHEFFLER SOLAR REFLECTOR

Om Prakash

Department of Mechanical Engineering, Birla Institute of Technology, Mesra,

Ranchi (INDIA)

[email protected]

Abstract— In this paper, study about the process and the performance of

Scheffler reflector. For this system, the simulating software Fuzzy logic in

MATLAB software will be used. Firstly, the input temperature, the surface

temperature and according to that the output temperature were taken. These

values were compared with the practical values. The storage reservoir is

placed at the central point. After getting the results, it has been investigated

that the Fuzzy logic can be used proper output with least error. It has been

found that the model can be performed at different-different places with

different weather condition like ambient temperature, solar radiation and

humidity.

Keywords— Scheffler reflector, Fuzzy logic, temperature.



37

2nd


th -26


NCCS16006

A REVERSIBLE DATA HIDING USING DIFFERENCE-HISTOGRAM

MODIFICATION ON MULTI-DIRECTIONAL IN TWO-DIMENSIONAL

HISTOGRAM

Anil Pinapati1, R. Padmavathy2

1,2 Dept. of C.S.E, NIT, Warangal, Telangana, India,

[email protected] [email protected]

2

Abstract— A new approach in Reversible Data Hiding (RDH) is introduced in

proposed work named as Difference Histogram Modification on Multi-

Directional (DHMMD). This method achieves better embedding capacity and

Peak Signal to Noise Ratio (PSNR) compared with the existing methods.

Recently Li’s proposed a method which embed the data in four

directions (i.e., left, right, up, down), the proposed work enhanced the Li’s

method with one more direction(i.e., diagonally up and down) for

embedding. This modification leads to get more pixel pairs for embedding and

less for shifting. This eventually increases the embedding capacity. The

overhead data (information about embedded data and LSB bits) will be

embedded in watermarked image itself using Least Significant Bit(LSB)

Replacement. Gradient-Adjusted-Prediction (GAP) and Noise Level was

adopted for finding the priority pixel pairs for embedding. This method

achieves a better PSNR value more than 50dB in majority of images from

USC-SIPI database when compared with earlier RDH methods.

Keywords— Image Authentication, Difference Pair Mapping (DPM), Reversible

Data Hiding (RDH), Difference Histogram Modif ication on Multi Directional

(DHMMD).




38

2nd


th -26


NCCS16007

A NOVEL SINGLE-PHASE MULTILEVEL INVERTER TOPOLOGY WITH

REDUCED COMPONENT COUNT

Chandan kumar1, Tanmoy Maity2, K.C. Jana3

1,2Dept. of Mining Machinery, IIT (ISM), DHANBAD Jharkhand, INDIA 3Dept. of Electrical Engg. IIT (ISM), DHANBAD Jharkhand, INDIA

[email protected]

Abstract— Multilevel inverter has emerged as a better alternative for various

applications (medium as well as high power) meeting the standards. As

compared to the conventional two-level inverters, multilevel inverters are

superior due to less electromagnetic interference and lower harmonic

distortion. In this paper, a novel generalized single phase multilevel inverter has

been proposed. This configuration uses fewer numbers of total components as

compared with the existing inverters (especially for higher levels). Hence, the

total cost is reduced and complexity is also reduced for higher voltage levels.

The comparison has been done in terms of number of DC sources, switches,

diodes. The topology is simulated for 19-level employing SPWM as the control

strategy, being simulated in MATLAB/SIMULINK environment and validated this

simulation by using real-time digital simulator (OP-5600).

Keywords— Multilevel inverter (MLI), Power Electronics, carrier-based PWM,

Real-time digital simulator (RTDS).



39

2nd


th -26


NCCS16008

DESIGNING OF BUCK CONVERTER SOLELY POWERED BY

SUPERCAPACITORS FOR HAND-HELD DEVICES

Aditya Sankar Sengupta1, Ajoy K Chakraborty2, B.K.Bhattacharyya3

1,2Dept. of Electrical Engineering, NIT Agartala, India 3Dept. of Electronics and Communication, NIT Agartala, India

[email protected], [email protected], [email protected]

Abstract— The idea presented in this paper is the use of supercapacitor arrangement as the only input power source for a dc-dc buck converter. First the designing of a variable input-constant output buck converter with input voltage based closed loop PWM control has been discussed. This buck converter solely operates on two voltage supplies for a maximum load currents ranging from 400mA to 1.5A. Eventually, the two voltage sources are replaced by supercapacitor arrangements. In this work the operation of a dc analogue circuit from a supercapacitor module arrangement has been shown. These supercapacitor module arrangements provide a time varying decaying input voltage to the buck converter circuit but its output voltage is kept constant by proportionately varying the duty ratio with the decaying input voltage across the supercapacitor arrangement. The buck converter and all the components for the closed loop PWM control circuit are supplied solely by the supercapacitor module arrangements. The entire circuit design has been done by cheery picking the components having wide range of operating voltages. This circuit topology can be used for low to medium voltage applications where a variable dc input is supposed to yield a constant output voltage at a constant current and also can be in applications like mobile phones in place of battery since supercapacitor has a very short charging time due to low ESR values of the supercapacitors. The operating frequency is in range of 1to 2.5Khz.

Keywords— PWM control ,supercapacitor, inductor, open-loop, closed loop,

buck.





40

2nd


th -26


NCCS16009

ENERGY EFFICIENT 64-BIT ASYNCHROBATIC ADDER

1 K.Srilakshmi, 2 AVN.Tilak, 3 K.Srinivasa Rao, 4 Y. Syamala

1 2 4 Gudlavalleru Engineering College, Gudlavalleru, 3 TRR College of Engineering, Inole.

[email protected], 2 [email protected], 3 [email protected],

[email protected]

Abstract— A radix-four 64-bit Carry Look-ahead Adder (CLA) is implemented

using CMOS and FinFET based asynchrobatic logic. The performance of

designed adder circuits is assessed by comparing their power, energy and

power-delay product with that using 45nm static CMOS technology over a wide

range of supply voltages and frequencies. The results obtained reveal power

and energy savings of upto 82% and 97% for CMOS and FinFET asynchrobatic

adders respectively as compared to static CMOS circuits. A maximum PDP

improvement of 89.47% at 0.5 V supply voltage is obtained with FinFET

technology.

Keywords— Asynchrobatic logic; Fin-FET; Low power; Radix-four; Carry Look-

ahead Adder.






41

2nd


th -26


NCCS16011

PV ARRAY’S RESISTANCE & TEMPERATURE SENSITIVITY

ANALYSIS WITH SHADING EFFECTS

Gourab Das1,Meenakshi De2,K.K.Mandal3

1,2,3Department of Power Engineering Jadavpur University Kolkata-700098,India

[email protected]

Abstract— Vast growing global concern of solar energy in last few years has

bought to focus the maximum power point tracking and module mismatch

losses. Photovoltaic energy is the exhaustible, clean and pollution free energy.

Mainly, the losses are occurring by partial shading of the array and different

types of solar modules. These losses can be reduced by different parameter

analysis. This paper represents the novel method to forecast existing PV array

for all. The efficiency of solar module is influenced by different shading

configuration. There are six different interconnection schemes, which show

reliable power production forecast under normal operating condition. PV is the

method of generating electric power converting i.e. solar radiation into

electrical power using semiconductor devices exhibits the photovoltaic effects.

The analysis of I-V and P-V curves at varying solar irradiation levels and

temperatures have been obtained. In this study, a new theoretical model,

offering a good compromise between simplicity and accuracy, was developed in

Matlab to determine the parametric study of different types of solar module to

demonstrate a feasibility and reliability of the simulation model.

Keywords— Photovoltaic (PV) module; Sensitivity; Maximum power point

tracking (MPPT); current over voltage (V-I); power over voltage (P-V); Partial

shading;



42

2nd


th -26


NCCS16014

EFFECT OF LOCATION OF PIEZOELECTRIC SENSOR OVER A

SMART STRUCTURE

Sukesha1, Manu Sharma2

1,2UIET, Punjab University, Chandigarh, India

[email protected]

Abstract— A square cantilevered smart plate instrumented with piezoelectric

sensor is considered in this work. Finite element model of the plate is done using

Hamilton’s principle. Only first three modes are obtained using modal

truncation. Time response of sensor voltage is observed at different element

locations. Piezoelectric sensor voltage in open loop is compared for different

element locations. Simulations are performed using MATLAB software.

Keywords— piezoelectric sensor; finite element model; smart structure.



43

2nd


th -26


NCCS16015

A SYSTEMATIC APPROACH TOWARDS DEVELOPMENT OF

UNIVERSAL SOFTWARE FAULT PREDICTION MODEL USING

OBJECT-ORIENTED DESIGN MEASUREMENT

Dipti Kumari 1 & Kumar Rajnish2

1,2Department of Computer Science & Engineering, BIT Mesra, Ranchi, Jharkhand-835215

[email protected]

Abstract— This paper discusses a new systematic approach towards

development of universal software fault prediction model for reliability and

quality improvement of software systems by predicting fault-prone module

before testing. Model utilizes the classification capability of data mining

techniques and most important Object-oriented properties of software system

which is stored in the form of knowledge in software metrics to classify the

software module as fault-prone or not fault-prone. A decision tree is constructed

using a different algorithm like Hoeffding tree (VFDT) for existing project data in

order to gain information for the purpose of decision making whether a

particular module is fault-prone or not. The gained information is converted into

fuzzy rules and integrated with fuzzy inference system to predict fault-prone or

not fault-prone software module for target data. The goal is to help software

manager to concentrate their testing efforts to fault-prone modules in order to

improve the reliability and quality of the software system.

Keywords— fuzzy-profile; Object-oriented metrics; decision tree; fault-

prediction



44

2nd


th -26


NCCS16016

IMPEDANCE PROFILE MEASUREMENT OF INTEGRATED CIRCUIT PACKAGES

Nivedita Laskar and Bidyut K. Bhattacharyya (Fellow, IEEE)

Department of ECE NIT Agartalla, Agartalla India

[email protected]

Abstract— In this paper, we will discuss the drawbacks on the impedance measurement methodology developed by Intel for measuring the impedance profile of the power delivery network (PDN) of a central processing unit (CPU) package and the encapsulated silicon chip inside the package. It is found that Intel's methodology does not work to measure the accurate value of the impedance profile as a function of frequency. The Fourier Series Method is used with an assumption that the current drawn by the device and the corresponding voltages measured inside the chip as a function of time. It is found that measured impedance profile does not match with the analytical calculations, even for a simple PDN circuit with one resonance frequency. The reasons are discussed in this paper. It is also shown that all the assumptions Intel made needs to be corrected to get accurate values of the integrated die and package impedance profile measurements for any PDN as a function of frequency. It is also important that one needs to eliminate the transient data (Depends on the resonance frequencies of PDN), which will be riding on the top of the steady state data (Forced Current Function), for the generation of continuous impedance vs. frequency data in a single shot measurement. Normally an arbitrary current profile was assumed, by some hand waving argument by Intel and also IBM. Part of the measurement error was originated from that hand waving assumption on the current drawn by the device. This paper will also elevate how to eliminate the transient effect on the voltage measurements so that one can determine the correct Fourier Coefficients of the measured voltage to estimate accurately the impedance profile. Even after this correction, the measured value of impedance still has large errors due to current drawn by the device assumption. This assumption is pure square wave forced current function generated inside the device due to clock toggling on and off for some fixed amount of time.

Keywords— Power Deliver Network, Die capacitance, Package Inductance, Rate of Change of current, CPU PDN.



45

2nd


th -26


NCCS16017

DESIGN AND IMPLEMENTATION OF A REACTION TIMER USING CMOS LOGIC

Omkar Yadav1, Sumit Singh2, Vijay Nath3,

1,2,3VLSI Design Group, Department of Electronics & Communication Engineering

Birla Institute of technology, Mesra, Ranchi, India

[email protected], [email protected],

Abstract— The paper presents an overview of a Reaction timer having an

accuracy up to two decimal places (which is extendable). Three Decade

counters constitute the circuitry of this reaction timer wherein each of the

Decade counter in turn is connected to four Master-Slave JK Flip-Flops to form a

combinational circuit. A Delay signal is also introduced at the input so that the

output is genuine. The whole simulation process is carried out in cadence

virtuoso analog design environment of gpdk045 nm technology at a supply

voltage of 1 V.

Keywords— Decode Counter, Master Slave, J-K Flip flop.




46

2nd


th -26


NCCS16018

A NOVEL HYBRID RESOURCE ALLOCATION SCHEME FOR MAXIMUM FAIRNESS AMONG MULTIPLE SERVICES

Shubham Goswami1, Sagnik Mukherjee2, Iti Saha Misra3, Deepan Mukherjee4 and

Biswanath Chakraborty5

1,2,3,4,5Deprtment of Electronics and Telecommunication Engineering, Jadavpur

University, Kolkata-700032, India

[email protected],[email protected] ,[email protected], [email protected], [email protected]

Abstract— A hybrid resource allocation scheme has been designed to maximize

the fairness among multiple services. The algorithm developed is a combination

of priority queuing and weighted fair queuing. At first the optimum weight

distribution to achieve maximum fairness has been obtained using Particle

Swarm Optimization. Later the practical implementation of the real time server

has been done with two proposed methods viz. Regression Analysis and Lookup

Table Search. The optimized results have been generated offline by the

algorithm to be used later by the server i.e. during real time behavior. The

algorithm serves as a general tool for resource allocation which can be applied

in domains like telecommunication (radio resource management in BWA

networks) or computer networks. Validation of the proposed allocation scheme

is made for 5 services for WiMAX BWA networks.

Keywords— scheduling, hybrid, weighted fair queuing, priority queuing,

optimization, fairness index, QoS Parameters







47

2nd


th -26


NCCS16019

MODELLING EQUIVALENT CIRCUIT FOR SUPERCAPACITOR

MODULE VOLTAGE DECAY

Aditya S Sengupta1, Anandita Goswami2, Ajoy K Chakraborty3, Bidyut K bhattacharyya4

1,3Dept. of Electrical Engineering NIT Agartala, Agartala, India 2,4Dept. of Electronics and Communication Engineering NIT Agartala, Agartala,

India

[email protected], [email protected], [email protected], [email protected]

Abstract— Supercapacitor is an invention of material science that has a wide variety of industrial applications. Many applications usually powered by batteries are taken over by supercapacitors. This paper is constituted of two parts. In the first part a supercapacitor module is used as the prime power source for a buck converter circuit. This buck converter circuit yields a constant output voltage irrespective of decaying input across the supercapacitor module or increase in the output current draw due to fault. This supercapacitor powered buck converter circuit maintains a constant output due to a closed loop feed-forward PWM control loop which is designed to change the duty ratio proportionately with changes in input voltage. This buck converter is designed for an output of 4.3 to 5 volts and 1A. The voltage of the supercapacitor module decays at a certain rate depending on the output current draw. In the next part a circuit is designed to decay the voltage of power supply almost exactly in the same manner and at the same rate at which the voltage across the supercapacitor module decays. This equivalent circuit for supercapacitor module voltage decay should yield the same output when used as the power source for the buck converter in place of the supercapacitor module leading to the inference that, if the power consumption of a circuit is known for which a supercapacitor module is the power source, the time for which the circuit would run without failing and the rate at which the voltage of supercapacitor module will decay can be estimated without using the supercapacitor itself.

Keywords—buck, supercapacitor, PWM, control loop.






48

2nd


th -26


NCCS16020

AN INNOVATIVE DESIGN APPROACH OF SOC BASED SMART CMOS

SENSOR FOR MIXED SIGNAL PROCESSING BASED APPLICATIONS

Rajinder Tiwari1, Ankita Tiwari2

1,2Department of Electrical & Electronics Engineering, ASET, Amity University,

Lucknow.

[email protected] [email protected]

Abstract— The CMOS based sensor design technology has evolved with tremendous applications in MSP domain with enhanced characteristic of maximized S/N ratio. This feature has been obtained with the utilization of pixel-based amplification in addition to minimizing the presence of the noise at the output of the device. It means that the noise present in the various active device of the system has been suppressed with the help of SoC based design technique i.e. three level pixel implementation. This system basically supports all the SoC components such as feedback amplifier, buffers, tapered reset device, etc. The CMOS based smart system has both software as well as hardware modules which in turn behave as a complete system on chip (SoC) and has got tremendous use in mixed signal based applications. The main application fo this system is in the computational analysis of the various images captured from the real world. The author present a novel approach of implementing a smart system based on SoC design approach with required performance in the domain of mixed signal processing. The simulation of the system has been carried out on LabVIEW with optimum results desired. Some the result has been carried with mathematical modeling based approach using MatLAB software. The minimum S/N ratio of the system is 55 dB with 1920 X 1080 frame readout at 550 Hz. Keywords— CMOS sensor, HDTV, FPA, CCD, APS, SoC, LabVIEW, MatLAB, PID algorithm, MSP, CCD.




49

2nd


th -26


NCCS16029

INVESTIGATION OF MTCMOS 6T SRAM CELL FOR ULTRA LOW

POWER APPLICATION

Priyanka Parihar1, Neha Gupta2, Vaibhav Neema3*, Praveen Singh4

1,2,3,4 Electronics & Telecommunication Engineering Department IET- Devi Ahilya University, Indore- 452017, INDIA

[email protected], [email protected],


Abstract- — In this paper, application of MTCMOS technique is investigated on

static random access memory (SRAM) cell. Cell or/and pass transistors with

high threshold and various aspect ratio (β) of transistor are presented. This

work is focused on stability, power consumption, delay and write trip point of

SRAM cell which are very important parameters to design any memory circuit.

The read, write and hold data stability are enhanced by up to 2.13x, 1.06x and

1.25x respectively with new MTCMOS SRAM cells as compared to conventional

6T memory cell. The read and write power consumption is suppressed by up to

1.08x and 2.83x respectively and the read delay is suppressed by up to1.96x and

write trip point is enhanced by up to 1.03x with new MTCMOS SRAM cells as

compared to conventional 6T SRAM circuit in 70 nm with multi-threshold voltage

CMOS technology.

Keywords— SRAM, Static noise margin, write trip point, MTCMOS






50

2nd


th -26


NCCS16030

NOVEL APPROACH FOR SLEEP TRANSISTOR SIZING TO SUPPRES

POWER AND GROUND BOUNCING NOISE IN MTCMOS CLUSTERING

TECHNIQUE

Neha Gupta1, Priyanka Parihar2, Vaibhav Neema3*, Praveen Singh4

1,2,3,4 Electronics & Telecommunication Engineering Department IET- Devi Ahilya

University, Indore- 452017, INDIA

[email protected] , [email protected], [email protected], [email protected]

Abstract— As the critical dimensions of MOSFETS are continuously shrinking, to achieve the high speed at present technology supply voltage is a challenging task for VLSI designers. At low supply voltage maintain the high speed of integrated circuit and low power dissipation are the major challenges for circuit designers. MTCMOS is the most useful technique for leakage power reduction in VLSI circuits. MTCMOS has some limitations in terms of delay and area due to extra SLEEP transistors. Area penalty at MTCMOS can be overcome by using a clustering technique where a single SLEEP transistor is used for a number of integrated circuit cells. By proper sizing of sleep transistor in the cluster, will overcome delay and area penalty in MTCMOS circuits with low leakage current. In this paper, we propose an algorithm for selecting proper sizing of sleep transistor for cell cluster under defined / marginal delay penalty. The proposed algorithm is tested on basic inverter cells circuit and from simulation results we get by properly sized SLEEP transistor achieve the high speed of operation and it is improved 2X times compare to conventional MTCMOS circuit. Here, we have also considered ground bouncing and power bouncing noise and reduction in both are observed in simulation result.

Keywords— Sleep Transistor Sizing, Clustering, MTCMOS






51

2nd


th -26


NCCS16031

INVESTIGATIONS ON LOGIC PERFORMANCE OF P-GE/N-SI HYBRID

CMOSFETS FOR DIGITAL APPLICATIONS

Suchismita Tewari1, Suchismita De1, Abhijit Biswas1 and Abhijit Mallik2

1Institute of Radio Physics and Electronics University of Calcutta 92 Acharya Prafulla Chandra Road Kolkata-700009, India

2Department of Electronic Science University of Calcutta 92 Acharya Prafulla Chandra Road

Kolkata-700009, India

[email protected]

Abstract— We study the logic performance of hybrid (H) CMOS devices

comprising Ge p-MOSFETs and Si n-MOSFETs in terms of noise margins (NM),

rise time (tr), fall time (tf) and propagation delay (td)using numerical device

simulation. Our analysis is conducted for channel thickness (tch) of 5 and 10 nm

at channel length (Lg) of 30 nm. Our investigation reveals that hybrid CMOS

devices show an improvement of 568% and 136% in rise time and propagation

delay, respectively as compared with corresponding Si value for Wp/Wn = 3 and

channel thickness of 5 nm. Additionally the frequency of oscillations (fosc) of a 3-

stage ring oscillator with hybrid CMOSFETs shows a significant improvement of

156% for Wp/Wn = 1, 136% for Wp/Wn = 3 compared with its equivalent Si

counterpart for tch = 5 nm. Similar trends are observed for hybrid CMOS devices

with tch = 10 nm.

Keywords— Hybrid p-Ge/n-Si CMOS, logic performance, noise margin,

propagation delay, rise time.



52

2nd


th -26


NCCS16032

AN EFFICIENT BLIND DETECTION WATERMARKING

ALGORITHM USING RANGE CONVERSION METHOD

S.MUTHUMANICKAM 1, C.ARUN 2

1,2 Department of ECE, RMK College of Engineering and Technology, TN-601206,

India


Abstract— In today digital technology, data transmission has been increased rapidly over the recent years. Most of the digital content or data exchange happens through the internet. Provision of authentication or copyright protection is the most challenging problem. Digital watermarking technology is a promising solution to provide authentication and copyrights. We propose an efficient blind watermarking algorithm using DWT (Discrete wavelet transform)-SVD (Singular value Decomposition) with range conversion method. In general, DWT is time-frequency based domain it is used to transform image coefficients into different sub bands such as LL, LH, LL and HL. We obtain host image of LH-HL sub band of DWT and embed the watermark gray scale image into HL bands using singular values obtained from SVD. Embedding information is spread across the original image and increased robustness of watermarking. As experimental results show, we achieved PSNR of about 45dB after extracted the watermark image and correlation factor is close to 0.9 for different attacks. The proposed method is useful for secure copyright protection and data authentication. Keywords— Authentication, copyright, digital watermarking technology, DWT-SVD, PSNR

mailto:%[email protected]



53

2nd


th -26


NCCS16033

EFFICIENT DESIGN AND SIMULATION OF NOVEL EXCLUSIVE-OR

GATE BASED ON NANO-ELECTRONICS USING QUANTUM DOT

CELLULAR AUTOMATA

Mukesh Patidar1, Namit Gupta2

1,2Department of Electronics Engineering

Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore (Madhya Pradesh), India


Abstract— Quantum-dot cellular automata are a new transistor less computation paradigm in nanotechnology, which encode digital binary information via configuration of charges among quantum dots. The nanostructures “Quantum dots” is a promising emerging nanotechnology for implementing digital system at the Nano scale in nanometer (nm), based on cells of coupled quantum dots. It is a highly intensifying nanotechnology that has very fast switching speed and extremely low power consumption than transistor technology. In this paper, we have implemented the novel Exclusive-OR gate using quantum-dot cellular automata technology; with designs have significant improvement in terms of layout cell area, latency and power consumption in comparison to previous designs. The proposed QCA based novel XOR layout uses only 19 QCA cells (quantum dots cells) with an area of 0.03 μm2, latency of

0.25 clock cycles and it is simple structure and powerful in terms of implementing any digital circuit’s system. These layouts are designed and simulated using bistable engine setup in QCA Designer Var. 2.0.3 tool, by taking unique features and many advantage of the nanotechnology; we are able to create complete circuits on a single layer of QCA.

Keywords— Crossovers, Exclusive-OR, Inverter, Majority voter, Nanotechnology, Polarization, Quantum Dots, QCA clocking, QCA cell.




54

2nd


th -26


NCCS16036

DESIGN STRATEGY TO SMART TOLL AND BILLING SYSTEM

Varun Bohra1, Soumendra Kumar Dash2, Kripa Singh Munda3, Deepak Prasad4

and Vijay Nath5

1, 2, 3, 4, 5 Department of Electronics and Communication Engineering

Birla Institute of Technology, Mesra

Ranchi, India


Abstract— This paper expresses an overview of the design strategy of smart toll

and billing collection system. Now-a-days, due to an improved transportation

infrastructure a huge rush can be seen at the toll plazas in order to pay the toll

taxes. Hence, an effective model for automation in toll tax payment is being

designed so that the traffic at these toll plazas can be reduced. The so-called

model uses a combination of an image capturing device with high resolution

and a processor which would not only reduce the monetary loss due to faults in

manual operation but also save the time of the riders. The objective of the

project is to design a layout which automatically identifies approaching

vehicles, records the data related to the vehicles and generates an

appropriate toll bill which can be paid either in cash or using e-wallets, plastic

money or by providing a system for automatic deduction of the amount from a

predefined user account. This vision when implemented would help to reduce

traffic congestion at toll plazas and decrease the fuel consumption of vehicles

waiting in the queue.

Keywords— Automatic toll collection system, license plate recognition

Introduction




55

2nd


th -26


NCCS16037

NOVEL CELL SEARCH METHOD IN LONG TERM EVOLUTION

SYSTEM

Sanket P. Singhania1, Smita A. Lonkar2, K T V Reddy3

1,2SSJCOE Thane, India

3Governing Council IETE HQ, New Delhi


Abstract— In Long Term Evolution Systems(LTE) user equipment (UE)

undergoes cell search procedure to synchronize with a cell. Through this

procedure UE recognizes time and frequency parameters of a cell through its

cell ID. Hence it is important that procedure is robust and quick. To facilitate the

cell search two synchronization signals termed as Primary Synchronization

signal (PSS) and Secondary Synchronization Signal (SSS) have been used. This

paper focuses on the aspect of generation and detection of these two signals.

This paper simulates the schemes for PSS and SSS generation &

detection of cell identity and subframe index using Cross Correlation.

Keywords— LTE, cell search, PSS, SSS





56

2nd


th -26


NCCS16038

VARIOUS FEATURE EXTRACTION AND CLASSIFICATION

TECHNIQUES

Dalvir Kaur1, Sukesha Sharma2

1,2UIET, Panjab University Chandigarh, India


Abstract— This work concentrates on techniques for feature extraction and

selection. Feature extraction plays an important role in image processing. The

discrete cosine transform (DCT), discrete Fourier transform (DFT) and wavelet

transform (WT) are used for feature extraction. For optimal feature selection

PCA and ICA statistical techniques are used. Then, classification technique

support vector machine (SVM) is discussed. PCA and ICA performance is

compared in SVM. Classification is proposed for detecting defects.

Keywords— Feature Extraction; DCT; DFT; DWT; Feature Selection; PCA; ICA;

Classification; SVM




57

2nd


th -26


NCCS16039

PATH TRACKING METHOD OF ALV MODEL BASED ON ADRC STRATEGY AND DIFFERENTIAL FLATNESS THEORY

Abhinav Kumar1, Mrs. Sushma Kamlu2

1,2Dept. of EEE, Birla Institute of Technology, Mesra, Ranchi, India


Abstract— This paper is about implementing a newest approach to track the path of Autonomous Land vehicle based on differential flatness theory combined with ADRC strategy method, a new approach for tracking the path. This approach is very helpful in the under actuated, non-linear and with large uncertainties problem which is hard to control. By making a small angle approximation a linear model is found. An alternative form of the model is based on the flat output and its derivatives only. The effectiveness of the proposed method has been justified by the simulations and comparing the results with standard tracking methodology Keywords— Active disturbance rejection control (ADRC), differential flatness, lateral path tracking, under actuated.




58

2nd


th -26


NCCS16040

PERFORMANCE ANALYSIS OF CONVENTIONAL SRAM WITH

HIGHER ORDER SRAM TOPOLOGIES

Ravneet Kaur1, Garima Joshi2, Maninder Kaur Saggu3, Vishal Sharma4

Department of Electronics, U.I.E.T, Panjab University Chandigarh, India

[email protected], [email protected], [email protected],

[email protected]

Abstract— The growth in digital consumer electronics has evoked a tremendous rise in performance of portable devices. To meet these demands, there is a need of primary memory and thus Static Random Access Memory (SRAM) serves this purpose. Technical innovations have provided the improved memory density and speed. Innovations in memory technology are reflected in terms of high density, high speed and low power memory cells. Therefore, low power, high speed and high stability are the major concerns in designing SRAM cells. Scaling down the voltage meets the low power requirements of the cell but at the same time delay increases and the stability degrades. Thus, there is always a trade-off between the performance parameters. On the basis of particular application, various methods like sizing of device, scaling of voltage and architectural techniques are used to improve the overall performance of memory cells. This paper compares different architectural designs of SRAM topologies, such as 6T, 7T, 8T, and 9T, on the basis of stability (write SNM, read SNM and hold SNM), power consumption and delay. For example, feedback loop cutting architectural technique in 7T SRAM cell increases the write stability as compared to 6T SRAM cell but at the same time area increases. An attempt has been made to identify topologies with optimized overall performance.

Keywords— SRAM, Transmission Gate, read static noise margin (RSNM), write static noise margin(WM),hold static noise margin(HSNM) memristor, power dissipation, delay, charge sharing, feedback loop cutting, sleep transistor and transmission gate.






59

2nd


th -26


NCCS16041

PERFORMANCE ANALYSIS OF TIME-REVERSAL DIVISION

MULTIPLE ACCESS UNDER MULTI-PATH RICIAN FADING

CHANNELS

Shashank Shekhar1, Shanidul Hoque2, Ashraf Hossain3, and Wasim Arif4

Department of Electronics and Communication Engineering National Institute of Technology Silchar, Silchar, India

[email protected], [email protected], [email protected],

[email protected]

Abstract—The unprecedented growth of wireless communication resulted in large number of personal digital devices, which created rapid increment in traffic due to their demand for data and content access. Present sub-6 GHz spectrum with various techniques is unable to fulfill future requirement so it is inevitable to go for millimeter wave spectrum which offer a large bandwidth. Time-reversal technique promises for low complexity wideband system with high throughput. In this paper, we analyze performance of multiple-input-single-output Time-reversal division multiple access scheme under multipath Rician fading environment considering the effect of specular power. We present the comparison of system performance under different specular power.

Keywords—Rician fading; Rice factor; Time-Reversal; specular power; TRDMA; MISO






60

2nd


th -26


NCCS16042

ANALYSIS OF SOFTWARE DEVELOPMENT LIFE CYCLE MODELS

Amninder Singh, Puneet Jai Kaur

UIET, Panjab University Chandigarh, India


Abstract— Software development life cycle is key technology to create a sound product on basis of Cost, Accuracy and Quality. There are several types of models given to us with different scenarios. It is important to choose best methodology according to our objective. There are two types of methodologies traditional and agile. Each and every model aims to minimize anomalies that came in previous one. There are two framework linear and iterative used in different models. The model like waterfall and v use linear type of strategy that's why they are less flexible on the other hand remaining models use iterative framework which provide flexibility to use at each and every stage. In this paper, various characteristics of different models are discussed and comparison is being made on basis of aspects.

Keywords— SDLC models; Charact erstics; comparison table;




61

2nd


th -26


NCCS16043

DESIGN OF NARROWBAND 2.69GHZ CMOS LOW NOISE AMPLIFIER

FOR WIMAX APPLICATION

Sumit Singh1, Abhishek Pandey2, Vijay Nath3

1,2,3VLSI Design Group, Department of Electronics and Communication Engineering Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India,

Pin-835215


Abstract— In this paper, a radio frequency (RF) 2.69 GHz CMOS low noise

amplifier (LNA) for WiMAX applications is presented. WiMAX gives a modern

approach to wireless communication with better throughput and larger area

coverage. Earlier 2.69GHz frequency was allotted to satellite communication

and military communication in India. Later to maximise the use of this frequency

band, telecom regulatory authority of India sets this band to WiMAX application

aimed to use in smart cities for high speed internet connectivity. The output

results show that the proposed LNA has the forward gain of 27.7dB, IIP3 of

−1.81dBm, noise figure of 1.44dB and the 1dB compression of −10.88dBm and

IIP3 is -1.81dBm at 2.69GHz frequency. The power consumption of the proposed

amplifier is 18.06mW at 1.5V power supply. The design and simulation of

proposed LNA is carried out in Cadence Virtuoso gpdk 45nm CMOS technology.

Keywords— Worldwide Interoperability for Microwave Access(WiMAX), Noise

Figure(NF), Rollet’s factor(k),Common source(CS), Common Gate (CG), Source

degenerated LNA.




62

2nd


th -26


NCCS16044

SENSITIVITY ANALYSIS OF VARIOUS MAGNETO-OPTIC MATERIALS

BASED ON FARADAY ROTATION PRINCIPLE

Sarita Kumari and Sarbani Chakraborty

Department of EEE, Birla Institute of Technology, Mesra, Ranchi, Jharkhand 835215

[email protected]

Abstract— This paper discusses the properties of magneto-optic materials and

its sensitivity with wavelength in a basic current / magnetic field sensor set up

for different relative orientation between analyzer and polarizer angle. TDG,

TGG, doped TGG, YIG and dense flint glass materials were used for

characteristics analysis. Faraday rotation is inversely proportional to

wavelength.TGG shows larger rotation, high stability to temperature change as

well as high optical quality. Pr3+ doped TGG has been observed to exhibit the

maximum sensitivity with change in analyzer angle at 532 nm as well as 1064

nm. At 632.8 nm Ce3+doped TAG ceramic shows maximum sensitivity. The MO

sensors are used for various process parameters measurement such as

current, displacement, magnetic field etc.

Keywords— Magneto-Optics, Faraday rotation, TDG, TGG, YIG, Sensitivity.



63

2nd


th -26


NCCS16045

A SECURE THREE - WAY HANDSHAKE AUTHENTICATION PROCESS

IN IEEE 802.11i

Anil kumar, Partha Paul

Department of Computer Science and Engineering Birla Institute of Technology, Mesra Ranchi, India


Abstract— The significance of wireless devices has been growing day by day.

Performance and Security is an essential issue, leading to more trustworthy and

effective communications. IEEE 802.11i is the most updated security protocol

for wireless LAN. Authentication and Key management is major portion of a

secure wireless communication. An IEEE 802.11i usage the IEEE 802.1X

standard for authentication; and for key management and distribution, Four -

Way Handshake protocol is used. Research has presented that there are

various security concerns associated with the authentic IEEE 802.11i

authentication protocol. The most severe of these security concerns is the key

recapture attack, during which attackers are able to recover the secret key and

use it to get access to a targeted network. In order to alleviate this severe

security susceptibility, the aim of this paper is to investigate those

vulnerabilities and enhance the IEEE 802.11i standard by presenting a

substitute enhanced Three - Way Handshake authentication protocol which can

efficiently forestall the key recapture attack. In addition, this technique reduces

the memory overheads and computation.

Keywords—IEEE 802.11i; WEP; TKIP; WPA; IEEE 802.1X; PMK.




64

2nd


th -26


NCCS16046

BROWSERGUARD2: A SOLUTION FOR DRIVE-BY-DOWNLOAD

ATTACKS

Gireesh Joshi1, R. Padmavathy2, Anil Pinapati3, Mani Bhushan Kumar4

Department of Computer Science & Engineering National Institute of Technology

Warangal-506004, Telangana, India

[email protected], [email protected], [email protected], [email protected]

Abstract— Drive-by-download attacks have become one of the major threats on web infrastructure. These attacks are triggered when a user visits a malicious website which downloads and executes malware in user’s system by exploiting the vulnerabilities in web-browsers or plug-ins. After using these attacks, an attacker can sometime gain complete access on the system. In this paper we design and implement a solution for drive-by-download attacks called BrowserGuard2. It is a run-time, behaviour based solution therefore it doesn’t need to analyze source code of a webpage or run-time states of a script code. It also doesn’t take into account the reputation value of a website and doesn’t need to maintain exploit code sample. BrowserGuard2 analyzes download scenario of a file to be downloaded and based on the conclusions it draws, it successfully blocks the execution of a malware. Experimental results show that BrowserGuard2 has no false positives and false negatives for the web pages used in the experiments. It was also observed that BrowseGuard2 has very less overhead.

Keywords— drive-by-download attack, heap spray, malware, Web browser, intrusion detection, system security.






65

2nd


th -26


NCCS16047

GA BASED ENERGY OPTIMIZATION IN TRAFFIC GROOMING WDM

OPTICAL MESH NETWORK

Nishat Aafreen1, Partha Paul2

1,2 Department of Computer Science and Engineering,Birla Institute of

Technology, Mesra, Ranchi 835215, India


Abstract— With the beginning of new millennium, the multicast application such

as HDTV, interactive learning, video conferencing, distributed games, movie

broadcasting etc. are boosting and requires point-to-multipoint (PtMP)

connections from a source node to the destination node in a network. These

requirements show an excessive increase in the growth of network traffic, and

hence increases the energy consumption cost of the network equipments in

telecom industries. In this paper, our objective is to optimize the energy

consumption cost in a static WDM optical mesh network using genetic algorithm.

There are differences in bandwidth offered by a wavelength and necessity of

bandwidth for the multicast connection in an optical network which can be

solved by grooming low bandwidth connection request into a high bandwidth

channel. In a WDM optical mesh network, the higher layer electronic ports such

as transmitter and receiver are the most important energy consumption

devices. So for multicast traffic grooming (MTG) in high bandwidth light-trees,

we have to reduce these devices to optimize the energy consumption. Our

proposed algorithm will compare with the existing multicast traffic grooming

(MTG) algorithm as well as saturated light tree path multicast traffic grooming

(SLTMTG) algorithm and measure the cost of the network and wavelength

utilization.

Keywords— Multicast Traffic Grooming (MTG), Wavelength Division Multiplexing

(WDM), Light-tree




66

2nd


th -26


NCCS16048

PIEZOELECTRIC ENERGY HARVESTING: A DEVELOPING SCOPE

FOR LOW POWER APPLICATIONS

Oshin Garg, Sukesha Sharma, Preeti, Pardeep Kaur

UIET, Panjab University Chandigarh, India

[email protected]

Abstract— The area of energy harvesting using vibration sources has attracted numerous researchers over the past few years. It has a great potential to have extended lifetime of low power devices such as wireless sensors, portable devices, wearable devices. The wireless devices in today’s date require batteries which have a limited lifetime and needs to be replaced with time. In case of wireless sensors that work in harsh environment, it is nearly impossible to replace batteries. The concept of energy harvesting aims to develop devices that do not require replaceable batteries. This is done by converting available energy from environment into electrical energy to power wireless devices. This paper is focused on piezoelectric energy harvesting. Firstly, different approaches to harvest energy have been discussed in brief. After that piezoelectric energy harvesting has been discussed in detail. Different components of piezoelectric energy harvesting circuit namely transducers, rectifiers and storage devices have been discussed. Keywords— Energy Harvesting, Piezoelectricity, Rectifier circuit, Storage devices.



67

2nd


th -26


NCCS16049

AN OVERVIEW OF TEMPERATURE SENSORS

Deepak Prasad1 & Vijay Nath2

1,2Dept of Electronics and Communication Engineering

Birla Institute of Technology, Mesra, Ranchi

[email protected]

Abstract— Temperature has been one of the key parameter used in almost

every field. The evolution of temperature sensor is highly appreciated by

industrial process control, automotive industry, aerospace, well logging and

power generation etc. On other word, it can be said that measuring high

temperature is now one of the key enabling technologies of the current century.

Development in temperature sensor technologies not only allows increases in

accuracy, control, efficiency and reliability in safety-critical systems operating

in harsh environments in many applications but also decrease the causality ratio

in human machine interface. The change in trend occurs with the evolution of

CMOS which puts storm in the field of electronics where a large circuit can be

supposed to work at very low power supply. The present paper reviews the

various technologies available to measure temperature.

Keywords— component; formatting; style; styling; insert (key words).



68

2nd


th -26


NCCS16050

A 3.65MW, OP-AMP BASED UP-CONVERSION MIXER FOR ZIGBEE FRONT-END TRANSMITTER

Abhishek Pandey, Vijay Nath (Member IEEE)

VLSI Design Group, Department of ECE, B.I.T. Mesra, Ranchi-835215(JH), India

[email protected], [email protected].

Abstract— This paper illustrates up-conversion mixer with very high linearity

and improved conversion gain. CMOS Operational amplifier is used to enhance

the overall conversion gain of the proposed mixer circuit. Derivative

Superposition technique is applied to improve the linearity of the proposed Up-

conversion mixer circuit. The operating frequency of this circuit is 2.4 GHz and it

is applicable for the Zigbee transmitter front-end. In this proposed Up-

conversion mixer, passive balun circuit is used to convert unbalanced base-

band signal to differential balanced signal. The proposed up-conversion mixer

coverts input base band signal of 100 MHz to radio frequency output signal of

2.4GHz. The local oscillator frequency is 2.3 GHz and a local oscillator power is

considered at 2 dBm. The conversion gain of this mixer is 18.86 dB, IIP3 and

OIP3 are 15.9708 dBm and 16.4053 dBm respectively. The circuit is simulated

on cadence analog and digital design tool at 45nm CMOS technology and rail to

rail power supply is ±1.2 V.

Keywords— Base-Band Signal, Local Oscillator (LOSC), Inter mediate frequency

(IF), Radio-frequency (RF), Input Intercept Point (IIP), Output Intercept Point

(OIP), Conversion Gain (CG), Complementary Metal Oxide Semiconductor

(CMOS).




69

2nd


th -26


NCCS16051

ADAPTIVE COMPENSATION ALGORITHM FOR FLUX ESTIMATION

OF PM BLDC MOTOR DRIVES

Vijay Kumar Karan (Member IETE) , P.R. Thakura (Fellow IETE), A.N. Thakur

1,2Department of Electrical & Electronics Engineering, Birla Institute of Technology,Mesra, Ranchi-835215

3Department of Electrical Engineering, National Institute of Technology,Jamshedpur-834014


Abstract— Hybrid Electric Vehicle for low cost, low emission, uses a Permanent

Magnet Brushless DC Motor having trapezoidal back-emf. In low cost, low

power application, high cost rotary shaft encoder is prohibitive. Therefore there

is a need of estimation of speed through accurate flux estimation. Application of

pure integrator for flux estimation is difficult because of its dc drift and initial

value problem [4]. Flux is estimated in PM BLDC motor by integration of emf

derived out of voltages and currents of motor in a stationary reference frame.

The integration of emf requires the initial values of stator flux. In absence of

initial values the integration adds a dc flux linkage component to the stator flux

and therefore produces a drifted stator flux linkage vector. Due to this

inaccuracy the estimation of flux linkage angle speed and torque in a sensorless

drive also becomes inaccurate. In this paper it is shown that the error due to

normal integration can be easily eliminated using a New Integration Algorithm

suggested for AC systems [4]. The method has been used on PM BLDC motor to

eliminate the dc drift in stator flux and achieving correction in estimation of

stator flux angle.

Keywords— Hybrid Electric Vehicle, Emf, Integration, Stator Flux Linkage, PM

BLDC motor, Sensorless Drive, Stationary Reference Frame, Adaptive

Compensation.





70

2nd


th -26


NCCS16052

2nd International Conference on Nano-electronics, Circuits ...

Documents

Transcript of 2nd International Conference on Nano-electronics, Circuits ...