7/30/2019 [2]A Simple and accurate Modeling of Non-Rectilinear Gate Shape with Trapezoidal Approximation.pdf

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M. H. Ryu and Y. M. Kim *

School of Electrical and Computer Engineering, UNISTUlsan, 689-798, Republic of Korea

AbstractA simple and accurate modeling technique which analyzes NRG

(Non-Rectilinear Gate) transistor with a simplified trapezoidal

approximation method is proposed in this paper. To approximate a

non-rectangular channel shape into a trapezoidal shape, we extract

three geometry-dependent parameters from post-lithographic

patterns; Lmin (minimum channel length from the slices), Lmax

(maximum channel length from the slices), and W eff (effective

channel width). First, we slice the NRG transistor gate along the

width of the device, then sort these slices according to size, and the

trapezoidal approximation will follow. By using those 3 new

parameters from the NRG shape in post-lithographic simulation,

simple modeling of trapezoidal approximation becomes possible.

The physics-based TCAD simulation is used to verify our model in

a typical 45-nm process. The developed model requires a lot less

computations and run time compared to the previous approaches.

Therefore, a full chip post-lithography analysis (PLA) becomes

feasible.

1. IntroductionIn the sub-wavelength regime, discrepancy of device

performance by NRG effect has been getting worse with rapid

CMOS technology scaling. As a result of the shape of

non-rectilinear gate which is significantly distorted from the

designed rectangular layout, a substantial discrepancy is observed

between the result of the post-lithography simulation and the result

of the circuit simulation with significant impacts on timing and

power [1]. So far, several post-lithographic simulation (PLS)

techniques which can handle NRG transistors have been proposed[2, 3]. Most of the approaches are based on the modeling of

summation of I on and I off in each slice after uniformly partitioning a

given device channel into small slices. However, modeling in these

approaches is too cumbersome and requires many amounts of

resources as well. In this paper, we propose a technique for simple

and accurate modeling which analyzes NRG transistor with a

simplified trapezoidal approximation method.

2. Trapezoidal approximation modelOnce the coordinates of any LER shape are given, we can

extract the Lmin and Lmax based on the simple algorithms of inner,outer, average length as below. In this paper, the average approach

is used because it gives the lowest discrepancy among the three possible cases. The flow of trapezoidal approximation is shown inFig. 1. (a). Based on our model, the three geometry-dependent

parameters from post-lithographic patterns are extracted in threedifferent cases; inner, outer, and average approximation. The SEM(scanning electron microscope) image of the practical channelregion of the MOS transistor which is distorted from the designed

rectangular shape and one of the slices after slicing the channelregion are shown in Fig. 1. (b) and (c), respectively.

min 2 3 1 4

max 2 3 1 4

1min min min min

1max min min min

min( , ) max( , ) , 1 ; n = # of slices

max( , ) min( , ) . 1. ( )

min( , , , , ):

max( , , , , )

i i i i i

i i i i i in

i n

i n

L x x x x where i n

L x x x x x in Fig c

L L L Linner approximat

L L L L

1min max max max

1max max max max

1 1min max min max min max

min

1 1min max min max min

max

min( , , , , ):

max( , , , , )

min( , , , , )2 2 2

max( , , , ,2 2

i n

i n

i i n n

i i

ion

L L L Louter approximation

L L L L

L L L L L L L

L L L L L L

max

:

)2

n naverage

L

The extracted Lmin and Lmax from the above equations can be

used to approximate an arbitrary NRG shape into a trapezoidalshape. In Fig. 2., (a) and (b) show two representative examples (thecase of HDL > 0, HDL < 0, respectively, where HDL is half deltachannel length; variation of the gate shape at one side), (c) is anarray of slices according to their lengths and (d) is approximatedtrapezoidal shape. By using only two parameters Lmin and Lmax ,

there are still significant errors between original shape andtrapezoidal approximated shape because the channel lengths at thedevice edges have higher impact than channel lengths at the center of device. In this paper, in order to consider edge effect [4] for different channel length at the edge of devices, weighting factor (effective width; W eff ) is introduced. To identify and thus reduceapproximation errors in the trapezoidal method, we extract W eff from the curve-fitting of TCAD simulation results for various NRGshapes. We extract Lmin and Lmax in simple NRG channel that hashexagonal shape.

3. TCAD setup & model verification I D vs. V DS data based on published 45-nm SPICE model [5] was

used to setup parameters for TCAD simulation, Silvaco Atlas [6].

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The parameters used for 3D TCAD simulation are shown in Table

I. The unequal distribution of drive current ( I on) across the width of

the channel is due to different V th in the region of edge and the

region of center, hence I on depends on the location of the channel

length variation [7]. We used the location-dependent weightingfactor to apply different W eff for minimizing the approximation

error due to the edge effect . Fig. 3 represents I on error distribution

between the original NRG transistors and the proposed model, it is

clearly shown from the result that the error reduces significantly

with W eff along with trapezoidal of Lmax and Lmin . For 40 sample

transistors, the error ranges from -9.11% to 2.92% without W eff and

then is reduced from -1.33% to 1.24% with W eff .

4. ConclusionWe demonstrate that I on characteristics of arbitrary NRG

transistors can be modeled by trapezoidal approximation in simple

and fast method using three parameters, Lmin , Lmax , and W eff instead

of taking summation of all slices into account. In order to capture

the effect of edge effect which causes the unequal distribution of

drive current across the width of the channel, we used the

location-dependent weighting factor ( W eff ). The results of TCAD

simulation show that proposed modeling is suitable for device

simulation with edge effect since its error about I on is around 1%

for various NRG transistors.

References[1] R. Singha, et al, 2007. DAC '07. 44th ACM/IEEE, (2007), pp.

823-828.

[2] A.P. Balasinski, et al, Proc. SPIE Conf. on Design, (2002) Vol.

4692.

[4] P. Gupta, et al, Proc. SPIE Conf. (2006) Vol. 6156.

[5] http://www.eda.ncsu.edu/wiki/FreePDK45:Contents

[6] http://www.slivaco.com

[7] P. Gupta, et al, ASPDAC, (2008), pp. 480-485.

Fig. 2. Approximated equivalent trapezoidal channel.(a) HDL > 0, (b) HDL < 0, (c) after sorting according to

size, (d) trapezoidal shape

Fig. 1. Procedure to approximate a NRG transistorinto trapezoidal shape : (a) approximation flow, (b)SEM (scanning electron microscope) image of gateLER and slicing, (c) i th slice with four coordinates.

Fig. 3. I on error distribution

Parameters ValueLength (nominal) 45nmWidth (nominal) 0.2um

V dd 1.0VT ox 1.5nm

Channel doping 3.92e+18cm -3

NSUB 1e+15 cm -3 Junction depth 20nm

S/D Region to Gate Poly 0.04umSTI width 0.1umSTI depth 0.3um

Table I. 45-nm TCAD model parameters