28nm Fully-Depleted SOl Technology: Cryogenic Control ... · 7mV/ckc). FDSOI coo provick a valuable...
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28nm Fully-Depleted SOl Technology: Cryogenic Control Electronics for Quantum Computing H. Bohuslavskyj') , s. Barraud', M. Casse', v. Barra)', B. BeI1rand', L. Hutin', F. Arnaud', P. Galy', M. Sanquer, S. De Franceschi', and M. Vinet' ' CEA, LETI, Minatec Campus, F-38054 Grenoble, France ' CEA, INAC-PHEUQS, F-38054 Grenoble, France , STMicroelectronics, 850 rue 1. Monnet, 38920 Crolles, France. E-mail: [email protected] Abstract This paper reports the first cryogenic characterizatioo of 28nm FuJly- Depicted-SOl CMOS technology. A comprehensive study of digitallaoalog performaoces sod body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent Vnt controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/ ckc) . FDSOI coo provick a valuable approoch to cryogenic low- power electronics. Applications such as classical control hardware for quantum processors arc envisioned. Introduction Since the early 2010·s. increaaing attcntioobas been paid to Si-based spin qubits for quaotum computiog 11..3). Besides allowing for loog spin cubaeocc:. largely eobanced by the uae of isotDpica1ly eoriched nuclear spin-free " Si layers 13), Si qubil!l benefit from wcll-c:stablisbed miaoc1cc:tto11ics fabrication techniques. This coostitutcs a clear asset in the prospect of large-scale qubit integratioo 14) . Recc:ntly. the implementatioo of Si spin qubit 00 a foundry-compallble CMOS SOl platform was demonstrated IS, 6). marking an important first step towards the realization of a Si-bascd quantum. computer. In a quantum. processor, qubil!l need to be individually addressed, i.e. initialized. manipulated, and mcasW"Cd. This large-scale parallelism seems hardly manageable without the usc of co-integrated. or at lcastprox:imal.. classical hardware. Therefore, extc:nding the operatioo of both digital ood aoalog Si electronics to temperatures as low as 4 K (and below) appears as 00 urgent task to UDdertakc: in parallel with qubit ckvelopment. At such low temperatures. however. cktrimental effi:cl!I on ckvice ope2"atioo have been obaerved due to dopant freeze-out sod cbarge trapping 17-8). Nevertheless. the actual impact of these effects in advanced CMOS technology remains oniy barely cxplored 19J . Here, for the first time, we present a study of digitallaoalog performances sod body-biasing ofFDSOl doWD to 4K. We aim at assessing the pot<nti.al ofFDSOl for low-temperature electronics. FOSO] is an attractive golution since it can simwtaneously deliver low. power clectronics and a versatile teclmology framework for qubits development 14-6) . FDSOI process r •• tu .... The FDSOI traosistors are fabricated with a gate-first high-" metal gate. They arc processed 00 300mm (100) SOl wafers with a buricd oxide thickncss [10). The 7nm-thick Si chaonel is undoped. The EOT is l.5Snm for NMOS (resp. 1.7nm for PMOS) for thin oxick (GOI) and 3.7nm for thick oxick (002) traosistors. Regular Vm traosiston are studied with PWBLL (resp. NWBLL) ood additional P-type (resp. N-typc) ground plaoe implantatioo for NMOS (resp. PMOS) ckvices. FIg.l summarizcs the main technology features and shows a Cf'OS!J.-scction of FDSOI traosistor. Device digital performances do..... to 4K The carrier mobility v. inversion charge (NlNV) is 00 important parameter to characterize the behavior of devices. NlNV is obtained by integration of gate-ebannel (Ca) capacitance sbawn in ",.2 for different temperstun: (I). The T-dependence n:sull!l in a shift in Vm but does DOt influmcc much the shape of Co. The electron and hole I'1iPF measured duwn to 4K are shown in Fig. 3. Since pbooon mobility is sufficiently weak and can be neglected at such low temperature, the carrier mobility is enhanced as temperstun: doen:ases (FigA). It can also be noted that thick gste oxide (G02) weakons remote Caulomb sod soft-optica1 phoooo scattering. It therefore leads to so improved carrier mobility 111,12) . Typical traosfer cbaracteristics of G02 traosiston are plotted in Fie.! (NMOS) and FiC.6 (PMOS). The incn:ase of IVml as the temperature is reduced is accompanied by a significant improvement of current for a given overdrive gste voltage (IVos-Vml-Q.SV). At 4K, a subthresbold swing SSllN of oniy 7mV/ckv is acbieved in tho linear regime (Fig.7). Even st bigh drain voltage (V",,-().9V), thc evolutioo of subthreshold swing versus T remains the same (sec inset of Fia.7). At the same time, the linear current IOllliN of NMOS G02 is eubanced by a factor x6.2 (FiaA). By comparison with 300K, the substantial increase of ckvices performance at low·te:mperatme is summarized in Fta;.9. The saturation current IaoSAT and V",,=O.9V) incn:ases due to bigher mobility while the subthreshold swing SSSAT remains very low. GOI transistors (NIPMOS) show a higher saturation current than G02 transistors due to a lower EOT. Back bi ••• fflciency down to 4K The use ofback biasing (BB) is a key factor in optimizing performance. and power consumption. Therefore, maintaining its efficiency at very low temperatures is aucial . In addition. back·biasing can lWovide a useful cootml tool for qubits. eoabliog fast readout circuin-y sod a lnnable coupling between neighboring quaotom dots 14,6J . Tbe Vm cootrollability offered by the back-gste a14K is ShOWD in FiI. IO. Compared to 300K, the BB factor (y-!Nmlt.VBACK) for N ood PMOS n:mains uuchaoged (FIg.ll). It means that the ckvioe behavior is not alten:d by frccze-<J\lt l'hcnomena who are likely to play an important role at low-temperature 18,9], At short gste leugth (La=28nm). the ckviee performaoces (Fig.Il) studied on NMOS GOI transistors leads to a similar conclusion. The subthreshold swing is strongly reduced with T independently of1he active layer width W (Fig.13). FIg14 shows that at 28nm gate length. the linear current (IVos-Vm!=O.5V) is significantly improved (+62% at 4K). Tbe effect oCBB measured at 4K is ickntica1 to tlte 300K ooe (F1c.lS). In case of PMOS 001. low-temperature combined with a sbart La lead to a modification of subthreshold behavior: oscillations occur at Low VDS (FIc.I6). They an: most likely induced bytbe presence of ciopaol!l diffused from SID into the chaoncl I13J . However. these ""cillatians are strongly soppr<SSed stbigh Vns(Fig.I7). Device analoR performa ... do ... to 4K Device aoalog performlUlQC is also as:IC8SOCI down to 4K throogh tbo key paramctera such as the II1lD8coDductan Gr... tbe output cooductaoce On and the intrinsic gainAvo= Gw'Gn. The figure of merit GWIns 'Vs Ins xLJW for NMOS (n:sp. PMOS) GOI is reported in F• • 18 (rcop. Flg.19). Since GMiIns is inversely proportioml to the subthreshold swing (in weak inversion) and proportional to (in strong inversion) the [GWIos liS Ins] metric at 4K is strongly improved. GWW va intrinsic voltage gain (Avo) is shOWD in Fig.20. Low-temperature and back-biasing siguificantiy improve the transconductance OM (due to increased and the intrinsic gain Avo (due to reduced On). ConclulioDI For the first time, the opcratioo of28nm FOSOI CMOS technology was successfully demonstrated down to 4K. We have shown that a reduced temperature operatiOtl largely improvea CMOS ckvice performance. Additiooally. UDder a DC operatioo, the ability to adjust Vm through back-biasing n:maina uuchanged at 4K. This unique capability could be particularly helpful in the devclopmc:nl of tltst power-cfficient pcriphcntl circuitty (multiplexing. cootrol and n:adout of qubits) and allows incn:ased fleXIbility in the design ofa sca1able dusica1-quantom imerfaoe. Atknowledgemeals: We odmowIedge finaocial support from the ElI under Project MOs-QUITO (No.688539). RefereDcn 11) R Kawakami et m., Nature NaIJotzdJ., 9, p.666, 2014. 11] J.T. Muhooen et aJ., Nature Nonotech.. 9, p.986, 2014. (3] M Vcldhortn et al. , Nature Nanotech.. 9, p.981.2014. [4] S. De FfIIlccschi et al. , EUROSOl-UUS, p.l24, 2016, [5] L. Hulin et aI., p.1-2, VLSI,2016. [6] Dc Fnmceschi eI aJ. , /EDN.. 2016. [7] G. Ghibaudo et al., Microelectronics Eng., 19, p.833, 1992. [8] E. Simoen et al., IEEE TED. 42. pllOO, 1995. [9] E. Charbon et al.,lEDM, 2016. (10] N. Planeset a/. , VLSI. p.133, 2012. [11] M Casse et al., IEEE TED, 53, p.759, 2006. Pl] V.-H Nguyen et al., IEEE TED. 61. p.3096. 2014. [13] R W"'QUCZ et a1 .• VI.SI . p.193. 2010.
Transcript of 28nm Fully-Depleted SOl Technology: Cryogenic Control ... · 7mV/ckc). FDSOI coo provick a valuable...
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28nm Fully-Depleted SOl Technology: Cryogenic Control Electronics for Quantum Computing H. Bohuslavskyj'), s. Barraud', M. Casse', v. Barra)', B. BeI1rand', L. Hutin',
F. Arnaud', P. Galy', M. Sanquer, S. De Franceschi', and M. Vinet' ' CEA, LETI, Minatec Campus, F-38054 Grenoble, France ' CEA, INAC-PHEUQS, F-38054 Grenoble, France
, STMicroelectronics, 850 rue 1. Monnet, 38920 Crolles, France. E-mail: [email protected]
Abstract This paper reports the first cryogenic characterizatioo of 28nm FuJlyDepicted-SOl CMOS technology. A comprehensive study of digitallaoalog performaoces sod body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent Vnt controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/ckc). FDSOI coo provick a valuable approoch to cryogenic lowpower electronics. Applications such as classical control hardware for quantum processors arc envisioned.
Introduction Since the early 2010·s. increaaing attcntioobas been paid to Si-based spin qubits for quaotum computiog 11..3). Besides allowing for loog spin cubaeocc:. largely eobanced by the uae of isotDpica1ly eoriched nuclear spin-free " Si layers 13), Si qubil!l benefit from wcll-c:stablisbed miaoc1cc:tto11ics fabrication techniques. This coostitutcs a clear asset in the prospect of large-scale qubit integratioo 14). Recc:ntly. the implementatioo of Si spin qubit 00 a foundry-compallble CMOS SOl platform was demonstrated IS, 6). marking an important first step towards the realization of a Si-bascd quantum. computer. In a quantum. processor, qubil!l need to be individually addressed, i.e. initialized. manipulated, and mcasW"Cd. This large-scale parallelism seems hardly manageable without the usc of co-integrated. or at lcastprox:imal.. classical hardware. Therefore, extc:nding the operatioo of both digital ood aoalog Si electronics to temperatures as low as 4 K (and below) appears as 00 urgent task to UDdertakc: in parallel with qubit ckvelopment. At such low temperatures. however. cktrimental effi:cl!I on ckvice ope2"atioo have been obaerved due to dopant freeze-out sod cbarge trapping 17-8). Nevertheless. the actual impact of these effects in advanced CMOS technology remains oniy barely cxplored 19J. Here, for the first time, we present a study of digitallaoalog performances sod body-biasing ofFDSOl doWD to 4K. We aim at assessing the pot<nti.al ofFDSOl for low-temperature electronics. FOSO] is an attractive golution since it can simwtaneously deliver low. power clectronics and a versatile teclmology framework for qubits development 14-6).
FDSOI process r •• tu .... The FDSOI traosistors are fabricated with a gate-first high-" metal gate. They arc processed 00 300mm (100) SOl wafers with a buricd oxide thickncss of2~nm [10). The 7nm-thick Si chaonel is undoped. The EOT is l.5Snm for NMOS (resp. 1.7nm for PMOS) for thin oxick (GOI) and 3.7nm for thick oxick (002) traosistors. Regular Vm traosiston are studied with PWBLL (resp. NWBLL) ood additional P-type (resp. N-typc) ground plaoe implantatioo for NMOS (resp. PMOS) ckvices. FIg.l summarizcs the main technology features and shows a Cf'OS!J.-scction of FDSOI traosistor.
Device digital performances do ..... to 4K The carrier mobility (~I!FP) v. inversion charge (NlNV) is 00 important parameter to characterize the behavior of devices. NlNV is obtained by integration of gate-ebannel (Ca) capacitance sbawn in ",.2 for different temperstun: (I). The T-dependence n:sull!l in a shift in Vm but does DOt influmcc much the shape of Co. The electron and hole I'1iPF measured duwn to 4K are shown in Fig. 3. Since pbooon mobility is sufficiently weak and can be neglected at such low temperature, the carrier mobility is enhanced as temperstun: doen:ases (FigA). It can also be noted that thick gste oxide (G02) weakons remote Caulomb sod soft-optica1 phoooo scattering. It therefore leads to so improved carrier mobility 111,12). Typical traosfer cbaracteristics of G02 traosiston are plotted in Fie.! (NMOS) and FiC.6 (PMOS). The incn:ase of IVml as the temperature is reduced is accompanied by a significant improvement of current for a given overdrive gste voltage (IVos-Vml-Q.SV). At 4K, a subthresbold
swing SSllN of oniy 7mV/ckv is acbieved in tho linear regime (Fig.7). Even st bigh drain voltage (V",,-().9V), thc evolutioo of subthreshold swing versus T remains the same (sec inset of Fia.7). At the same time, the linear current IOllliN of NMOS G02 is eubanced by a factor x6.2 (FiaA). By comparison with 300K, the substantial increase of ckvices performance at low·te:mperatme is summarized in Fta;.9. The saturation current IaoSAT (~os-Vmf'{l.5V and V",,=O.9V) incn:ases due to bigher mobility while the subthreshold swing SSSAT remains very low. GOI transistors (NIPMOS) show a higher saturation current than G02 transistors due to a lower EOT.
Back bi ••• fflciency down to 4K The use ofback biasing (BB) is a key factor in optimizing performance. and power consumption. Therefore, maintaining its efficiency at very low temperatures is aucial. In addition. back·biasing can lWovide a useful cootml tool for qubits. eoabliog fast readout circuin-y sod a lnnable coupling between neighboring quaotom dots 14,6J. Tbe Vm cootrollability offered by the back-gste a14K is ShOWD in FiI.IO. Compared to 300K, the BB factor (y-!Nmlt.VBACK) for N ood PMOS n:mains uuchaoged (FIg.ll). It means that the ckvioe behavior is not alten:d by frccze-<J\lt l'hcnomena who are likely to play an important role at low-temperature 18,9], At short gste leugth (La=28nm). the ckviee performaoces (Fig.Il) studied on NMOS GOI transistors leads to a similar conclusion. The subthreshold swing is strongly reduced with T independently of1he active layer width W (Fig.13). FIg14 shows that at 28nm gate length. the linear current (IVos-Vm!=O.5V) is significantly improved (+62% at 4K). Tbe effect oCBB measured at 4K is ickntica1 to tlte 300K ooe (F1c.lS). In case of PMOS 001. low-temperature combined with a sbart La lead to a modification of subthreshold behavior: oscillations occur at Low VDS (FIc.I6). They an: most likely induced bytbe presence of ciopaol!l diffused from SID into the chaoncl I13J . However. these ""cillatians are strongly soppr<SSed stbigh Vns(Fig.I7).
Device analoR performa ... do ... to 4K Device aoalog performlUlQC is also as:IC8SOCI down to 4K throogh tbo key paramctera such as the II1lD8coDductan Gr... tbe output cooductaoce On and the intrinsic gainAvo= Gw'Gn. The figure of merit GWIns 'Vs InsxLJW for NMOS (n:sp. PMOS) GOI is reported in F • • 18 (rcop. Flg.19). Since GMiIns is inversely proportioml to the subthreshold swing (in weak inversion) and proportional to ~EFP (in strong inversion) the [GWIos liS Ins] metric at 4K is strongly improved. GWW va intrinsic voltage gain (Avo) is shOWD in Fig.20. Low-temperature and back-biasing siguificantiy improve the transconductance OM (due to increased ~) and the intrinsic gain Avo (due to reduced On).
ConclulioDI For the first time, the opcratioo of28nm FOSOI CMOS technology was successfully demonstrated down to 4K. We have shown that a reduced temperature operatiOtl largely improvea CMOS ckvice performance. Additiooally. UDder a DC operatioo, the ability to adjust Vm through back-biasing n:maina uuchanged at 4K. This unique capability could be particularly helpful in the devclopmc:nl of tltst power-cfficient pcriphcntl circuitty (multiplexing. cootrol and n:adout of qubits) and allows incn:ased fleXIbility in the design ofa sca1able dusica1-quantom imerfaoe. Atknowledgemeals: We odmowIedge finaocial support from the ElI under Project MOs-QUITO (No.688539).
RefereDcn 11) R Kawakami et m., Nature NaIJotzdJ., 9, p.666, 2014. 11] J.T. Muhooen et aJ., Nature Nonotech.. 9, p.986, 2014. (3] M Vcldhortn et al. , Nature Nanotech.. 9, p.981.2014. [4] S. De FfIIlccschi et al. , EUROSOl-UUS, p.l24, 2016, [5] L. Hulin et aI., p.1-2, VLSI,2016. [6] Dc Fnmceschi eI aJ. , /EDN.. 2016. [7] G. Ghibaudo et al., Microelectronics Eng., 19, p.833, 1992. [8] E. Simoen et al., IEEE TED. 42. pllOO, 1995. [9] E. Charbon et al.,lEDM, 2016. (10] N. Planeset a/., VLSI. p.133, 2012. [11] M Casse et al., IEEE TED, 53, p.759, 2006. Pl] V.-H Nguyen et al., IEEE TED. 61. p.3096. 2014. [13] R W"'QUCZ et a1 .• VI.SI. p.193. 2010.
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Min CPP-11.nrn M1 pltdla90nm T_ -7nm G.te: HKMG mlllal SID: 81 EPI ... 1/1
(b) (t)
Fig.!. (a) Cross-9CC!ion, (b) key ground rules, technology features and (c) TEM ofFOSO! tnnsistDr.
la's T [Kl
10 ' 7 - 300 - 210
~ 10 '9 - 160 ~ 110
10' 11 77 36
- '0 - 4.3
o 0.4 0.8 1.2 VGS [V]
Fig.S. IDs(Vos) for different T (Lo~W~2""" Vns=sOmv, V8AaAlV).
§" 40 _ NMOSGOZ • '" 40 1f ::I NMOS GOl 35 t 3. 120 =~~~ 30 :E I 100 4.3K 12 - yo: 2S b ~ 36 10 "'-,380 . 77 20}
60 7110/1 -~ 160
j>- 40 Z10 20 ,~'
60 40 20 o SSs",r [mV/dec]
Fig.9. lrosAr versus SSMT fordiffc:rent T (Lo=W~~m for G02 and l.o='W~I~m fo<GOI). VOAaAlV.
80 NMOS GO' f:~ ...... 60 ". ]20 " ... ~ ~ •••• ~ :::l ° .... ~ •••• " 250 T (KI 0
.§.40 ·· ... A J ... theory ··· ... Vl 20 + W - aOnm ". '"
.. W _ 210nm ..... ::\.... W - 1pm .••• :-
~~00~--2~0-0--~,~00~--~0 T [Kl
Fig. 13. SSUN vcrsus T for NMOS with various W (L,=28run. Vos--sQmV. VOAaAlV). SB..,(T) is in inset.
l a's T [Kl
10'7 - 300
~ 10'9 2'0
- 160
~ 110 77
10 '11 36 - '0
10,13 - 4.3
-, .2 -0.8 -0.4 0 VG, [V]
Fig.!7. loo(Vos) for different T (VSAC.-<JV, 1.o-28nm and w - sOorn).
30 NM05G02 3000 400 ..... "" • 00 NMOSG02 PMOSGOl
'5 r T[K] - 300
210 - 160
110 36
-10
2500 2500 .... ,,"
/. .... 00'
_ 20
'" ~2000
';j' 300 i zoro , > >
:;:15 T [K] "',i 1 500 - '00 "'i 200 '"
T [K)
- ' 00 m ; 1500
"'i 1000
~ 500
, 10 -+ ~n;
$ 1000 - '''' $ '" - '''' ~ 36 ~ 100 '" " ,
- 4.3
O~~~~~~~~ 500 -" -n ./ "
o 0. 4 0.8 1.2 VGS (V]
Fig.2. Gate-channel capacitance versus V GS for different T (Lo- W- 2""" VSAC.-<JV).
' 0" ,......==------:--:-:-=-, PMOS G02
T [K l - 300 - 210 - 160
110 77 36
-10 - 4.3
-1.2 -0 .8 -0.4 VG, [V]
o
Fig.6. Ios(Vos) for different T (Lo~~",", Vns=SOmV, VOAaAlV)·
VIlAC( (V]
- -0.9 - -0.6
-0.3 - 0
0.3 - 0.6 - 0.9
NMOS
G02
-1.0 0.0 1.0 VGS [V]
Fig.IO. Ins(V(J5) for different VQACK (Lo~W~~m,Vns=SOmV, T=4.3K).
150
...... 140 E .i 130
;< , 20
) 11 0
'00
NMOS GO '
",, "
• W - 80nm .. W_210nm
W . l p m
300 200 '00 0 T [K]
Fig.14. lcn.IN versus T for difi.'crcnt W (L«=2Snm Vns=SOmv, VSAaAlV)
250 NMOS GOl
200
VIIACK [V]
- 0.6 - 0
-0.6 ~ 1 50 r-~W,'~
~ 100 • '" SO
1 O' ll 10-10 10'8 10-6
io,' L,/ W [A] Fig.IS. ~s VJ' IDSxlofW for different V""", T. NMOS GOI device with l..g=28nm and W=8Onm.
- 4.3 - 4.3
00 1 2 3 4 5 0 0~'-1 -:-, -:-3' 4-!' 0 o 300 200 100 0
N1NV [1012cm'2] NIHV [1012
cm' l ] T [IC)
Fig.3. Electron and hole IJ.EIIF versus NINVfor 4K...<T900K (1o~W~~m, VSAaAlV).
Fig.4. J.LE'PF.MAX versus T. Lo=W=2J.Lm for G02 and Lo=W= lJ.LmforGOl. VBA.cr=QV
80 r----::i"'::.-."-... -_ ... -_ .. -~~ _ 60 . _
~ J Z~..., > '." 2S0 0 S 40 ' T [K]
... theo~··). J • NMOS GOl',._ (/) 20 NMOS GOl
PMOS G02 PMOS GOl
~~00'----~20-0~--'~0~0----~0 T [Kl
Fig.7. SS[JN versus T (Lo=W~"," fur G02 and 1o- W- I ~m for GOI).
VSACI< [V] (PMOS) 0.5 0 -0.5 - 1
150r-:-------,
\
I'MOSGOZ ... ,00<
4. 31( i 100
o 50 ~ Reverse '" FOfWafd
J 0 - -- -(i.> 6I.--.g Bi<o"..-.g
I -so (FIBS) ~~F8B;) '% -100 ' NMOSGOZ >" _ 3001<.
-150 4 3K
·1 -0.5 0 0.5 1 V8AQ( [V] (NMOS)
Fig. I I . Vrn,NUtM vrrsus VDACK (GOIfG02 devices, v",~OmV).
10'5 VBAr:>:. [V] - ,0. 9 NMOSG01
10'7 - -0. 6 -0.3
~ 10 ,9 - 0
~ 0.3 0.6
10'11 - 0.9
14o~ l' 20 '\ >!i 0 RBS __ FBB
" ·20 300K :::-~ ·40 · • 4. 3K
10 .13 11
> ·1 0 VIJO. [vI
a 0.4 0.8 1.2 VGS [V]
r.- N-NO-' -GO-, --------' 7 NMOSGOI 6 f PMOSG02 •• z PMOSGOI 5 ~
x6.2
4~ 31 2 ;;
" 19 o 0 300 200 100 a
T [Kl Fig.S. Ia..1N versus T (Lo~W~"," fur G02 and 1o~W=I~m furGOI). VSAaAlV.
T [Kl - 300
210 - 160
11 0 77 36
- '0 - 4.3
o 0.4 0.8 1.2 VGS [V]
Fig.12. I".(V "') for different T (V",-SOmV, VOAaAlV, l.o='28nm W_).
1 O·s r==;::;;;:::::::-~;-:>00Nl
T [Kl - 300
210 - 160
110 77 36
-10 -4.3
-1.2 -0.8 -0.4 0 VG, [V]
Fig.IS. J",(V",) fur different VSA« (W=28orn Vns=SOm V, T=4K). The effect ofBB is shown in the inset.
Fig.!6. Ios(V",) fo< different T (VOAaAlV, 1o~8nm and ~8Omn).
200 PMOSGOI
SO
VSAQ( (V] - 0.6 - 0
-0.6
10, ll 10'10 10'8 10'6
io, ' L,;/W [A] Fig.19. GM'1na liS InsxLdW for different VBACIC, T. PMOS GOI device with l.o='28nm and w~sOnm.
1., r---;,;;;"",= GO;;;'Cl 1.0 fMOS GOI W _ 300m!
~ : ~:..... _ L.;_ l Btvn
I:: f~~ I:: 1 ...... [7-~0.9 i .4.3K,Vo..cx.Q.8V J 07 ! 4.3(.Vo..cx_-O. 8V .
'. V"._ 1V 300K 0.8 v~ _ v", ~ 0.5V 0.6 v". _ 0.9V Vo;.s. v", - 0.5V
5060708090 5101SZ0Z530 I!1trinsk: gain, Avo [dB] IntrinsIC galO. Avo [dB]
Fig.20. GWW vs Avo for different T, W, 10 and VSAcr. NlPMOS GOI device.
![Characterization and Modeling of 28-nm FDSOI CMOS ...analytical model for bulk cryogenic MOSFET operation [27] has been proposed, which has been developed start-ing from the Poisson](https://static.fdocuments.net/doc/165x107/606785df43df281dd4363617/characterization-and-modeling-of-28-nm-fdsoi-cmos-analytical-model-for-bulk.jpg)
