2480 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 11, NOVEMBER 2007

Hybridization of CMOS With CNT-BasedNano-Electromechanical Switch for Low Leakage

and Robust Circuit DesignRajat Subhra Chakraborty, Student Member, IEEE, Seetharam Narasimhan, Student Member, IEEE, and

Swarup Bhunia, Member, IEEE

Abstract—Exponential increase in leakage power has emerged asa major barrier to technology scaling. Existing circuit techniquesfor leakage reduction either suffer from reduced effectivenessat nanometer technologies or affect performance and gate-oxidereliability. In this paper, we propose application of a specificcarbon nanotube (CNT)-based nano-electromechanical switch asa leakage-control structure in logic and memory circuits. In case ofmemory circuits, we demonstrate that the proposed hybridizationcan be employed to reduce both cell leakage and bitline leakage,thereby improving the read noise margin as well. Due to theunique electromechanical properties of CNTs, these switches havehigh current-carrying capacity, extremely low leakage current,and low operating voltages. Moreover, they can act as nonvolatilememory elements, which can be exploited for data retention ofimportant registers and latches during power down. Simulationresults for a set of benchmark circuits show that we can obtain sev-eral orders of magnitude improvement in leakage saving in logiccircuits at iso-performance compared to existing multi-thresholdCMOS technique. In memory circuits, simulations show 19

reduction in standby leakage and 55 reduction in bitlineleakage compared with the best existing techniques.

Index Terms—Bitline leakage, CMOS logic circuits, CMOSmemory circuits, nano-electromechanical switch (NEMS), leakagereduction.

I. INTRODUCTION

ONE OF THE MAJOR challenges with aggressive tech-nology scaling is the dramatic increase in leakage power

with each technology generation. At nanometer scale, CMOSdevices suffer from severe “short-channel effects” [1], whichcombined with greater gate-oxide tunneling leakage, resultin large device current in the OFF state. The leakage power ispredicted to constitute nearly 50% of chip power at and beyond65-nm technology nodes [1]. This phenomenal wastage ofpower is clearly unacceptable, more importantly in mobile bat-tery-operated systems. In memory circuits, the effect of leakageis also manifested as a decrease in robustness of read/writeoperations [24].

To address this issue at circuit level, various techniqueshave been proposed to reduce leakage current; particularlythe subthreshold component of leakage, in both logic andmemory circuits [2]–[9]. These techniques can be broadlycategorized into two classes: a) active mode leakage reduction

Manuscript received December 19, 2006; revised April 19, 2007. This paperwas recommended by Guest Editor C. Lau.

The authors are with the Department of Electrical Engineering and ComputerScience, Case Western Reserve University, Cleveland, OH-44106 USA. (e-mail:rsc22@ ase.edu; sxn124@case.edu; skb21@ case.edu).

Digital Object Identifier 10.1109/TCSI.2007.907828

and b) standby mode leakage reduction. Dual assignmentand adaptive body biasing (ABB) have been proven effectiveprimarily for active mode leakage reduction, although theyresult in leakage reduction in standby mode as well. However,scalability of these techniques at sub-65-nm technology nodeshas been questioned. Dual- technique [2], [3] suffers from itsnegative impact on parametric yield under process variations aswell as from diminishing difference between high- and low-values realizable at a process node. ABB suffers from largeincrease in band-to-band junction tunneling current (BTBT)[4]. On the other hand, standby-mode leakage reduction ispredominantly based on multi-threshold CMOS (MTCMOS)technique and its variants. The basic idea in MTCMOS designis to use a low- or dual- core (for high-performance) anda high- sleep transistor (for low leakage) that effectively“gates” the power supply in standby mode. To avoid perfor-mance impact due to the sleep transistor, it requires to besized judiciously. A major variation to the standard MTCMOSapproach [9] is to overdrive the gating transistor in active modefor high performance and/or underdrive it during standby modefor higher leakage saving. Apart from the overhead of biasingcircuitry for over/under-drive, an out-of-rail voltage in thisapproach causes gate oxide reliability problem (particularlyfor devices with thin gate oxide) as well as large increase ingate-induced drain leakage (GIDL) current [1].

Although MTCMOS-based supply gating can reduce leakagecurrent significantly, it cannot retain values in registers andlatches. It is important for the critical data held in state registersand latches to be restored when the system wakes up frompower-down mode. To achieve data retention in critical storageelements, broadly three major techniques have been proposed[5]. The first method relies on application software that writesspecified register values to disk storage before shutting downpower supplies and back again when re-entering the activemode. Although it requires no special hardware design, theprocess is too time-consuming and power-hungry to be prac-tical. The second scheme uses a scan chain to shift out theregister states into an always powered memory before powerdown and shift-in during wake up. The major disadvantagesare still time and power consumptions during memory access.In the third method, a high- “shadow latch” is added tothe normal register or latch to save the register’s state duringpower down. To maximize the leakage saving in the shadowlatch, a reduced but just sufficient voltage supply is used forthese circuits, so that they still retain their values. However, animportant problem associated with this scheme is the routing of

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CHAKRABORTY et al.: HYBRIDIZATION OF CMOS WITH CNT-BASED NANO-ELECTROMECHANICAL SWITCH 2481

two separate supply power lines. Further, since these high-CMOS shadow latches remain powered-on during standbymode, they also suffer from some leakage, which increaseswith technology scaling. Finally, these high- shadow latchesare more prone to soft error due to alpha and neutron particlehit [10] and thus likely to result in erroneous stored content incase of single event upset (SEU).

In case of Static Random Access Memory (SRAM) circuits,numerous leakage reduction techniques have been investigated.A very effective technique for memory circuits is source bi-asing [33], which “gates” the supply and applies a positive biasvoltage at the source of nMOS transistors (of a memory cell),such that the rail-to-rail voltage is reduced resulting in memoryleakage reduction. The technique selects a bias voltage in sucha way that ensures data retention while maximizing leakage re-duction. In both MTCMOS (for logic circuits) and source bi-asing (for SRAM) techniques, the sleep transistor itself, whichis typically made wide for acceptable performance, remains asignificant source of leakage current.

To address major circuit-level design issues with nano-scaledCMOS, several new devices like carbon nanotube (CNT)-basedfield-effect transistor (CNTFET), molecular electronic switchesand ferromagnetic logic devices have been proposed as alterna-tives to CMOS at the end of its roadmap [23]. Although some ofthese devices offer promising features in terms of device opera-tion, integration density, power and performance, a rapid transi-tion to an alternative device or computational paradigm appearsinfeasible due to lack of mature fabrication process as well asdesign and analysis tools.

In this paper, we propose a novel hybridization scheme,which addresses the leakage-induced power issue of CMOStechnology using nano-electromechanical systems (NEMS)switches as leakage-control elements. A specific NEMS switchreferred as complementary NEM switch (CNEMS), with CNTsas active elements is used as a platform device to controlleakage in CMOS logic/memory circuits and to retain dataduring power down. The CNEMS structure has the followingdistinct features making it amenable to leakage-control appli-cations: 1) the electromechanical nature of the switch resultsin virtually zero standby-mode leakage; 2) the switch behaveslike a nonvolatile memory (NVM) element and 3) it has lowoperating voltage V , low transition time ns , andlow transition energy.

The paper makes the following contributions.1) It exploits the unique electromechanical properties of

CNTs for leakage reduction in CMOS logic circuits. ACNT-NEMS device with specific characteristics (CNEMS)is chosen for this purpose.

2) It uses the NVM-mode operation of CNEMS for data reten-tion in standby mode, which allows complete power downwhile eliminating the possibility of soft-error induced datafailure.

3) It proposes a hybridization scheme of the CNEMS de-vices with conventional 6-T CMOS SRAM cells to reducestandby leakage in embedded memory.

4) It employs CNEMS to reduce bitline leakage in SRAMarray during read operation, thereby improving the readnoise margin.

The remaining part of the paper is organized as follows. InSection II, we present some emerging CNT NEMS switch struc-tures, followed by working principle of CNEMS. Leakage re-duction in logic circuits using CNEMS is described in Sec-tion III. In Section IV, we present standby data retention usingCNEMS. In Section V, we discuss the application of CNEMS inSRAM circuits to prevent cell and bitline leakage. In Section VI,we present simulation results for logic and memory circuits. Weconclude in Section VII.

II. STRUCTURE OF CNEMS AND ITS WORKING PRINCIPLE

A. CNTs as NEMS Switch

CNT-based NEMS structures have been intensively investi-gated in recent times. CNTs are particularly suitable for NEMSapplications due to their well-characterized physical and chem-ical properties and their exceptional electrical and mechanicalbehavior [13]. In recent years, many different NEMS switchesbased on CNTs have been proposed. Fig. 1(a)–(c) presentsseveral recent CNT-NEMS devices [11]–[13], two of whichcan operate as cantilever structures. In [11], a switch basedon multi-walled CNT cantilever structure suspended overmetallic trenches has been described. The switching behavior isobserved by noting the current at the bottom electrode, whichshows an abrupt increase beyond a certain “threshold” voltagedifference between the nanotubes and the bottom electrode.However, a key limitation of this device is the low ON-statecurrent nA at a bias voltage of around 3 V. In [12], athree-terminal multi-walled carbon “nanorelay” has been pre-sented. The switch operates by the application of bias voltagesbetween two electrodes and the current is measured at the thirdelectrode. The device operates at a comparatively high-voltage

V , and there is considerable fluctuation in the ON

current. In [13], the authors report the operation of an electro-mechanical CNT switch, which lso has comparatively low andrandomly fluctuating ON current nA .

B. CNEMS Structure and Operating Principle

Compared to the CNT-NEMS switches described in theprevious subsection, the switch proposed in [14] referred asCNEMS has certain properties which makes it more suitable forhybridization with CMOS as a leakage reduction and data re-tention device. The structure of the switch is shown in Fig. 1(d).It contains three co-planar CNTs of cantilever geometry, whichare initially unconnected. The switch can be toggled betweentwo complementary configurations by the application of anelectric field between the central CNT and either of the twoCNTs on the side. Once configured in a certain way, the switchremains in the same state until an opposite electric field isapplied to reconfigure the switch. This is because of the van derWaals’ interaction between the CNTs [22]. Due to this latchingmechanism, each switch works as a NVM element. The criticalphysical parameters of the structure such as turn-on voltageand switching speed are estimated below.

To calculate the “turn-on” or the “threshold” voltage, wenote that the total energy of two adjacent CNTs is given by

. Next, we note thatthe electrostatic and van

2482 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 11, NOVEMBER 2007

Fig. 1. (a) Self-assembled switches based on electroactuated multi-walled nanotubes [11]. (b) Three-terminal carbon nanorelay of a CNT cantilever beam switch[12]. (c) Single-walled nanotubes suspended over shallow trenches in SiO , with a Nb pull electrode [13]. (d) CNEMS. The central CNT (CNT1) is either touchingthe top (CNT2) or bottom (CNT3) CNT [14].

der Waals’ forces are both attractivewhile the elastic force is not. Thus,at , all the forces acting on the CNTscancel out and this results in a stable configuration. When

the van der Waals’ forces overcome theelastic force and CNTs can latch onto each other. Clearly, thissituation should be achieved after application of a voltage pulsebecause otherwise, the CNTs will spontaneously clamp ontoeach other. This simple but important observation puts a limiton how close the CNTs can be to each other. To demonstratefeasibility of switching and latching with reasonable voltages,we consider the CNEMS structure schematically shown inFig. 1(d). The two energies are equal at nm for

nm and of 20 nm.The electrostatic potential needed to bend the 50-nm long

CNT to achieve a deflection of nm is around 10 V. Insubsequent switching, however, this voltage will drop to around1 V. The main reason for this reduction is that the stored elasticenergy causes the center CNT [CNT1 in Fig. 1(d)] to springback towards CNT3 when it is released from CNT2. The vander Waals’ force latching CNT1 and CNT2 is almost entirelybalanced out as soon as CNT1 and CNT2 are charged with thesame polarity. Noting that CNTs have very large Young’s mod-ulus of around 1.3 TPa, very fast CNEMS with sub-nanosec-onds switching times can be realized. The proposed CNEMShave large on-to-off conductance ratio , very high cur-rent-carrying capability [34] and are radiation hard.

C. Hybridization of CMOS With CNEMS

The main challenge of combining traditional CMOS cir-cuitry and CNT structures on the same substrate is the highertemperature required in the growth process of the CNTs. Thiscauses adverse impact on the transistors built on the siliconsubstrate when CNTs are grown after MOSFET fabrication.Recently, several techniques on CMOS-compatible growth ofCNT have been proposed and experimentally validated. In thefirst approach, “localized heating” is applied using microscaleresistive heaters [16]. This creates small regions with extremelyhigh temperature, but the operation is globally carried out atroom temperature and thus remains CMOS compatible. Inthe second approach, plasma-enhanced chemical vapor depo-sition (PECVD) is applied to grow CNT structures on eithermetal [38] or the semiconductor (Si) substrate [35], [39]. Thethird technique achieves “self-assembled, surface-oriented”growth of CNTs using iron nanoparticles as catalyst [39]. Inthe fourth technique, single-walled CNTs are “solubilized”and then applied to the active CMOS substrate to grow func-

Fig. 2. Possible way to hybridize CNEMS with CMOS.

tional NVM devices [40]. Finally, in [24], high aspect ratiocylindrical “nanowires” are grown using porous membranes as“templates,” and manipulated using dielectrophoretic forces.A possible integration solution, shown in Fig. 2, consists ofseparate layers for MOSFET and CNEMS, with a metal inter-connect layer in between.

D. Equivalent Electrical Model for the CNEMS Structure

To measure the leakage and performance of the hybrid cir-cuits using CMOS and CNEMS, we need to use an accurate cir-cuit-compatible model for CNEMS. We have used the widelyaccepted transmission-line model [15] for CNT interconnects.The assumption is valid for CNEMS since the CNTs used inCNEMS are meant only to act as conducting wires when con-nected. The transmission-line model of a single nanotube isshown in Fig. 3. It consists of the series resistance and se-ries inductance , corresponding to the contact resistance andthe kinetic inductance, respectively. It also contains two shuntcapacitors and corresponding to the quantum capaci-tance and the coupling electrostatic capacitance [15]. The valueswere taken from previously published investigation results as

k , nH m, aF m, andaF m for metallic SWCNT, respectively, as men-

tioned in [15], [17] and [18]. We have neglected the magneticinductance, which has a very small reported value of 1 pH/ m.The coefficient of 4 for the quantum capacitance in the modelis due to the presence of 4 quantum conduction channels in par-allel. As shown in [19], it is possible to fabricate nanotubes withresistances approaching the theoretical limit of 6.45 k . Wehave also taken an extra resistance of 1 k which accountsfor the via resistances (assuming CNTs are grown on separatelayer).

III. LEAKAGE REDUCTION IN LOGIC CIRCUITS

In this section, we describe the application of CNEMS as aleakage reduction device in CMOS logic circuits.

CHAKRABORTY et al.: HYBRIDIZATION OF CMOS WITH CNT-BASED NANO-ELECTROMECHANICAL SWITCH 2483

Fig. 3. Equivalent circuit model for CNEMS.

Fig. 4. (a) Conventional MTCMOS scheme. (b) Logic block with an array ofCNEMS incorporated as gating devices.

A. Motivation of Using CNEMS

Supply gating techniques using sleep transistor have beenshown effective for leakage saving in standby mode and arescalable to future technology nodes. Sleep transistor-basedleakage reduction is predominantly based on MTCMOS ap-proach [1], [9], which uses high- sleep transistor to a low ordual- core [Fig. 4(a)]. The MTCMOS technique typicallysuffers from the following drawbacks: 1) it adds extra resistanceto the charging (for pMOS sleep transistor) or discharging path(for nMOS sleep transistor) and thus degrades performanceand 2) the sleep transistor itself can be a considerable source ofleakage. To reduce performance penalty and maximize leakagesaving, a high- sleep transistor can be overdriven in activemode [36] or a low- one can be underdriven in standby mode[37]. However, in both cases, the out-of-rail voltage causesgate oxide reliability problem and increases gate induced drainleakage.

The unique structure of the CNEMS switch allows the dis-charge path to switch between a low resistance path in the activemode (for high performance) and a separate high virtual groundvoltage path in the sleep mode (for low leakage).

B. Using CNEMS for Leakage Control in Logic Circuits

The proposed scheme for using CNEMS as a leakage reduc-tion device in combinational logic circuits has been shown inFig. 4(b), and compared with the MTCMOS scheme as shownin Fig. 4(a). The “B” terminal of the logic block acts as the vir-tual ground node, which is connected to the central ter-minal of 3-terminal CNEMS. Depending on the voltage at theother two terminals, the central terminal is attracted and getsconnected to either of the side terminals. The terminal “A” isalways connected to . However, by controlling the voltageat “C,” we can make the terminal “B” switch between terminal“A” and “C.” In the “active” mode of operation, terminal “B”

Fig. 5. (a) Timing diagram of the CNEMS terminal voltages. (b) Sleep-modecurrent waveform in the proposed scheme.

touches terminal “A” and is thus directly connected to ground.During this time, terminal “C” has a voltage below the thresholdrequired to attract terminal “B.” However, when the circuit goesto the sleep mode, the voltage at terminal “C” rises above theswitching threshold for the device, and thus terminal “B” shiftsto “C.” After this happens, the voltage at “C” goes back toits lower (but nonzero) value, which makes the voltage at the

terminal high and thus reduces leakage, by decreasing therail-to-rail voltage of the logic circuit. When the circuit needs toshift from the sleep to the active mode, the voltage at terminal“C” is again made high. Terminal “B” gets this high voltage, andhence is attracted to terminal “A.” Fig. 5(a) shows the timing di-agram of the voltages at terminals A, B, and C.

It is important to consider the energy dissipation in thisscheme. During the switching of the CNEMS switches, someenergy ( eV per switch) is required. Due to charging ofvirtual ground voltage from 0 to , the nodes of the logicblock which were at logic level 0 (and hence have a path to

) due to the applied input vector, will have a voltagetransition from 0 to . This will cause a current surge from

to these intermediate nodes initially. But after the initialsurge, the leakage current through the logic circuit will besignificantly reduced, as shown in Fig. 5(b). The “MTCMOS”scheme will also have an initial transition loss, followed bya steady leakage current through the sleep transistor. But thesteady-state current in MTCMOS will be more than that in theproposed scheme for equal performance penalty.

The effect of the nanotube resistance in the discharge pathduring the active mode of operation is also an important con-sideration. It is expected to increase the discharge time of theoutput node capacitances, and hence to adversely affect the falltime, which is roughly proportional to the on-resistance of thedischarging path. To reduce the net resistance presented by theswitches in the discharge path to ground, an array of CNEMSswitches is to be used.

2484 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 11, NOVEMBER 2007

Fig. 6. (a) CNEMS latch (inverting). (b) Initial configuration.

IV. STANDBY-MODE DATA RETENTION

The techniques described above for leakage reduction in com-binational circuits are not directly applicable to sequential cir-cuits since the output values of the circuits may not be retainedduring the sleep mode. This is not a concern in combinationalblocks since sleep modes are selected when the outputs are ofno consequence. But it is important to store the content of im-portant state registers and latches during power down and re-store them on wake up. An effective low-overhead technique forstate retention and restoration is based on using a low-leakage“shadow” latch [5]. Next, we will describe a CNEMS-basedlatch, which can be used as efficient alternative to shadow latchfor nonvolatile data retention.

A. CNEMS-based Inverting Latch

Fig. 6(a) shows a possible implementation of a stable in-verting latch structure using CNEMS [14]. To write a value inthe latch, it requires to be configured as in Fig. 6(b), by cre-ating a voltage difference between terminals B and C. Bringingthe latch to this initial state is important in order to configurethe CNTs to a position from where they can make a transi-tion when the input is connected. When the clock signal closesthe switch at the data terminal, the input data (say logic 0) ap-pears at terminal A. This causes the nanotubes at A and C ofthe upper CNEMS structure to get attracted to each other, andafter coming in contact, they remain connected due to the vander Waals’ force of attraction. This means that a new logic value(logic 1) appears at the output terminal. The clock signal keepsthe switch ON for a very short time to minimize short circuitcurrent between the input and output terminals. Similarly, whena data value 1 appears at the input, the nanotubes between ter-minals B and C of the lower switch structure connect and logicvalue 0 appears at the output. It should be noted that the latchstores the complement of the value written into it. Due to theunique property of the switch, it retains the configuration evenon removal of the voltage and hence, it acts as a NVM el-ement.

B. Previous Work on Standby-Mode Data Retention

Several schemes have been proposed to preserve data in thestandby mode using MTCMOS scheme [6]–[8]. In [6], high-MOS inverters connected directly to the and the GND ter-minals are used to retain data in the sleep mode, while low-inverters in the latch path are used to maintain performance inthe active state. This circuit successfully preserves data in the

sleep mode, but it creates a bottleneck during high-speed oper-ation due to high- transistors of the transmission gates in thecritical path. Moreover, since the high- power transistors mustbe large enough to supply power to the data-path inverters, thiscircuit incurs considerable area and power overhead comparedto conventional latch [8]. In [7], the level holder circuit has beenused in the sleep mode to hold the data. However, in this scheme,as in the latch circuit [9], high- power transistors also have tobe connected to low- data-path inverters independently to cutoff the standby leakage path. This also increases the delay andto reduce this delay, high- power transistors need to be made8 larger than low- transistors. To address these problems,in [8], a “balloon memory circuit” has been used in conjunctionwith a flip-flop. However, it incurs an area overhead of 43% overthe conventional flip-flop. Both schemes are also vulnerable tosoft-errors.

A more attractive option would be to store the data inthe standby mode using high-density NVM. However, withtechnology scaling beyond 32 nm, new challenges emerge inthe field of nonvolatile memories implemented with emergingnanometer devices [20] such as Flash devices, FeRAM, NROM,MRAM, etc. In Flash devices, high-electric field stress andextremely thin tunnel oxide in scaled devices are the mainchallenges [23]. In FeRAM, it is difficult to find ferroelectricmaterials that provide both adequate change in polarizationand the necessary stability over extended operating cycles. TheSONOS/NROM device technology has shown some progress inrecent times; however, further innovations are needed beyondthe 45-nm technology generation [23]. In case of MRAMdevices, controlling the dimensions and material propertiesis a major challenge along with material sensitivities to ICprocessing temperature. Compared to these NVM technologies,CNEMS appear more promising for data retention applicationdue to CMOS-compatible growth process, higher performanceand low transition power.

C. Motivation of Using CNEMS as Data Retention Device

The application of CNEMS as NVM element to retain regis-ters and flip-flop data during the standby mode has two majoradvantages over existing data retention techniques [6]–[8]: 1)Due to the nonvolatile nature of the CNEMS switch, we canallow complete power down while still retaining the states inregisters and latches, thus improving leakage saving; 2) Datastorage in CNEMS latch is achieved by an electromechanicalswitch and is thus, completely radiation-hard.

D. Use of CNEMS for Data Retention

Here, we describe a scheme for using the inverting latch madefrom CNEMS [14], as the shadow latch. Fig. 7 shows the overallscheme for data retention using CNEMS-based shadow latch.When RD and WR are disabled, the flip-flops in the circuitperform normal operation. However, when WR is enabled, theshadow latches are activated. Each shadow latch stores the stateof the corresponding flip flop and retains it even when powersupply is shut down. When normal operation needs to be re-sumed, the RD line goes high for a short time after power-on,enabling the value stored in the shadow latch to be written back

CHAKRABORTY et al.: HYBRIDIZATION OF CMOS WITH CNT-BASED NANO-ELECTROMECHANICAL SWITCH 2485

Fig. 7. Scheme for standby-mode data retention using CNEMS-based shadowlatch.

into the system flip-flop. The multiplexer logic can be imple-mented using transmission gates, as in [6]. It must be noted thatthe shadow latch, in our case, comes into action only in the sleepmode, so there is no increase in active power, unlike the existingtechniques [6]–[8], where data values are written into the normaland shadow latches at the same time. Also the standby leakage ispractically made zero. Although there is a current path throughthe ON CNEMS, the supply voltage is reduced to zero.

V. LEAKAGE REDUCTION IN SRAM CIRCUITS

With technology scaling, the leakage energy of SRAM cacheshas increased at an alarming rate [25]–[33]. At 130-nm tech-nology, the leakage energy is estimated to be 30% of the totalenergy for the cache and more than 80% of the total energyfor the cache [25]. Added to that is the bitline leakage, whichacts as a noise current source to the sense amplifier, causingslow or erroneous read/write operation [26]. We propose the in-tegration of CNEMS with CMOS-based SRAM to achieve: 1)reduction in cell leakage in standby mode and 2) robustness ofread/write operation by bitline leakage reduction.

A. Use of CNEMS for Leakage Reduction in SRAM

A number of schemes have been proposed to suppress theleakage power in SRAM cells [25], [27]–[30]. Among them,source biasing is a promising technique [27] that uses a gatingtransistor between the source and ground (or ) terminals ofthe cells to cut-off the leakage path during sleep mode. To ensuresteady rail-to-rail voltage, a fixed source-biasing potentialis applied at the source terminal during sleep mode. However,this scheme incurs considerable hardware overhead because itrequires the sleep transistor to have sufficient size so that theRead/Write performance of the SRAM cells is not affected. Thescheme for reducing standby leakage in memory with CNEMSswitches is shown in Fig. 8. Unlike conventional source biasingscheme using sleep transistor, we exploit the unique structureof the CNEMS to connect the virtual ground terminal tothe actual ground in active mode [Fig. 8(a)] and to a biasvoltage in standby mode [Fig. 8(b)], similar to the leakagereduction scheme proposed for logic circuits. In the active mode,the low resistance of the CNEMS switches and their high cur-rent-carrying capacity allows normal operation with minimalpenalty in Read/Write delay. In the sleep mode, the CNEMS

Fig. 8. Proposed leakage reduction scheme using CNEMS switches for sourcebiasing. (a) Active mode. (b) Standby mode.

switch terminal “B” at the virtual ground is connected tothe terminal “C,” which is at a positive bias voltage. This voltageis chosen so that it is below the data retention voltage (DRV) ofthe cell (to ensure data retention), while maximizing leakagesaving.

Several schemes have also been proposed for the reductionof bitline leakage or the mitigation of its effects [26], [33], [34]during read/write operation. In [26], a bitline “compensation”scheme has been proposed that measures the bitline leakage inprecharge phase, and then injects the same amount of currentin the evaluate phase to “compensate” for the bitline leakage.However, this scheme requires a relatively complicated currentsensing and duplicating circuitry as overhead. In [31], a bitlineleakage “equalization” scheme has been proposed that equalizesthe bitline leakage and thus maintains correct functionality ofthe sense amplifier. This scheme uses an 8T SRAM cell in placeof the traditional 6T cell and as a result has a 40% area overheadwhich reduces its practicality. In [32], a bitline leakage reduc-tion scheme has been proposed that underdrives the wordline inthe idle mode to reduce leakage through the access transistors.It requires cell and precharge voltage to be lower than globalsupply voltage.

The proposed bitline leakage reduction scheme usingCNEMS is shown in Fig. 9. We mitigate the effect of bitlineleakage by “re-routing” the leakage path during active mode.The rows of SRAM cells are grouped into separate blocks.When a bitline is charged high and connected to a SRAM cellstoring 0, there is a leakage current through the access transistorfrom the bitline to the node storing 0. The worst-case bitlineleakage occurs when only one cell stores 1 and all the othercells store 0. When the read operation (of the cell storing 1)starts, the sense amplifier might perform a faulty read operationdue to the large leakage current from BL. This is prevented bythe scheme shown in Fig. 9. Here, in addition to the BL and

lines, we have a leakage re-routing path for each block ofSRAM cells. When a wordline is asserted for read operation,the access transistors of all the cells belonging to the blockare connected to the BL and lines. The remaining blockswhich are not being accessed are connected via CNEMS tothe re-routing path, which prevents them from affecting thebitline charge. A pre-decoder (similar to [33]) assigns correctvoltage values to the dummy bitlines and thus controls theconnectivity of the memory cells with the bitline. Since theleakage of nonaccessed rows cannot affect the bitlines, the

2486 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 11, NOVEMBER 2007

Fig. 9. Proposed scheme for bitline leakage reduction in an SRAM array.

TABLE ILEAKAGE SAVING WITH CNEMS IN COMBINATIONAL LOGIC BLOCKS (AT

ISO-PERFORMANCE, V = 1 V, T = 373 K)

voltage droop due to bitline leakage in the BL (or ) lineeffectively reduces to zero.

VI. RESULTS

Simulations of the proposed leakage-reduction and data re-tention circuits were performed in HSPICE using 70- and 45-nmpredictive CMOS technologies [21] and compared with existingtechniques. The CNEMS structure was modeled, as describedpreviously, as a separate sub-circuit.

First, the combinational parts of the ISCAS89 benchmarkswere simulated with sleep transistors and CNEMS as leakage-control structure separately. The size of the gating transistor andthe number of parallel CNEMS are chosen in such a way, thatin the active mode, we have equal performance penalty. Thestandby leakage power values obtained in both cases for a setof benchmark circuits have been listed in Table I. It can be ob-served that we get several orders of magnitude improvementin leakage saving with CNEMS over conventional MTCMOStechnique. For MTCMOS technique, we considered properly-sized high- (30% higher than other transistors) sleep transis-tors as the leakage reduction mechanism for low- combina-tional logic.

For sequential circuits, we need to consider the actual leakageoccurring in nanoscaled CMOS flip-flops using low and high-transistors and compare it to the leakage of CNEMS-basedshadow latch (which is virtually zero). As seen in Table II, ahigh- data retention shadow latch for each of the flip-flopspresent in the ISCAS89 sequential benchmark circuits can stillcause considerable power dissipation in the standby mode.The total leakage is estimated as the sum of the leakage powerdue to the combinational part of the circuits and the flip-flops.The leakage reduces in the MTCMOS technique due to thepresence of the OFF sleep transistor and the high- latches. Inthe CNEMS case, though there is some leakage to the substrate,there is no leakage through the CNEMS shadow latches. Hence,the total leakage saving improves significantly. The leakagecurrent of the nonvolatile CNEMS memory elements remainspractically zero and thus provides higher standby leakagesaving in scaled technologies.

Next, we present the simulation results for the leakage reduc-tion in SRAM cells by the proposed technique. Table III showsthe reduction in standby leakage for an SRAM cell for PTM45- and PTM 70-nm models, compared to the source biasingscheme. We observe an improvement of for the 45-nmprocess and an improvement of for the 70-nm process.Table IV shows the improvement in bitline noise margins dueto the proposed scheme. The simulated BL and waveformshave been shown in Fig. 10 for the 45-nm process. It can be ob-served that the leakage in the bitline reading a 1 causes a voltagedroop of almost 200 mV in just 800 ps, reducing the read noisemargin considerably. On the other hand, the proposed bitlineleakage reduction scheme alleviates this problem by reducingthe bitline current ( ).

VII. CONCLUSION

We have presented the application of a CNT-based NEMSswitch, referred as CNEMS, for leakage reduction in CMOSlogic and memory circuits. CNEMS exploits the superiorelectromechanical properties of CNT to achieve low operatingvoltage, high current-carrying capacity and nonvolatile latchingmechanism. These properties can be utilized for leakage re-duction in standby mode, while incurring low performanceoverhead in active mode. Moreover, CNEMS-based nonvolatilelatches can be integrated with CMOS flip-flops for data reten-tion during power down. For memory circuits, the cell leakagecan be reduced and undesired bitline droop can be mitigated

CHAKRABORTY et al.: HYBRIDIZATION OF CMOS WITH CNT-BASED NANO-ELECTROMECHANICAL SWITCH 2487

TABLE IITOTAL LEAKAGE SAVING IN SEQUENTIAL BENCHMARK CIRCUITS USING CNEMS FOR LEAKAGE REDUCTION AND DATA RETENTION

TABLE IIICOMPARISON OF LEAKAGE REDUCTION WITH SOURCE BIASING SCHEME IN

STANDBY MODE

TABLE IVIMPROVEMENT IN READ NOISE MARGIN (DUE TO BITLINE LEAKAGE) (VALUES

AFTER 800 PS, V = 1 V, T = 300 K)

Fig. 10. Reduction in read noise margin due to bitline leakage (V =

1V; T = 300 K, 256 rows).

by redirecting the bitline leakage using CNEMS. Simulationresults on benchmark circuits show that using CNEMS, we can

obtain large improvement in leakage saving at iso-performancecompared to the existing techniques. The leakage improvementis less in case of memory, since the rail-to-rail voltage cannotbe reduced arbitrarily without affecting the stored content.

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Rajat Subhra Chakraborty (S’07) received theB.E. (Hons.) degree in electronics and telecom-munication engineering from Jadavpur University,Kolkata, India in 2005. He is presently workingtoward the Ph.D. degree in computer engineering atCase Western Reserve University, Cleveland, OH.

From 2005 to 2006, he worked as a CAD SoftwareEngineer with National Semiconductor at their IndiaDesign Centre, Bangalore, India. He has also held aninternship at the same office. His research interests in-clude design of low-power and robust VLSI systems,

computer-aided design and developing VLSI approaches for nanoelectronicsand molecular electronics.

Seetharam Narasimhan (S’07) received the B.E.(Hons.) degree in electronics and telecommunicationengineering from Jadavpur University, Kolkata,India, in 2006. He is working toward the Ph.D.degree in computer engineering at Case WesternReserve University, Cleveland, OH.

His research interests include design of low-powerand robust VLSI systems for bio-implantable circuitsand nano-electronics.

Swarup Bhunia (S’00–M’05) received the B.E.(Hons.) from Jadavpur University, Kolkata, India, in1995, the M.Tech. degree from the Indian Instituteof Technology (IIT), Kharagpur, India, in 1997,and the Ph.D. degree from Purdue University, WestLafayette, IN, in 2005.

Currently, he is an Assistant Professor of ElectricalEngineering and Computer Science at Case WesternReserve University, Cleveland, OH. He has workedin the semiconductor industry on RTL synthesis,verification, and low power design for about three

years. His research interest includes low-power and robust VLSI design,adaptive nanocomputing, and bio-implantable devices for neural engineering.

Dr. Bhunia received the 2005 SRC technical excellence award as a teammember, the Best Paper Award in International Conference on Computer De-sign (ICCD 2004), the Best Paper award in Latin American Test Workshop(LATW 2003), and the Best Paper Nomination in Asia and South Pacific DesignAutomation Conference (ASP-DAC 2006). He has served in the technical pro-gram committee of Design Automation and Test conference in Europe (DATE2006–2007), International Symposium on Low Power Electronics and Design(ISLPED 2007), Test Technology Educational Program (TTEP 2006–2007), andon the Program Committee of International Online Test Symposium (IOLTS2005).