Quartus II Basic Training

2010 Altera CorporationConfidential

AgendaIntroduction to Altera Devices Quartus II Development system overview Timing Analysis Quartus II Quick Start using Galaxy Demo Kit ALTERA Development Kit Galaxy Development Kit

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Introduction to Altera Devices

2010 Altera CorporationConfidential

Programmable Logic FamiliesStructured ASIC

HardCopy IV HardCopy III HardCopy II Stratix IV E ,Stratix III L&E, Stratix II Cyclone IV E ,Cyclone III, Cyclone II

High & medium density FPGAs Low-cost FPGAs FPGAs w/ clock data recoveryStratix IV GT&GX, Stratix IIGX, StratixGX Arria II GX, Arria GX, Cyclone IV GX

CPLDs- MAX II , MAX II Z - MAX 3000 & MAX7000S

Configuration devices

AS Mode Serial (EPCS) & PS Mode enhanced (EPC) Cyclone III LS

Design Security Feature

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ALTERA CPLDs

2010 Altera CorporationConfidential

MAX 3000A & MAX 7000S Family OverviewParameterEPM3032A

MAX 3000AEPM7064S EPM3064A EPM3128A EPM3256A EPM3512A

MAX 7000SEPM7160S EPM7192S EPM7128S EPM7256S 5000 256 164 7.5 3.9 4.7

Useable Gates Macrocells Maximum User I/O Pins tPD (ns) fCNT (MHz) tSU (ns) tCO1 (ns)

600 1,250 2,500 32 34 4.5 227 2.9 3.0 64 66 4.5 222 2.8 3.1 128 96 5.0 192 3.3 3.4

5,000 10,000 1,250 2,500 256 158 7.5 127 5.2 4.8 512 208 7.5 116 5.6 4.7 64 68 5 128 100 6

3200 160 104 6

3750 192 124 7.5

175.4 147.1 149.3 125.0 128.2 2.9 3.2 3.4 4 3.4 3.9 4.1 4.7

EPM7032S End Of Life 2010 Altera CorporationConfidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Complete Voltage Portfolio5.0 VMAX 7000SPerformance Leader Feature Leader Wide Range of Package Offerings Industrial-Grade Offerings

3.3 VMAX IIPrice Leader

MultiVolt Core and I/O Operation

MAX II 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS Base on each I/O Bank

MAX 3000APrice Leader

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MAX 3000A Device Block Diagram

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MAX Macrocell

Global Global Clear Clock

Parallel Logic Expanders (from other MCs)

7000 has two Global Clock

Programmable RegisterRegister Bypass PRn D Q ENA CLRn

ProductTerm Select Matrix

to I/O Control Block

Clear Select

VCC

36 Programmable Interconnect 2010 Altera CorporationConfidential Signals9

Shared Logic Expanders 16 Expander Product Terms

Clock/ Enable to PIA Select

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MAX II Device Family OverviewDevice characteristics

Non-volatile, instant-on programmable logic TSMC 0.18-m, 6-lm flash process 240 to 2,210 logic elements (LEs) 80 to 272 user I/O pins Lowest cost per I/O pin Low power consumption Fast performance High-density

Key benefits

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MAX II: The Lowest-Cost CPLD EverNew Logic Architecture 1/2 the Cost 1/10 the Power Consumption 2X the Performance 4X the Density

Non-Volatile, Instant-On Supports 3.3-, 2.5- & 1.8-V Supply Voltages

Breakthrough Technology to Expand the Market 2010 Altera CorporationConfidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Flexible Supply VoltageOn-Chip Voltage Regulator Accepts 3.3-, 2.5- & 1.8-V Supply Inputs Internally Converted to 1.8V Core Voltage1.8 V 2.5 V 3.3 V

Convenience of 3.3 V with the Power & Performance of 1.8 V 2010 Altera CorporationConfidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

MAX II Device Family

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MAX II Packaging and User I/O Pins

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MAX II Family Package Size

F256 1.0mm FBGA 17x17mm

T100 0.5mm TQFP 16x16mm

Partial M100 0.5mm MBGA 6x6mm

2010 Altera CorporationConfidential

Partial M256 0.5mm MBGA 11x11mm

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MAX II Architecture

Logic Elements (LEs) Staggered I/O Pads

Configuration Flash Memory JTAG & Control Circuitry User Flash Memory ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. 2010 Altera CorporationConfidential and Altera marks in and outside the U.S.

MAX II Performance

Delay for Best-Case I/O Placement

tPD2

tPD1

Delay for WorstCase I/O Placement: (Full Diagonal Path Across Device)

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LE Normal Modesload sclear aload

addnsub

Register Chain Row, Column & Direct Link Routing Local Routing LUT Chain Register Chain

Reg Reg data1 data2 data3 cin data4 4-Input 4-Input LUT LUT clock ena aclr DEV_CLRn

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User Flash MemoryFeature Flash memory

storage bank 8,192 bits per device Interface to SPI, parallel, I2C or proprietary buses

Industry First!

Applications Store revision & serial

number data Store boot-up & configuration data

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MAX & MAX II ComparisonParameter/FeatureProcess Technology Logic Architecture Density Range Routing Architecture On-Chip Flash Memory Maximum User I/O Pins Supply Voltage I/O Voltages Global Clock Networks Output Enables (OEs) Schmitt Triggers 2010 Altera CorporationConfidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

MAX0.3-um EEPROM Product Term 32 to 512 Macrocells Global None 212 5.0 V, 3.3 V, 2.5 V 5.0 V, 3.3 V, 2.5 V, 1.8 V 2 per Device 6 to 10 per Device None

MAX II0.18-um Flash Look-Up Table (LUT) 128 to 2210 Macrocells (240 to 2,210 LEs) Row & Column 8 Kbits 272 3.3 V/2.5 V, 1.8 V 3.3 V, 2.5 V, 1.8 V, 1.5 V 4 per Device 1 per I/O Pin 1 per I/O Pin

ALTERA FPGA Cyclone series

2010 Altera CorporationConfidential

Cyclone IV GX: Lowest Cost, Lowest Power FPGAs with Transceivers Lowest CostHigh functionality Up to 150K Logic Elements Up to 6.5 Mb RAM, 360 Multipliers Up to 8 integrated 3.125Gbps transceivers

Low Power Functionality

Lowest system cost Smallest density FPGA with transceivers Integrated Hard IP PCIe x1, x2, x4 endpoint and rootport Transceivers built from ground up for low cost Requires only two power supplies Wirebond packages

Low power 60nm Low power process PCI to GbE bridge for