20080502 software verification_sharygina_lecture04

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USI-CMU summer school 2007 Natasha Sharygina 1 z Deadlock Detection Outline

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Transcript of 20080502 software verification_sharygina_lecture04

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USI-CMU summer school 2007 Natasha Sharygina 1

Deadlock Detection

Outline

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Actual Goal

Deadlock for concurrent message-passing blocking C programs

Tackle complexity using automated abstraction and compositional reasoning

Obtain precise answers using automated iterativeabstraction refinement

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For this part of the lecture

Focus on finite state machinesLabeled transition systems (LTSs)

Parallel composition of state machinesSynchronous communicationAsynchronous executionNatural for modeling blocking message-passing C programs

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Finite LTSP = ( Q , I , Σ , T )Q ≡ non-empty set of statesI ∈ Q ≡ initial stateΣ ≡ set of actions ≡ alphabetT ⊆ Q × Σ × Q ≡ transition relation

a

a

b

c d

e

PΣ(P) = {a,b,c,d,e,f}

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Concurrency

Components communicate by handshaking (synchronizing) over shared actionsElse proceed independently (asynchronously)Essentially CSP semantics

Composition of A1 & A2 ≡ A1 || A2

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Deadlock

1 2 3 4a b c

1’ 2’ 3’ 4’a c b

M2 Σ = {a,b,c,d}M1 Σ = {a,b,c,d}

2,2’a

M1 k M2

Deadlock

d d

1,1’

Deadlock⇔ a reachable state cannot perform any actions at all

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Deadlock and Composition

a b

c

M1

b c

c

M2

Deadlock

c

M1 || M2

No Deadlock

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Deadlock and Composition

a

b

M1

b

a

M1

No Deadlock

M1 || M2

Deadlock

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A

Conservative Abstraction

1

2 3

4 6

a b

c f

P

[2,3]

[4,5] [6,7]

[1]

5 7

ed

a b

c d fe

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Conservative Abstraction

Every trace of P is a trace of APreserves safety properties: A ² φ⇒ P ² φA over-approximates what P can do

Some traces of A may not be traces of PMay yield spurious counterexamples - h a, e i

Eliminated via abstraction refinementSplitting some clusters in smaller onesRefinement can be automated

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A

Original Abstraction

1

2 3

4 6

a b

c f

P

[2,3]

[4,5] [6,7]

[1]

5 7

ed

a b

c d fe

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A

Refined Abstraction

1

2 3

4 6

a b

c f

P

[4,5] [6,7]

[1]

5 7

ed

a b

c d

[2] [3]

e f

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Deadlock : Problem

Deadlock is not preserved by abstraction

1 2a 3b

M1

1’ 2’b 3’a

M2

[1,2,3]a,b [1’,2’,3’]a,b

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Deadlock Detection : Insight

Deadlock ⇔ a reachable state cannot perform any actions at all

Deadlock depends on the set of actions that a reachable state cannot perform

In order to preserve deadlock A must over-approximate not just what P can do but also what Prefuses

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Refusal & Deadlock

Ref(s) = set of actions s cannot perform

M deadlocks iff there is a reachable state s such that Ref(s) = Σ

Denote by DLock(M)

Ref([s1 .. sn]) = Ref(s1) Å .. Å Ref(sn)

1 2a 3b{b} {a} {a,b} { }

[1,2,3]a,b

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Abstract Refusal

AR([s1 .. sn]) = Ref(s1) ∪ .. ∪ Ref(sn)

AR([M1] .. [Mn]) = AR([M1]) ∪ .. ∪ AR([Mn])

[a,b]

1 2a 3b{b} {a} {a,b}

[1,2,3]a,b

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Abstract Deadlock

M abstractly deadlocks iff there is a reachable state s such that AR(s) = Σ

Denote by ADLock(M)

¬ ADLock([M1] || .. || [Mn])⇒

¬ DLock(M1 || .. || Mn)

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Iterative Deadlock Detection

1 2a 3b 1’ 2’b 3’a

[1,2,3]a,b [1’,2’,3’]a,b

[a,b] [a,b]

[1,2,3],[1’,2’,3’]

[a,b]Counterexample toAbstractDeadlock

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Counterexample Validation

[1,2,3],[1’,2’,3’]

[a,b]

[1,2,3]

[a,b]

×1 2a 3b

{b} {a} {a,b}

[1’,2’,3’]

[a,b]

1’ 2’b 3’a{a} {b} {a,b}

×

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Refinement

1 2a 3b 1’ 2’b 3’a

1 2a 3b

[1]

b

[1’,2’,3’]a,b[2,3]a

[b] [a,b] [a,b]

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Counterexample Validation

[1],[1’,2’,3’]

[a,b]

[1]

[b]

1 2a 3b{b} {a} {a,b}

[1’,2’,3’]

[a,b]

1’ 2’b 3’a{a} {b} {a,b}

×

Another spurious counterexample

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Refinement

1 2a 3b 1’ 2’b 3’a

[1]

b

1 2a 3b

[2,3]a

1’ 2’b 3’a

[b] [a,b]

[1’]

a

[2’,3’]b[a,b][a]

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Counterexample Validation

[1],[1’]

[a,b]

[1’]

[a]

1’ 2’b 3’a{a} {b} {a,b}

Real Deadlock Detected1 2a 3b

{b} {a} {a,b}

[1]

[b]

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☺☺

Iterative Deadlock

No AbstractDeadlock?

Yes

System OKAbstraction

Model

CounterexampleValid?

System

AbstractionGuidance

Yes

No

Counterexample

AbstractionRefinement

ImprovedAbstractionGuidance

No

SpuriousCounterexample

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Case Studies

MicroC/OS-IIReal-time OS for embedded applicationsWidely used (cell phones, medical devices, routers, washing machines…)6000+ LOC

•ABB IPC Module–Deployed by a world leader in robotics–15000+ LOC–4 components–Over 30 billion states after predicate abstraction

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Results

Plain IterDeadlock

St

ABB * * 162 1973 861 1446 33.3

SSL 25731 44 43.5 16 16 31.9 40.8

μCD-3 * * 58.6 4930 120 221.8 15

μCN-6 * * 219.3 71875 44 813 30.8

DPN-6 * * 203 62426 48 831 26.1

DPD-10 38268 87.6 17.3 44493 51 755 18.4

Name St T Mem It T Mem

* indicates out of time limit (1500s)

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Results

Plain IterDeadlock

St

ABB * * 162 1973 861 1446 33.3

SSL 25731 44 43.5 16 16 31.9 40.8

μCD-3 * * 58.6 4930 120 221.8 15

μCN-6 * * 219.3 71875 44 813 30.8

DPN-6 * * 203 62426 48 831 26.1

DPD-10 38268 87.6 17.3 44493 51 755 18.4

Name St T Mem It T Mem

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References Sagar Chaki, Edmund M. Clarke, Joël Ouaknine, Natasha Sharygina: Concurrent software verification with states, events, and deadlocks. Formal Aspects of Computing 17(4): 461-483 (2005)

Chiara Braghin, Natasha Sharygina, Katerina Barone-Adesi: Automated Verification of Security Policies in Mobile Code, In Proc. of Integrated Formal Methods 2007 conf., LNCS 4591:37 - 54 (2007)