20050712 MB91403 HARDWARE MANUAL - Fujitsu · CONTROLLER MANUAL MB91403 HARDWARE MANUAL...

FUJITSU

CONTROLLER MANUAL

MB91403HARDWARE MANUAL

Preliminary-1

20050712

FUJITSU LIMITED

MB91430HARDWARE MANUAL

Chapter1OVERVIEW

Overview, Features

1

Chapter1 OVERVIEW

1.1 Overview

What is the MB91403?The MB91403 is a one-chip network security LSI with a Fujitsu 32bit RISC microcom-

puter: FR as a CPU core together with a 10/100Base-T MAC Controller and encryption

and authentication macros as well as a large-capacity ROM/RAM. As a feature of this LSI,

the MAC Controller has a packet filtering function to alleviate the CPU load encountered in

response to ever-increasing packet filtering. Also, the encryption and authentication process-

ing macro realizes high speed processing of the encryption and authentication processing

communications (IKE/IPsec/SSL), which will be even more necessary in the future.

Equipped with more features such as an External IF that enables high-speed data communi-

cations with wide-ranging external hosts as well as an external memory IF, I2C IF, general-

purpose IO port, the MB91403 will find various applications.

Note that FR is used as the core but its chip select function is limited. For more information,

see "1.6 Address map".

2

Chapter1 OVERVIEW

1.2 Features

FR Core• Fujitsu FR series instruction compatible 32-bit RISC core, 5-stage pipeline, executing one

instruction per cycle

• Instruction cache: 4KB, data RAM: 8KB

• Operating frequency: Max. 33MHz

• DMAC: 5ch, UART: 2ch, 16-bit reload timer: 3ch, peripheral functions of an interrupt

controller mounted

*For more information, see Chapter 2, "FR Core Functions."

ETHERNET MAC INTERFACE

Packet filtering function

The MB91403 provides the packet filtering function in L3/L4 and allows you to select to pass

or not to pass data if you set addresses (IP and MAC). It also provides a function of receiving

data not only from its own address but also from registered multicast addresses.

• Built-in 10/100M MAC compliant to EEE802.3

• MII interface (for full and half duplex operations)

• SMI interface for PHY device control

<Caution>

Layer 3/4 filtering function (hardware-based).

This function allows you to decide to pass or drop a packet when it has a matchingcondition, i.e., either the IP address in Layer 3 (Network Layer) or the TCP/UDP portnumber in Layer 4 (Transport Layer).

Encryption and authentication processing functionThe MB91403 provides hardware-based support for DES/3DES/AES, private-key encryption

systems that perform encryption and decryption of data as well as HMAC-MD5/HMAC-SHA1

used for data authentication. Compared with software-only systems, this system offers a 30 to

40 times better performance.

Furthermore, it has a built-in accelerator function that executes on a hardware basis processing

frequently used in a public-key encryption system or other such algorithm that imposes a sig-

nificantly heavy load in software-based processing. Compared with software-based processing

time, this feature offers about 100 times higher speed.

With these functions, the MB91403 supports IPsec, a security function used in the Network

Layer of the Internet. The encryption and authentication functions can be easily used as func-

tions by host applications and can also be used to speed up encryption applications such as

RSA and SSL.

• Support of ECB/CBC mode of DES/3DES/AES(Key Length=128/192/256bit)

• Support of MD5/SHA-1/HMAC-MD5/HMAC-SHA-1 modes

3

Chapter1 OVERVIEW

• Support of DH group: 1(MODP 768bit)/2(1024bit)

EXTERNAL INTERFACE

External interface with a communication function

The MB91403 is equipped with a high-capacity send and receive FIFO buffer that realizes

massive data send and receive as well as a communication register. With a 1.5-kilobyte buffer

for reception and a 1.5-kilobyte buffer for sending, the device has a function of processing data

while storing it in the buffer and a host function that stops receiving data when the buffer is

full.

This feature enables performing communication control even during data send and receive in

order to alleviate CPU load and realize efficient communications.

• 8/16-bit data port

• Send and receive data port control function

• Transfer rate: 89Mbps(MAX.)

* When the interface is not used, it can be used as a general-purpose port (Port B).

GENERAL PURPOSE IOThe 4-bit general-purpose IO port (Port A) and the external interface can be used as a general-

purpose IO port of 22 bits at the maximum (Port B).

• The input-output settings can be made for each bit.

• When the input settings are made, a signal change can be used to generate an interrupt (only

on Port A).

MEMORY INTERFACEThe memory interface can be connected with various external memory and IO ports.

• Support of ROM/RAM/SDRAM/FCRAM IF

• 2-chip select signal

• 8/16-bit data bus

• Address space settings

[ROM/RAM setting] An address area from 64Kbyte to 8Mbyte can be set.

[SDRAM/FCRAM setting] An address area from 64Kbyte to 128Mbyte can be set.

I2C INTERFACEThe I2C Interface is a serial interface that supports Inter IC Bus advocated by Philips.

• Master/slave send and receive function

• Supports standard mode (Max.100Kbps) and high-speed mode (Max.400Kbps).

High-capacity ROM/RAMA high-capacity ROM/RAM is embedded in the chip. In addition to the main ROM for user

programs, the chip has a ROM storing serial download programs.

• ROM: 256Kbyte (for user programs) + 2Kbyte (for serial download programs)

• RAM: 64Kbyte

4

Chapter1 OVERVIEW

Clock• Built-in crystal oscillation circuit

• Built-in PLL

• Input clock: 10MHz to 50MHz

* For the combinations of input clocks and PLL multiplication modes, see Chapter 2,

"Guide to FR Core Functions."

LSI overall specifications• 0.18µCMOS Al5-layer technology

• LQFP 144-pin package

• 3.3-V single-power specification

• Operating frequency: CPU/Peripheral modules (external buses) - 33MHz (MAX)

Built-in resources of FR core - 16.5MHz (MAX)

Note: To enable 100Base communications using the MAC IF of a peripheral module, set

the operating frequency of the peripheral module to higher than 25MHz. (33MHz

greater-than or equal to peripheral module operating frequency > 25MHz)

Power consumption: 250mW @ 33MHz (MAX)

5

Chapter1 OVERVIEW

1.3 Internal block diagram

1.3.1 Block diagram

FR core: CPU, U-Timer, UART, Timer, Interrupt Controller, DMAC, Bit

Search, external interrupt, memory_IF, data-RAM, cache, bus

controller

Peripheral resources: LAN, External_IF, Encryption/Authentication Macro, PIO, I2C, Built-

in ROM, Built-in RAM (Peripheral resources are connected to the bus

of the bus controller.)

E

B

T

I2C Bus

PORT

External IF/PORT

MB91403

8/16bit bus

Encryption/Authentication macro

DES/3DES/AES

HMAC-MD5/SHA1

DH

ROM256KByte

Crystal oscillator/external clock

RAM64KByte

MU

X

GPIO

External IF

10/100 EthernetMAC Controller

L2/L3/L4 Filtering

I-Cache(4KB)

DMACR

Serial IF(2ch)

DSU IFINT(2ch)

D-RAM(8KB)

OSC

DSUFR CORE

I2C IF

CLKCont

PLL

UART

INT

Timer

PHY

ROM/FLASH

SRAM/SDRAM

6

Chapter1 OVERVIEW

1.4 Input-Output Pins

1.4.1 Signal lines

1.4.2 Pin descriptionThis section describes the list of pin functions.

Format exampleThe pin function list uses the conventions shown in the following format example:

SYSTEM MEMORY IF

IN TXI 1 A[22:0] 23INT[7:6] 2 D[31:16] 16MDI[2:0] 3 RDX 1

OSCILLATOR WRX[1:0] 2X0 1 CSX[7:6] 2X1 1 WEX 1

ICE MCLKE 1BREAKI 1 SRASX 1ICS[2:0] 3 SCASX 1

ICLK 1 MCLKO 1ICD[3:0] 4 RDY 1

TEST I2C IFTEST[2:0] 3 SDA 1

XTEST 1 SCL 1SM 1 EXTERNAL IF/GPIO(Port B)

VPD 1 EXCSX/PB[21] 1 UART EXA/PB[20] 1

SIN[1:0] 2 EXRDX/PB[19] 1SOUT[1:0] 2 EXWRX/PB[18] 1

SCK[1:0] 2 DREQRX/PB[17] 1 ETHERNET MAC IF DREQTX/PB[16] 1

TXCLK 1 EXD[15:0]/PB[15:0] 16TXD[3:0] 4 GPIO (Port A)

TXEN 1 PA[3:0] 4RXCLK 1RXER 1

RXD[3:0] 4RXDV 1

RXCRS 1 VDD/GNDCOL 1 VCC 10

MDCLK 1 VSS 9MDIO 1 C 1

MB91403

LQFP-144

Signal lines 124 Pin

Power supply/GND

20 Pin

N.C. 0 Pin

Pin name

Pin no. Polarity I/O Circuit Function/application

Pin 1 1 Positive OUT C The general functions and applications of this pin are described here.

7

Chapter1 OVERVIEW

Pin name

Shows the external pin name.

Pin no.

Shows the package pin number of the target external pin.

Polarity

Shows the polarity at which the input or output pin becomes active.Throughout this specifica-

tion, an input level is indicated either as "1" or "0" and an output level is indicated either as "H"

or "L".

"Positive": Input level of "1" and output level of "H"

"Negative": Input level of "0" and output level of "L"

I/O

Shows the input or output direction of a signal in reference to this LSI.

"IN" : Shows that this pin is an input pin of this LSI.

"OUT" : Shows that this pin is an output pin of this LSI.

"I/O" : Shows that this pin is an input-output pin of this LSI.

Circuit

Shows the circuit type of the I/O buffer.

Function/application

Shows the outline of functions of the target external pin.

CautionUnused input pins should be made inactive and unused output pins should be left open.

Pin 2 8 Negative I/O D The general functions and applications of this pin are described here.

Pin 3 2 Positive IN A The general functions and applications of this pin are described here.

Pin name

Pin no. Polarity I/O Circuit Function/application

8

Chapter1 OVERVIEW

1.4.2.1 SYSTEM (6 pins)

1.4.2.2 OSCILLATOR (2 pins)

1.4.2.3 ICE (9 pins)

Pin name Pin no. Polarity I/O Circuit Function/application

INITXI 7 Negative IN A

Setting initialization reset inputThis pin inputs a signal to initialize the settings of the LSI.When turning on the power supply, apply "0" level to the pin until the power supply and the clock signal input to the X 0 pin becomes stable.If INITXI is asserted "0", all built-in registers and external pins are initialized.

INT[7:6] 8,9 Negative (default setting)

IN A

External interrupt inputThese pins input an external interrupt request signal.For external interrupt detection, set the ENIR, EIRR, and ELVR registers of the FR core.

MD I[2:0] 17,15,14 - IN A

Mode pinThese pins determine the operation mode of the LSI.Always set this bit to "00 1".


X0 11 - IN H

Crystal oscillation/external clock input This is a common input pin of X0 11 -IN H crystal oscillation cell and external clock. 10MHz to 50MHz frequency can be input.

X1 13 - I/O HCrystal oscillation outputOutput pin of X1 13 -I/O H crystal oscillation cell.


BREAKI 16 Positive IN BEmulator break requestThis pin inputs the emulator break request when an ICE is connected.

ICS[2:0] 24,22,20 Positive OUT CEmulator chip statusThese pins output the emulator status when an ICE is connected.

ICLK 19 - OUT D-3Emulator clockThis pin serves as the emulator clock pin when an ICE is connected.

ICD[3:0] 28 - 25 - I/O EEmulator dataThese pins serve as the emulator data bus when an ICE is connected.

9

Chapter1 OVERVIEW

1.4.2.4 TEST (6 pins)

1.4.2.5 UART (6 pins)


TEST [2:0] 133 - 135 - IN A

Test pinUse this pin to select the BOOT ROM. For more information, see Section 1.7.5, "Boot ROM selection."

XTEST 5 - IN ASCAN test pinSCAN test pin. Normally, fix this pin to "0".

SM 6 - IN ASCAN mode pinSCAN mode pin. Normally, fix this pin to "0".

VPD 136 - IN AThrough current prevention pinNormally, fix this pin to "0".


SIN [1:0] 29,30 - IN ASerial data inputSerial data input pin of built-in UART of the FR core.

SOUT [1:0] 31,32 - OUT CSerial data outputSerial data output pin of built-in UART of the FR core.

SCK [1:0] 34,35 - I/O D-2Serial clock input-outputSerial clock input-output pin of built-in UART of the FR core.

10

Chapter1 OVERVIEW

1.4.2.6 MEMORY IF (50 pins)


A [22:0] 37 - 43, 45 - 60

- OUT D-1Address output23-bit address signal pins.

D [31:16] 73 - 88 - I/O D-1Data input-output16-bit data input-output signal pins.

CSX [7:6] 64,63 Negative OUT D-2

Chip select output2-bit chip select signal pin.Outputs "L" level signals during access to external memory.

RDX 61 Negative OUT D-2Read strobe outputRead strobe signal pin.Outputs "L" level signals during read access.

WRX [1:0] 71,72 Negative OUT D-2

Write byte strobe outputWrite byte strobe signal pin.Outputs "L" level signals during write access.* Serves as DQM on the SDRAM/FCRAM area.

WEX 69 Negative OUT D-2

Write enable outputWrite enable signal pin.Outputs "L" level signals during write access regardless of the bus size.* Serves as a write-strobe pin on SDRAM/FCRAM.

MCLKE 65 Positive OUT D-2Memory clock enable output* Serves as CKE on the SDRAM/FCRAM area.

SRASX 67 Negative OUT D-2RAS signal output* Serves as RAS on the SDRAM/FCRAM area.

SCASX 68 Negative OUT D-2CAS signal output* Serves as CAS on the SDRAM/FCRAM area.

MCLKO 66 - OUT CMemory clock outputOutputs the same frequency clock as the internal bus.

RDY 36 Positive IN AExternal RDY inputWhen the external bus cycle is not completed, inputting "0" extends the bus cycle.

11

Chapter1 OVERVIEW

1.4.2.7 ETHERNET MAC IF (17 pins)

1.4.2.8 I2C IF (2 pins)


RXCLK 2 - IN AInput of clock for receptionMII sync signal during reception. The frequency is 2.5MHz at 10Mbps and 25MHz at 100Mbps.

RXER 139 Positive IN A

Receive error InputWhen "1" is input from the PHY device during reception, it is recognized that the reception packet has an error.

RXDV 140 Positive IN AReceive data effective inputIt is recognized that receive data is effective.

RXCRS 141 Positive IN ACarrier sense inputIt is recognized that either reception or sending is in progress.

RXD[3:0] 1,144 -

142 - IN A

Receive data Input4-bit data input from PHY device.

COL 3 Positive IN ACollision detection inputWhen TXEN signal is active and this signal is "1", a collision is recognized. Otherwise, it is ignored.

TXCLK 4 - IN AInput of send clockMII sync signal during sending. The frequency is 2.5MHz at 10Mbps and 25MHz at 100Mbps.

TXEN 124 Positive OUT C

Send enable outputIndicates that effective data is on the TXD bus. This signal is output in synchronization with TXCLK.

TXD[3:0] 125,127 -

129 - OUT C

Send data output4-bit data bus for sending to PHY device. This signal is output in synchronization with TXCLK.

MDCLK 130 - OUT CSMI clock outputSMI IF clock pin. Connect this pin to SMI clock input pin of PHY device.

MDIO 132 - I/O D-2SMI data input-outputSMI data input-output pin. Connect this pin to SMI data pin of PHY device.


SDA 121 - I/O GSerial data line input-outputI2C bus data input-output pin.

SCL 122 - I/O GSerial clock line input-outputI2C bus block input-output pin.

12

Chapter1 OVERVIEW

1.4.2.9 EXTERNAL IF /GPIO (Port B) (22 pins)

1.4.3 GPIO(Port A) (4pins)

1.4.4 Power supply/GND (20 pins)


EXCSX/PB[21]

109 Negative IN

F

External chip select inputInput pin for chip select signals from external host.

- I/O General-purpose input-output port.

EXA/PB[20]

110 -

INF

External address inputInput pin for address signals from external host."0": Register select"1": FIFO data select

I/O General-purpose input-output port.

EXRDX/PB[19]

111 Negative IN

F

External read strobe inputInput pin for read strobe signals from external host.


EXWRX/PB[18]

112 Negative IN

F

External write strobe inputInput pin for write strobe signals from external host.


DREQRX/PB[17]

114 Negative OUT

F

External receive data request outputIndicates that data can be written to the receive FIFO.


DREQTX/PB[16]

115 Negative OUT

F

External send data request outputIndicates that there is data in the send register and the send FIFO.


EXD[15:0]/PB[15:0]

89,91 - 93,95 -

98,100 - 103,105 -

108

- I/O F

External data input-outputInput-output pins for data bus bits [15:0] with an external host.

General-purpose input-output port.


PA [3:0] 117 - 120 - I/O F

GPIO input-outputInput-output port. When the input signal settings are made, a signal change can be used to generate an interrupt.

Pin name Pin no. I/O Function/application

VDDE10,12,21,33,64,90,

99,113,123,131 Power supply

3.3V power supply pins. Use all of these pins at the same potential.

VSS18,23,44,70,94, 104,116,126,138

GND GND pins. Use all of these pins at the same potential.

C 137 OUT Pin for connecting a capacitor for the built-in regulator.

13

Chapter1 OVERVIEW

1.4.5 Input-output circuit types

A CMOS level input

BCMOS level input with pulldownPullup resistance = about 33KΩ (TYP)

CCMOS level outputIOL = 4mA

D-1CMOS level outputCMOS level inputIOL = 2mA


Digital input

Digital input

Digital output

Digital output

Digital input

Digital output

Digital output

Digital input

Digital output

Digital output

14

Chapter1 OVERVIEW


E

With pulldownCMOS level outputCMOS level inputPulldown resistance = about 33KΩ (TYP)IOL = 4mA

F

With pullupCMOS level outputCMOS level inputPullup resistance = about 33KΩ (TYP)IOL = 4mA

G

I2C Bus Fast Mode I/O BufferCMOS level outputCMOS Schmitt trigger inputIOL = 4mA

Digital input

Digital output

Digital output

Digital input

Digital output

Digital output

Digital input

Digital output

Digital output

Digital input

Digital output

Digital output

15

Chapter1 OVERVIEW

HOscillation circuitFeedback resistance of 1MΩ

Oscillation output

Built-in feedback resistorX0

X1

16

Chapter1 OVERVIEW

1.4.6 Pin Assignment Diagram

1.4.7 Pin number table

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

1 RXD3 37 A22 73 D31 109 EXCSX

2 RXCLK 38 A21 74 D30 110 EXA

3 COL 39 A20 75 D29 111 EXRDX

4 TXCLK 40 A19 76 D28 112 EXWRX

5 XTEST 41 A18 77 D27 113 VDDE

6 SM 42 A17 78 D26 114 DREQRX

7 INITXI 43 A16 79 D25 115 DREQTX

8 INT7 44 VSS 80 D24 116 VSS

9 INT6 45 A15 81 D23 117 PA3

10 VDDE 46 A14 82 D22 118 PA2

EX

D0/

PB

0

EX

D1/

PB

1

EX

D2/

PB

2

EX

D3/

PB

3

VS

S

EX

D4/

PB

4

EX

D5/

PB

5

EX

D6/

PB

6

EX

D7/

PB

7

VD

DE

EX

D8/

PB

8

EX

D9/

PB

9

EX

D10

/PB

10

EX

D11

/PB

11

VS

S

EX

D12

/PB

12

EX

D13

/PB

13

EX

D14

/PB

14

VD

DE

EX

D15

/PB

15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

EXCSX/PB21 109 72 WRX1EXA/PB20 110 71 WRX0

EXRDX/PB19 111 70 VSSEXWRX/PB18 112 69 WEX

VDDE 113 68 SCASXDREQRX/PB17 114 67 SRASXDREQTX/PB16 115 66 MCLKO

VSS 116 65 MCLKEPA3 117 64 VDDEPA2 118 63 CSX6PA1 119 62 CSX7PA0 120 61 RDXSDA 121 60 A0SCL 122 59 A1

VDDE 123 58 A2TXEN 124 57 A3TXD3 125 56 A4

VSS 126 55 A5TXD2 127 54 A6TXD1 128 53 A7TXD0 129 52 A8

MDCLK 130 51 A9VDDE 131 50 A10MDIO 132 49 A11

TEST2 133 48 A12TEST1 134 47 A13TEST0 135 46 A14

VPD 136 45 A15C 137 44 VSS

VSS 138 43 A16RXER 139 42 A17RXDV 140 41 A18

RXCRS 141 40 A19RXD0 142 39 A20RXD1 143 38 A21RXD2 144 37 A22

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

RX

D3

RX

CLK

CO

L

TX

CLK

XT

ES

T

SM

INIT

XI

INT

7

INT

6

VD

DE

X0

VD

DE

X1

MD

I0

MD

I1

MD

I2

VS

S

ICLK

ICS

0

VD

DE

ICS

1

VS

S

ICS

2

ICD

0

ICD

1

ICD

2

ICD

3

SIN

1

SIN

0

SO

UT

1

SO

UT

0

VD

DE

SC

K1

SC

K0

RD

Y

108 100102104106

MB91403(Top View)

101103105107

17

Chapter1 OVERVIEW

11 X0 47 A13 83 D21 119 PA1

12 VDDE 48 A12 84 D20 120 PA0

13 X1 49 A11 85 D19 121 SDA

14 MDI0 50 A10 86 D18 122 SCL

15 MDI1 51 A9 87 D17 123 VDDE

16 BREAKI 52 A8 88 D16 124 TXEN

17 MDI2 53 A7 89 EXD15 125 TXD3

18 VSS 54 A6 90 VDDE 126 VSS

19 ICLK 55 A5 91 EXD14 127 TXD2

20 ICS0 56 A4 92 EXD13 128 TXD1

21 VDDE 57 A3 93 EXD12 129 TXD0

22 ICS1 58 A2 94 VSS 130 MDCLK

23 VSS 59 A1 95 EXD11 131 VDDE

24 ICS2 60 A0 96 EXD10 132 MDIO

25 ICD0 61 RDX 97 EXD9 133 TEST2

26 ICD1 62 CSX7 98 EXD8 134 TEST1

27 ICD2 63 CSX6 99 VDDE 135 TEST0

28 ICD3 64 VDDE 100 EXD7 136 VPD

29 SIN1 65 MCLKE 101 EXD6 137 C

30 SIN0 66 MCLKO 102 EXD5 138 VSS

31 SOUT1 67 SRASX 103 EXD4 139 RXER

32 SOUT0 68 SCASX 104 VSS 140 RXDV

33 VDDE 69 WEX 105 EXD3 141 RXCRS

34 SCK1 70 VSS 106 EXD2 142 RXD0

35 SCK0 71 WRX0 107 EXD1 143 RXD1

36 RDY 72 WRX1 108 EXD0 144 RXD2

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

18

Chapter1 OVERVIEW

1.4.8 Outside dimensions

Plastic LQFP, 144-pin Lead pitch 0.50mm

Package width by package length

20.0 x 20.0mm

Lead type Gull-wing

Sealing method Plastic mold

Mounting height 1.70mm MAX

Weight 1.20g

Code (for your reference)

P-LFQFP144-20×20-0.50

Plastic LQFP, 144-pin(FPT-144P-M08)

(FPT-144P-M08)

C 2003 FUJITSU LIMITED F176006S-c-4-6Unit: mm (inches)Note: Values in parentheses are reference values.

Note 1: A dimension with an asterisk do not include resin residue.* The resin residue is +0.25 (.010) on one side at the maximum.Note 2: The width and thickness of a pin include the thickness of plating.Note 3: The width of a pin does not include tie bar cut residue.

19

Chapter1 OVERVIEW

1.5 Precaution on use

1.5.1 Preventing latch-upLatch-up may occur if a higher voltage than VDDE or a lower voltage than VSS is applied to

the input pin or output pin of a CMOS IC or if a higher voltage than the ratings is applied to

between VDDE to VSS. If latch-up occurs, the supply current increases rapidly, sometimes

resulting in thermal breakdown of the device. Use meticulous care not to let any voltage

exceed the maximum rating during device operation.

1.5.2 Treatment of pins

1.5.2.1 Treatment of unused pinsLeaving unused input pins open may result in a malfunction. Apply pullup or pulldown treat-

ment to such pins.

1.5.2.2 Treatment of output pinsA large current may flow to an output pin if it is short-circuited with the power supply or other

output pin or if it is connected to a large volume load. Leaving the output pin that way for an

extended period of time degrades the device. Use meticulous care not to let any current exceed

the maximum rating during device operation.

1.5.2.3 About mode (MDI[3:0]) pins and test (TEST[2:0], XTEST, SM, VPD) pins

Connect these pins directly to VDDE or VSS. To prevent the device from entering test mode

accidentally due to noise, minimize the lengths of the patterns between individual mode pins

and VDDE or VSS on the PC board and connect them with as low an impedance as possible.

1.5.2.4 About power supply pinsThe power pins should be connected to VDDE and VSS of this device at the lowest possible

impedance from the power supply source. It is also advisable to connect a ceramic capacitor of

approximately 0.1 µF as a bypass capacitor between VDDE and VSS near this device.

1.5.2.5 Crystal oscillation circuitNoise near the X0 and X1 pins may cause the MB91403 to malfunction. Design the PC board

so that the X0 and X1 pins, the crystal oscillator, and the bypass capacitor to ground are

located as close to the device as possible.

It is strongly recommended to design the PC board artwork with the X0 and X1 pins sur-

rounded by ground plane because stable operation can be expected with such a layout.

1.5.2.6 Connection specification of MB91403 and ICEThis section describes the recommended type and circuit composition, designing precautions,

20

Chapter1 OVERVIEW

and wiring regulations for the emulator interface connector to be mounted on a user system.

To use a flat cable, it is recommended that you select a combination of connectors with

housing.

Recommended connector type

Circuit compositionWhen an ICE is connected, put a damping resistor of 15Ω in series with the ICLK signal to

ensure stability of operation. When you design a PC board, mount the resistor near the ICLKpin of this LSI.

*1: Use a wiring pattern with a higher capacity than the current rating.

*2: See "Precaution on designing" for more information on a switch circuit, which may become necessary.

*3: Mount the resistor near the ICLK pin of the MB91403.

Attached cable

Part number Remarks

FPC cable FH10A-30S-1SH (Maker: Hirose Electric Co., Ltd.) With latch

UVcc

ICLK

ICS[2:0]

ICD[3:0]

BREAK

RST

XRSTIN

FR

GND

FUSE 1

(Open) Reset output circuit

Emulator interface connector

MB2198-01 and MB2197-01 sideMCU for evaluation

MB91403VDDE

VSS

*2

VDDE

ICLK

ICS[2:0]

ICD[3:0]

BREAKI

INITXI

15Ω 3

21

Chapter1 OVERVIEW

Precaution on designingWhen you operate the evaluation MCU on a user system without an emulator connected, the

input pins of the evaluation MCU connected to the emulator interface should be treated on the

user system as shown below.

During designing, therefore, note that a switch circuit, etc. may be necessary on the user

system.

The emulator interface pins should be treated as shown below.

Documents for referenceFor connection with an ICE, see also the following manuals:

• DSU-FR Emulator MB2198-01 Hardware Manual

• FR20/30 Series MB2197-01 Hardware Manual

Table 1.5-1 Emulator interface pin treatment (DSU-3)

Evaluation MCU pin name Pin treatment

INITXI To be connected to the reset output circuit on the user system

BREAKI To be connected to pulldown

Other To be open

Table 1.5-2 Emulator interface wiring regulations

Signal line name Wiring regulation

ICLKICS[2:0] ICD[3:0] BREAKI

• The total wiring length of each signal (from an evaluation MCU pin to an emulator interface connector pin) shall be not more than 50 mm.

• The difference between the total wiring lengths of signals shall be not more than 2 cm and the total wiring length of ICLK shall be the shortest of all.

UVCC • Use a wiring pattern with a higher capacity than the current rating.

• Connecting a probe incorrectly may cause a short circuit or reverse connection between the power source and GND. For safety's sake, insert a fuse or other protective circuit in each power supply pattern.

GND • To be directly connected to a power supply pattern such as the ground plane.

22

Chapter1 OVERVIEW

1.5.3 Precaution on mounting a crystal oscillatorThe built-in crystal oscillation circuit of this LSI has the following configuration:

Pin description

Circuit constants on external boards

Reference values

C3 and L need to be added depending on the basic wave and overtone characteristics of a

20MHz to 30MHz oscillator. Note: These reference values are to be used only as a guide. The

constants vary according to the characteristics of a crystal oscillator to be used. Fujitsu recom-

mends, therefore, that you conduct preliminary evaluation using an evaluation sample to

Pins Function

X0 Input pin of crystal oscillation cell (OSC)

X1 Output pin of crystal oscillation cell (OSC)

Circuit constant Description

C1,C2,C3 External load capacity

L Inductance

Rr Damping resistor (to be added if necessary)

Oscillation frequency

C1,C2 C3 L Rr

Up to 30MHz 5 to 33pF None None None

20MHz to 50MHz 5 to 15pF Around 10nF Around uH None

X0

C1 C2 C3

Crystal oscillator

To be added during overtone

oscillation

OSC

MB91403

Rr

X1

23

Chapter1 OVERVIEW

establish the circuit constants. To obtain an evaluation sample, contact the Fujitsu sales

department.

1.5.3.1 Receiving clock input signals to the crystal oscillation cell from out of the LSI

To use clock signals generated by an oscillation module outside the LSI, input external clock

signals to the X0 pin and leave the X1 pin open as shown in the following figure.

<Caution>

If external signals to be input have such small-amplitude waveforms that they do notcome across Vth (VDDE/2) of the inverter, the signals cannot be propagated to inside theLSI. In this case, you may need to take a necessary countermeasure such as inserting acapacitor of about 0.01µF between the oscillation module, etc. and the X0 pin on theboard to shape the signals into an input waveform centered around Vth of the inverterbefore inputting it.

1.5.4 Precaution on handling power supply

1.5.4.1 Power-onAt the time of power-on, apply a setting initialization reset (INIT) from the INITXI pin.

Input an "L" level to the INITXI pin until the input clock becomes stable.

1.5.4.2 Indeterminable output at power-onAt power-on, the output pins may become indeterminable until the internal power supply

becomes stable.

1.5.4.3 Built-in DC-DC regulatorThe MB91403 has a built-in regulator. You need to supply 3.3V input to the VDDE pin

MB91403

External clock

OPEN

X0

X1

24

Chapter1 OVERVIEW

and connect a bypass capacitor of about 4.7µF for the regulator to the C pin.

1.5.5 Precaution on the device

1.5.5.1 About the watchdog timer functionThe watchdog timer function of this macro is provided to check that a program delays a reset

within a certain period of time and reset the CPU if the program runs away and fails to delay a

reset.Once the watchdog timer function is enabled, therefore, it keeps running until a reset

occurs.

As an exception, a reset is automatically delayed under a condition that program execution is

stopped on the CPU. For the conditions to which this exception applies, see the section on the

function description for the watchdog timer.

Note that a watchdog reset may not occur if the above status is reached due to system run-

away. If so, apply a reset (INIT) from the external INITXI pin.

1.5.5.2 Restrictions Clock control block

• Allow for clock stabilization time when you input "L" to INITXI.

• To enter the standby mode, use the synchronous standby mode (set with the bit8 SYNCSbit in the TBCR: time-base counter control register) and then use the following sequence:

(LDI #value_of_standby,R0); value_of_standby is write data

to STCR.

(LDI #_STCR,R12) ; _STCR is an address (481H) of STCR.

STB R0,@R12 ; Write to standby control register (STCR).

LDUB @R12,R0 ; STCR read for synchronous standby

LDUB @R12,R0 ; Dummy re-read of STCR

NOP

NOP

NOP

NOP

NOP

In addition, set the I-flag and the ILM and ICR registers to branch to an interrupt handler after

the interrupt handler triggers the microcontroller to return from the standby mode.

3.3V VDDE C

VSS

GND

MB91403

4.7µF

25

Chapter1 OVERVIEW

• If you use the monitor debugger, observe the following precautions:

Do not set a breakpoint within the above array of instructions.

Do not single-step the above array of instructions.

26

Chapter1 OVERVIEW

CPU

• Since the instruction fetch is not done from D-bus, do not set the code area on D-busRAM.

• Do not set a stack area or a vector table on the instruction RAM.

• The following operations may be performed when the instruction immediately followed by

a DIV0U/DIV0S instruction results in (a) acceptance of a user interrupt, (b) single-

stepping, or (c) a break in response to a data event or emulator menu:

(1)The D0 and D1 flags are updated in advance.

(2)An EIT handling routine (user interrupt or emulator) is executed.

(3)Upon returning from the EIT, the DIV0U/DIV0S instructions are executed and the

D0/D1 flags are updated to the same value as in (1).• When a user interrupt factor exists, executing either of theORCCR, STILM and MOV Ri

and PS instructions to enable an interrupt results in the following operations:

(1)The PS register is updated in advance.

(2)An EIT handling routine (user interrupt) is executed.

(3)Upon returning from the EIT, the above instructions are executed and the PSregisters are updated to the same value as in (1).

• Since some instructions manipulate the PS register earlier, the following exceptions may

cause a break in the interrupt handling routine or update the display content of the PS flag

when the debugger is being used. In either case, the processing is conducted properly again

after return from an EIT, the operations before and after the EIT are conducted as

specified.

1.The following operations may be performed when the instructionimmediately followed by a DIV0U/DIV0S instruction results in (a) acceptance

of a user interrupt, (b) single-stepping, or (c) a break in response to a data event or

emulator menu:

(1)The D0 and D1 flags are updated in advance.

(2)An EIT handling routine (user interrupt or emulator) is executed.

(3)Upon returning from the EIT, the DIV0U/DIV0S instructions are executed

and the D0/D1 flags are updated to the same value as in (1).2. When a user interrupt factor exists, executing either of the ORCCR, STILM and

MOV Ri and PS instructions to enable an interrupt results in the following

operations:

(1)The PS register is updated in advance.

(2)An EIT handling routine (user interrupt) is executed.

(3)Upon returning from the EIT, the above instructions are executed and the

PS registers are updated to the same value as in (1).• Do not access data in the control register of the instruction cache and the cache memory in

RAM mode immediately before the RETI instruction.

27

Chapter1 OVERVIEW

• If one of the instructions listed below is executed, the SSU or USP (*1) value is not used

as the R15 value and, as a result, an incorrect value is written to memory.

This applies to only the following 10 types of instructions with R15 specified as Ri.AND R15,@Rj ANDH R15,@Rj ANDB R15,@Rj

OR R15,@Rj ORH R15,@Rj ORB R15,@Rj

EOR R15,@Rj EORH R15,@Rj EORB R15,@Rj

XCHB @Rj,R15

(*1) R15 has no entity. When a program accesses R15, either SSP or USP is accessed

depending on the state of "S" flag of the PS register.

Specify a general-purpose register other than R15 when you write either of the above ten

instructions in assembler.

External bus interface

• If the area set up as little endian has a 32-bit bus width, access the relevant area using only

word (32-bit) access.

• To enable prefetch to the area set up as little endian, access the relevant area using only

word (32-bit) access. The area cannot be correctly accessed using byte or half-word

access.

DMA

• Do not use DMA transfer to the instruction RAM.

Bit search module

• The BSD0, BSD1, and BDSC registers can be accessed using word access only.

1.5.6 Precautions related to debugging

1.5.6.1 Single-stepping the RETI instructionIf an interrupt occurs frequently during single-stepping, only the relevant processing routine is

repeatedly executed after single-stepping RETI. Consequently, the main routine and low-

interrupt-level programs are no longer executed.

To work around this problem, do not single-step the RETI instruction.

Alternatively, perform debugging with the relevant interrupt disabled after the debugging of

the relevant interrupt routine becomes unnecessary.

1.5.6.2 Operand breakDo not apply a data event break to access to the area containing the address of a system stack

pointer.

1.5.6.3 Interrupt handler for NMI request (tool)Add the following program to the interrupt handler to prevent the device from malfunctioning

in case the factor flag to be set only in response to a break request from the ICE is erroneously

set, for example, by an adverse effect of noise to the DSU pin while the ICE is not con-

nected. Note that the ICE can be used without problems after this program is added.

28

Chapter1 OVERVIEW

Location to add this program

The following interrupt handler

Interrupt factor : NMI Request (tool) Interrupt number : 13(decimal), 0D(hexadecimal) Offset : 3C8H TBR is the default address : 000FFFC8H Program to be added

STM (R0,R1)

LDI #B00H,R0 ; B00H is the address of DSU break factor

register.

LDI #0,R1

STB R1,@R0 ; Clear the break factor register.

LDM (R0,R1)

RETI

1.5.6.4 Trace modeIf, during debugging, the trace mode is set to "Full trace mode" (in which the trace memory of

the ICE itself is used with the built-in FIFO as output buffer, thus preventing the loss of trace

data), the electric current may be increased or D-busDMA access may be lost.

Also, the trace data may be lost.

To work around this problem, do not set the full trace mode.

1.5.6.5 Simultaneous occurrence of a software break and a user interrupt

If a software break and a user interrupt occur simultaneously, the debugger may encounter the

following phenomena:

The debugger stops while pointing to a location other than the programmed breakpoints.

The halted program is not re-executed correctly.

If either of these phenomena occurs, use a hardware break in additino to a software break. If

you are using the monitor debugger, do not set any break at the relevant location.

29

Chapter1 OVERVIEW

1.6 Address mapThe built-in FR core of this LSI can be configured to have eight chip select (CS) areas. The CS

areas are allocated in this LSI as follows:

• CS0-1,6-7: User area

- Allocated to the CS0 built-in ROM area.(*1)

- Allocated to the CS1 built-in RAM area.

CS6-7: These areas are allocated to the external chip select signals: CSX[6]/CSX[7].

- CS6 CSX[6]

- CS7 CSX[7]

• CS2-5: Areas for management of this LSI

(*1) CS0 can be allocated to an external area in the external pin (TEST[2:0]) setting.

For more information, see Section 6.1, "Built-in and External Boot ROM selection."

1.6.1 Chip select area settingsThe areas for management of this LSI, which are allocated to the CS2-5 areas, consist of the

registers and processing areas of peripheral modules of this LSI, such as the built-in MAC

interface, encryption and authentication processing unit, I2C interface, and GPIO.

Before configuring the registers of these modules, first configure the ASR (Area Select Regis-

ter), ACR (Area Configuration Register), AWR (Area Wait Register) and define the CS areas.

The following table shows the modules allocated to each of the CS0-5 areas and whether the

RDY control of the FR core should be conducted.

CS area Module Address Size RDY control

CS0 Built-in ROM0x000C_0000

- 0x000F_FFFF

256KB Not required

CS1 Built-in RAM0x0010_0000

- 0x0010_FFFF

64KB Not required

CS2 I2C IF0x010F_0000

- 0x010F_FFFF

64KB Not required

CS3

MAC/MII IFEncryption and authentication processing unit

0x0110_0000 -

0x0113_FFFF256KB Not required

CS4 External IF/PORT0x0114_0000

- 0x0114_FFFF

64KB Not required

CS5 DH processing unit0x0115_0000

- 0x0115_FFFF

64KB Not required

30

Chapter1 OVERVIEW

<Caution>

The areas for management of this LSI basically have 32-bit bus specifications.

However, note that CS2 has 8-bit bus specifications.

The following figures show the setting examples for the ASR, ACR, and AWR registers inthe FR core.

Setting values for CS registers (Examples)

ASR (Area Select Register) setting example

ASR0=0x000CACR0=0x2940AWR0=0x0148

ASR1=0x0010ACR1=0x0920AWR1=0x0148

ASR2=0x010FACR2=0x0020AWR2=0x2048

ASR3=0x0110ACR3=0x2820AWR3=0x1048

ASR4=0x0114ACR4=0x0820AWR4=0x2058

ASR5=0x0115ACR5=0x0820AWR5=0x2048

15 14 13 2 1 0ASRx A31 A30 A29 A18 A17 A16

CS0 : 16'h000C

CS3 : 16'h0110 CS4 : 16'h0114

CS1 : 16'h0010 CS2 : 16'h010F

CS5 : 16'h0115

31

Chapter1 OVERVIEW

ACR (Area Configuration Register) setting example

AWR (Area Wait Register) setting example

<Caution>

For W05-W04 of AWR4, 2' b00 must not be set.

15 14 13 12 11 10 9 8ACRx ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0

CS0 : 4'h2 (256KB) CS0 : 2'b10 (32bit) CS0 : 2'b01 (2burst) CS1 : 4'h0 (64KB) CS1 : 2'b10 (32bit) CS1 : 2'b01 (2burst) CS2 : 4'h0 (64KB) CS2 : 2'b00 (8bit) CS3 : 4'h2 (256KB) CS3 : 2'b10 (32bit) CS4 : 4'h0 (64KB) CS4 : 2'b10 (32bit) CS5 : 4'h0 (64KB) CS5 : 2'b10 (32bit)

CS2-5 : 2'b00 (Single access)

7 6 5 4 3 2 1 0ACRx SREN PFEN WREN 0 TYP3 TYP2 TYP1 TYP0

1'b0 CS0-1:1'b1 CS0:1'b0

Others:1'b0 Others:1'b1

(No BRQ/BGR NTX)

(Prefetch enabled)

(Write disabled)

CS0-5 : 4'h0 (Normal access)

(Prefetch disabled)

(Write enabled)

15 14 13 12 11 10 9 8AWRxH W15 W14 W13 W12 W11 W10 W09 W08

CS0 : 4'h0 (0 wait cycle) CS0 : 4'h1 (1 wait cycle) CS1 : 4'h0 (0 wait cycle) CS1 : 4'h1 (1 wait cycle) CS2 : 4'h2 (2 wait cycles) CS3 : 4'h1 (1 wait cycle) (Burst access not supported) CS4 : 4'h2 (2 wait cycles) CS5 : 4'h2 (2 wait cycles)

Others : 4'h0

7 6 5 4 3 2 1 0AWRxL W07 W06 W05 W04 W03 W02 W01 W00

1'b1 1'b0 1'b0 1'b0

CS4 : 2'b01(Write recovery cycle: 1)

(CSX setup cycle: 0)

(CSX hold

cycle: 0)

2'b01(Idle cycle during

successive read and write: 1)

(Write recovery cycle: 0) CS0-3,5 : 2'b00

(Asynchronous write strobe

output)

(Address setup

cycle: 0)

32

Chapter1 OVERVIEW

1.6.2 Address mapThe following figure shows the address map of this LSI.

The built-in ROM (*1) and RAM and peripheral modules allocated to the areas for manage-

ment of this LSI can also be set to other address spaces than shown in the above figure. In this

case, the CS[5:2] areas need to have a start address that meets the following conditions:

[ CS [3] start address setting condition]

Address[17:16]= "00"

[ CS[5:4,2] start address setting condition]

Address[13:12]= "00"

*1 The reset and mode vector table of the FR core are allocated to the following address areas.

Therefore, the built-in ROM needs to have an address space that meets the following

conditions:

• Reset vector: 0x000F_FFFCH

• Mode vector: 0x000F_FFF8H

Module Name Chip Select SIZEWait

Cycle

0000_0000H

FR core internal area

0004_0000H

000C_0000H

0010_0000H

010F_0000H

User area

0110_0000H

0111_0000H

0112_0000H

Areas for management

of this LSI0113_0000H

0114_0000H

0115_0000H

0116_0000H

FFFF_FFFFH

External IF/GPIO

256KB 1

CS[4] 64KB 2

FR core area

CS[2]I2C IF 2

Built-in ROM CS[0] 0256KB

DH processing unit CS[5] 64KB 2

64KB

CS[3]

Built-in RAM CS[1] 64KB 0

MAC/MII IFEncryption and authentication

processing unit

33

Chapter1 OVERVIEW

1.7 Operation

1.7.1 Clock

Clock generation controlThe internal clock is generated in the FR core as follows:

• Selecting a source clock: Select a clock source.

• Generating a base clock: Divide the source clock by two or cause PLL oscillation to

generate a base clock.

• Generating internal clocks: Divide the base clock to generate three operating clocks to be

supplied to various parts of the device.

The following sections describe the generation and control of these clocks. For detailed

description of register flags listed in the explanation, see Sections 2.3.10.9, "Block diagram of

clock generation control unit" and 2.3.10.10, "Registers of clock generation control unit."

Source clock

Self-excited oscillation mode (X0 and X1 pins input)

In this mode, an oscillator is connected to the external oscillation pin and the original oscilla-

tion generated in the built-in oscillation circuit is used as the source clock. All the clock

sources including the external bus clock are the FR core.

External oscillation mode (X0 pin input and X1 pin open)

In this mode, the clock generated by an oscillation module, etc. outside the LSI is used as the

source clock. All the clock sources including the external bus clock are the FR core.

<Caution>

If external signals to be input have such small-amplitude waveforms that they do not getacross Vth (VDDE/2) of the inverter, the signals cannot be propagated to inside the LSI.In this case, you may need to take a necessary countermeasure such as inserting acapacitor of about 0.01µF in series between the oscillation module, etc. and the X0 pin onthe board to shape the signals into an input waveform centered around Vth of the inverterbefore inputting it.

Base clockGenerate the internal base clock using either of the following source clocks.

• Main clock divided by two

• Main clock multiplied by PLL

The source clock selection control is conducted according to the setting of the clock source

control register (CLKR).

34

Chapter1 OVERVIEW

1.7.1.1 Block diagram of clock generation control unitThe following figure shows the block diagram of the clock generation control unit.

1.7.2 ResetWhen a reset factor occurs, this LSI stops the operations of all the programs and hardware and

initializes the operation status.

There are three types of reset operations, each of which has different generation triggers and

initialization processes.

1.7.2.1 Setting initialization reset (INITXI pin)Asserting the "L" level input of the INITXI (reset) pin generates a reset and causes

initialization.

[ Initialization location]

• FR core: Section 2.3.9.2.1, "Setting initialization reset (INIT)" is executed.

• Peripheral macro: The information of all the registers, internal operations, and external pins

is initialized.

CPU clock division CPU clock

Peripheral clock division

External bus clock division External bus clock

X0 PLL

X1

1/2

MB91403

Peripheral clock (in FR)

Clock generation unit

Oscillationcircuit

Peripheral clock (such as MAC IF)

CLKR register

DIVR0 and 1 registers

Sto

p co

ntro

l

FR Core

Sel

ecto

r

Sel

ecto

rS

elec

tor

Sel

ecto

r

35

Chapter1 OVERVIEW

Apply the "L" level input to the INITXI pin until the power voltage and the external clock

input become stable.

1.7.2.2 Watchdog resetWhen the watchdog timer expires, a watchdog timer reset is generated and initialization is

conducted.


FR core: Section 2.3.9.2.1, "Setting initialization reset (INIT)" is executed. However, the reset

factor flag is not cleared.

1.7.2.3 FR resetDue to a software reset in the FR core, a reset is generated and initialization is conducted.


• FR core: Section 2.3.9.2.2, "Operation initialization reset (RST)" is executed.

• Peripheral macro: The information of all the registers, internal operations, and external pins

is initialized.

1.7.3 InterruptThe FR core has eight external interrupt pins, six of which are used for interrupts in this LSI

and the remaining two of which are connected to external pins, being allocated to interrupts

from outside this LSI.

Interrupts in this LSI are connected to the external interrupt pins of the FR core, being allo-

cated as shown in the following figure.

The settings for external interrupt enable, interrupt request, and interrupt request detection are

made in the ENIR (external interrupt enable register), EIRR (external interrupt factor register),

and ELVR (request level setting register), respectively.

X0 and X1 pins

Power voltage

INITX pin

36

Chapter1 OVERVIEW

INT[7:6] External interrupt pins: Allocated to INT[7:6].

INT[5] Interrupt signals from GPIO (Port A) are input.

INT[4] Interrupt signals from I2C IF are input.

INT[3] Interrupt signals from External IF are input.

INT[2] Reserved for future use

INT[1] Interrupt signals from the authentication processing unit are input.

INT[0] Interrupt signals from Ethernet MAC IF are input.

Note: All the interrupt signals in this LSI are asserted "High" active.

Therefore, set the ELVR register to "H" level detection.

For information on the settings and processing of interrupts, see the manuals supplied with

modules.

1.7.4 DMA transferThis LSI provides the DMA transfer function using the DMAC of the FR core. DMAC has

five channels, two of which are used in the LSI.

The FR core DMAC channels are allocated as follows:

1) DMA factors from ch0 Ethernet MAC IF

The MAC IF (receive FIFO) to Memory supports the Fly-by (IO to Memory) mode.

Note: The Memory to MAC IF (send FIFO) supports only DMA transfer through software

activation.

Note: In Fly-by mode, two I/O wait cycles need to be set in IOWR0 (I/O Wait Register for

DMAC) in the CPU.

2) DMA factor from ch1 External IF

The External IF (receive FIFO) to Memory supports Fly-by (IO to Memory) mode.

3) DMA factor other than ch2 DREQ

FR Core

INT[7:6] External interrupt pin : INT[7:6]

INT[5] GPIO

INT[4] I2C IF

INT[3] External IF

INT[2] reserved

INT[1] Authentication processing unit

INT[0] Ethernet MAC IF

External interrupt pins (8)

MB91403

37

Chapter1 OVERVIEW



FR Core

DREQ0

DACKX0

IORDX

EOPX0

EOTX0

DREQ1

DACKX1

IORDX

EOPX1 OPEN

EOTX1

DMAC

(ch.2-4)

External IF

MB91403

* Factors other than DREQ

DMAC

DMAC

Ethernet MAC IF (ch.0)

(ch.1)

38

Chapter3 LAN CONTROLLER

Overview, Features

39


3.1 Overview

This is the Ethernet LAN controller compliant to IEEE802.3 with the built-in 10/100BASE-T transceiver incorporating L3/4 filtering functions.

LAN controller has the following features.

• Packet filtering function

• Packet filtering functions of L2/L3/L4 enable CPU load reduction.

• 10/100M MAC compliant to IEEE802.3

<Caution>

To perform 100M communication with this product, you must configure the settings for theoperating frequency of LAN controller (external bus frequency of FR) to above 25MHz.

• MII interface (for full and half duplex operations)

• SMI interface for PHY device control

When you conduct data communication with the outside through LAN, these interfaces will

enable CPU load reduction by carrying out the following operations with hardware.

• Convert send data to LAN data format/Convert from LAN data format to receive data.

• Continuous sending and receiving process for multiple packets (buffer manager)

Send buffer 1536Byte/Receive buffer 3072Byte

• Error check

• Retransmit when collision occurs (network management)

40


Block Diagram

FR CORE

RAM

8KB

I-Cache4KB

DSU

DMAC

5ch

PLL

UART 2ch

INTC

Timer

Built-in ROM256KByte

External IF

I2C

Memorycontroller

8/16

ROM/FLASH

SRAM/SDRAM

8/16

GPIO

PHY

MII

Internet

EtherMAC-L2/L3/L4FilteringSMI

Built-in RAM64KByte

Remote operation from PCs/mobile

phones

Controlling devices such as

PCs/internet appliances

41


3.1.1 Features FR core interface

FR core interface of LAN controller has data bus buffer to interface with FR core.

DMA read operation (data reception operation)

DMA read operation is the operation to transfer receive data in the buffer memory to the

external memory (data reception operation). This allows you to receive the data with a single

instruction.

Buffer memory manager

LAN interface normally has the buffer for sending and receiving data between data link

controller and FR core face. LAN controller has the built-in dedicated hardware for managing

and controlling the buffer memory (buffer memory manager) and RAM.

Data link controller

Data link controller (DLC) runs various functions that meet Ethernet standards of 10/100Mbps

for IEEE802.3 CSMA/CD method.

<Functions of data link controller>

• Functions to convert send data in the buffer to LAN data format and send.

• Functions to convert LAN data format to receive data in the buffer and receive.

• Functions to retransmit by binary exponential back-off algorithm for the case of collision

occurrence resulting in transmission failure.

• Functions to receive data so long as the address is the registered multicast address, apart

from your own address (multicast address filtering function).

Moreover, with the filtering function implemented, it can receive the required data only.

<Filtering function>

• Filtering function of layer 3/4 (implemented in hardware).

Network management function

You can manage the network from the internal register of LAN controller.

From result status information, you can find out the following information.

• Whether the transmission operation to network has succeeded.

• Whether CRC error, alignment error (bit size is not the integral multiple of 8) etc. have

occurred at the time of reception.

• Whether collision has occurred at the time of transmission, and the number of times, if any.

This allows you to find out error information of transmitted and received data. The processing

by using this information should be created by user.

Multicast receive address filtering function

The function to filter by specifying low-order 6 bits used to calculate CRC of destination

address 48 bits will enable you to narrow down the scope of the searches for filtering by L3/L4

filtering table and reduce the load.

42


Block Diagram

This section describes 6 functional blocks for LAN controller.

Data link controller part

It runs the functions of data link layer defined by the IEEE802.3. When transmitting, it adds

preamble and CRC code to the send data read out from the buffer memory and outputs

them. And when collision occurs, it automatically executes the back-off algorithm and

retransmits.

When receiving, it checks the address match of the incoming packet to be received, then,

after the error check, removes the preamble and CRC, converts to parallel data and writes

into the buffer memory.

In addition, the data link controller part has multicast address filtering function and can

recognize multicast address groups of up to 64 groups.

DataData

Write signalWrite signal Control signal

DataStatus

Buffer information

Control signalControl signal

DataData

Error informationInterrupt signal

DataFiltering information Read signal Buffer

informationRead signal Buffer information

Control signal

Data

SMI block

Receive data link

controller

Send data link

controller

Registerblock FR Core

interface

Filtering block

Send buffer memory manager

Receive buffer memory

manager

43


Buffer manager part

It has the built-in RAM to buffer send and receive data (the send buffer 1536byte, the

receive buffer 3072byte). Buffer memory automatically conducts the arbitration of access

from both FR core side and network side, update of buffer pointer, etc. by buffer manager

with the send buffer of 1 port and the receive buffer of 2 ports. And the send buffer has

packet chain function, which, once the send data for multiple packets are stored, allows you

to consecutively transmit the packets in the buffer with a single instruction for starting the

transmission.

FR core interface part

It inputs and outputs data bus and bus control signal for connceting to FR core bus. Byte

order is also settable.

LAN controller has three pairs of register sets that are data link control register, buffer

memory port register and multicast address register, and are accessible through FR core

interface. Also, receive data transfer between buffer memory port and FR core can be done

by DMA transfer.

Register block part

It puts together the registers such as data link control register, buffer memory port register.

You can find out individual status by address. And it also outputs interrupt signal.

Filter block part

The fact that the filtering processing to be done when receiving the packet, which has

traditionally been performed by CPU, is implemented in hardware enables you to

significantly reduce the processing load of CPU. It has the filtering function of L3/L4.

SMI block part

It is the block to read/write into PHY register through SMI interface. It draws different

types of status (half-duplex/full-duplex, link status, 10/100 identification, etc.) information

from PHY register and is also used when configuring the settings for device.

44


Table 3.1-1 Register list

Address Register Name abbreviation Size R/W Initial Value

0x0110 _0000 Data Link Control Register 0 DLCR0 8bit R/W 8'b0-000000

_0001 Data Link Control Register 1 DLCR1 8bit R/W 8'b0







BA

NK

0



_000A Data Link Control Register A DLCR10 8bit R/W 8'b0

_000B Data Link Control Register B DLCR11 8bit R/W 8'b0

_000C Data Link Control Register C DLCR12 8bit R/W 8'b0

_000D Data Link Control Register D DLCR13 8bit R/W 8'b0

BA

NK

1

_0008 Multicast Address Register 1 MAR8 8bit R/W 8'b0

_0009 Multicast Address Register 2 MAR9 8bit R/W 8'b0

_000A Multicast Address Register 3 MAR10 8bit R/W 8'b0

_000B Multicast Address Register 4 MAR11 8bit R/W 8'b0

_000C Multicast Address Register 5 MAR12 8bit R/W 8'b0

_000D Multicast Address Register 6 MAR13 8bit R/W 8'b0

_000E Multicast Address Register 7 MAR14 8bit R/W 8'b0

_000F Multicast Address Register 8 MAR15 8bit R/W 8'b0

BA

NK

2

_0010 Buffer Memory Port Register 8 BMPR8 32bit R/W 32'h0

_000A Buffer Memory Port Register 10 BMPR10 8bit R/W 8'b0

_000B Reserved - - - -

_000C Buffer Memory Port Register 12 BMPR12 8bit R/W 8'b0

_000E Buffer Memory Port Register 14 BMPR14 8bit R/W 8'b0

_0014 Filter Command Register FL_CMD 16bit R/W 16'b00000000---0---0

_0018 Filter Status Register FL_STATUS 1bit R 1'b0

_001C Filter Data Register FL_DATA 32bit R/W 32'b0

_0020 Filter mode Control Register FL_CONTROL 11bit R/W 11'b0

_0024 Filter Subnet Register FL_SUBNET 32bit R/W 32'hFFFFFFFF

_0028 SMI Command Register SMI_CMD 16bit R/W 16'b0--00000---00000

_002C SMI Command Status Register SMI_CMD_ST 2bit R 2'b0

_0030 SMI Data Register SMI_DATA 16bit R/W 16'h0

_0034 SMI Polling Register SMI_POLLINTVL 16bit R/W 16'h0

_0038 SMI PHY Address Register SMI_PHY_ADD 5bit R/W 5'b0

_003C SMI Control Register SMI_CONTROL 3bit R/W 3'b111

_0040 SMI Status Register SMI_STATUS 5bit R 5'b01110

_0044 SMI Interrupt Enable Register SMI_INTENABLE 1bit R/W 1'b-

_0048 SMI MDC Register SMI_MDCDIV 5bit R/W 5'b1011

45


About register bank

I/O address space used exclusively by LAN controller is 32 byte, and is to be accessed by

switching each register and I/O address space by bank switching.

Register bank can be switched by register bank bit (DLCR7.RBNKn).

<Caution>

For buffer memory port register (BMPR8), packet filters and SMI interface register, theycan be accessed using word access only.

Table 3.1-2 Register bank bit (DLCR7.RBNKn)

BIT3 BIT2 Mode

0 0 Use bank 0 (register set for DLCR0-DLCR7, DLCR8-DLCR15)

0 1 Use bank 1 (register set for DLCR0-DLCR7, MAR8-MAR15)

1 - Use bank 2 (register set for DLCR0-DLCR7, BMPR10-BMPR14)

46


3.2 Register DetailsExplanation of the code expressing access limits to each bit of the register

[Code]

R : Read permitted

R0 : Always 0

R1 : Always 1

RX : Indeterminate

W : Write permitted

W0 : Always write 0

W1 : Always write 1

WX : Write invalid

[Combination] "/" and ",

R/W: Written data can be read

R,W : The significance of the bit changes according to whether it is read or write

[Support for read modify write] using "(" ")

R(RM1)/W : Possible to read written value (The reading is always 1 during RMW)

R(RM1),W : Read is possible (always 1 during RMW), write is possible

47


3.2.1 Detailed Explanation of the Register

Transmission Status Register: DLCR0DLCR0: Address 0110_0000H (access: Byte/Half-word)

This is the register to display the transmission status of data link controller.

bit 7: Transmit O.K

• If packet ready bit is "1", "1" is automatically set when the transmission of all the

packets in the send buffer is complete, and is maintained until it is cleared.

bit 6: Net busy

bit 5-4: Undefined....Writing does not affect the operation. The read value is always "0".

bit 3: Late collision

bit 2: Collision error

• When the collision error bit is "1", collisions of up to 16 times are automatically

retransmitted by data link controller. You can find out number of times of collisions

occurred by reading collision count bit (DLCR4.COLn).

7 6 5 4 3 2 1 0 bit

TMT OK NET BSY - - LTE COL COL RETRY OVER

-

0 X 0 0 0 0 0 0 Initial value

R,W R/WX R0/WX R0/WX R,W R,W R,W R0/WX Attribute

TMT OK Read operation Write operation

0 This bit was cleared No effect

1 Transmission of all the packets in the send buffer complete

Clear this bit

NET BSY Read operation

0 Network is not used (carrier is not detected)

1 Network is used (carrier is detected)

LTE COL Read operation Write operation

0 No late collision No effect

1 Late collision occurred Clear this bit

COL Read operation Write operation

0 No collision error No effect

1 Packet collision occurred on the network during packet transmission

Clear this bit

48


bit 1: Retry over

bit 0: Undefined....Writing does not affect the operation. The read value is always "0".

Status bit for BIT7,BIT3-0 asserts external interrupt -INT of FR core by bit set if the

corresponding bit of DLCR2 is set.

Reception Status Register: DLCR1DLCR1: Address 0110_0001h (access: Byte/Half-word)

This is the register to display the reception status of data link controller.

bit 7: Packet ready

• When packet ready bit is "1", it means that the packet addressed to local is properly

received and the transfer to the receive buffer is complete. That is, there is at least one

packet of receive data in the receive buffer.

• If you set packet ready bit to "1", it clears this bit. However, if the received packet still

remains in the receive buffer after the host side reads out receive data for one packet

from the receive buffer, this bit is automatically reset.

bit 6: Communication error

RETRY OVER Read operation Write operation

0 No collision error for 16 times No effect

1 Collision occurred 16 times in a row during packet transmission

Clear this bit

7 6 5 4 3 2 1 0 bit

PKT RDY RX ERR FIL DROP

RX LNGPKT

RX SRTPKT

ALG ERR CRC ERR OVRFL0

0 0 0 0 0 0 0 0 Initial value

R,W R,W R,W R,W R,W R,W R,W R,W Attribute

PKT RDY Read operation Write operation

0 The packet received does not exist in the receive buffer

No effect

1 Transfer to the receive buffer complete Clear this bit

RX ERR Read operation Write operation

0 No communication error No effect

1 Communication error Clear this bit

49


bit 5: Filtering drop

bit 4: Long packet

• When long packet bit is "1", it means that the data length of received packet

(address+data length+data body) exceeds the set maximum data length (1514byte).

bit 3: Short packet

• When short packet bit is "1", it means that the data length of received packet

(address+data length+data body) is less than the set minimum data length (60byte). If

enable short packet receive bit [DLCR5:BIT3] is set, it is set in the case of being less

than 16 byte.

bit 2: Alignment error

• When alignment error bit is "1", it means that CRC of received packet is not correct and

that the number of bits of received data is not multiples of 8.

bit 1: CRC error

bit 0: Overflow error

FIL DROP Read operation Write operation

0 No packet drop with filtering mechanism No effect

1 Packet was dropped with filtering mechanism Clear this bit

RX LNG PKT Read operation Write operation

0 No long packet error No effect

1 Long packet error Clear this bit

RX SRT PKT Read operation Write operation

0 No short packet error No effect

1 Short packet error Clear this bit

ALG ERR Read operation Write operation

0 No alignment error No effect

1 Alignment error Clear this bit

CRC ERR Read operation Write operation

0 No CRC error No effect

1 CRC of received packet is not correct Clear this bit

OVRFLO Read operation Write operation

0 No overflow error No effect

1 Overflow error present Clear this bit

50


• When overflow error bit is "1", it means that the packet is erased because the data length

of the received packet is larger than the free space of the receive buffer memory. Even

after this bit is set, if the next packet is smaller than the free space of the buffer memory,

it is properly received. If this bit is set, it means that the receive buffer memory is almost

full, so urgently transfer the data in the buffer to the host system side.

Status bit for BIT7-0 asserts external interrupt -INT of FR core by bit set if the corresponding

bit of DLCR3 is set.

Reception Status Register: Supplementary Explanation Of DLCR1

Short packet bit [DLCR1:BIT3]

RX SRT PKT bit is set on the following conditions.

R(K) < 20 byte 20byte <= R(K)<minimum data length *2 R(K)>= minimum data length *2

RX SRT PKTBit

To be set *1 To be set *1 Not to be set

*1: When the carrier drop of transmitting end data occurs (by the collision caused by the packet that the local transmitted) during collision error, RX SRT PKT bit will not be set. *2: When DLCR5<ENA SRT PKT> =0, the minimum data length will be → 64 byte. When DLCR5<ENA SRT PKT> =1, the minimum data length will be → 24 byte. Only in the case of R(K)>=minimum data length, check CRC error.

51


Transmit Interrupts Enable Register:DLCR2DLCR2:Address 0110_0002h (access: Byte/Half-word)

This is the register to enable transmit interrupts.

bit 7: Transmit O.K interrupt occurrence enable


bit 3: Late collision interrupt occurrence enable

bit 2: Collision error interrupt occurrence enable

bit 1: Retry over interrupt occurrence enable

bit 0: Undefined....Writing does not affect the operation. The read value is always “0”.

By setting the bit that corresponds to the status bit of DLCR0 to "1", it asserts the external interrupt IRQX

of FR core when setting the status bit.

7 6 5 4 3 2 1 0 bit

ENA TMT OK

- - - ENA LTE COL

ENACOL ENA RETRY OVER

-


R/W R0,WX R0,WX R0,WX R/W R/W R/W R/W Attribute

ENA TMT OK Mode

0 TMT OK interrupt occurrence disable

1 TMT OK interrupt occurrence enable

ENA LTE COL Mode

0 LTE COL interrupt occurrence disable

1 LTE COL interrupt occurrence enable

ENA COL Mode

0 COL interrupt occurrence disable

1 COL interrupt occurrence enable

ENA RETRY OVER Mode

0 RETRY OVER interrupt occurrence disable

1 RETRY OVER interrupt occurrence enable

52


Reception Interrupts Enable Register:DLCR3DLCR3: Address 0110_0003h (access: Byte/Half-word)

This is the register to enable reception interrupts.

bit7: Packet ready interrupt occurrence enable

bit 6: Communication error interrupt occurrence enable

bit 5: Filtering drop interrupt occurrence enable

bit 4: Long packet interrupt occurrence enable

bit 3: Short packet interrupt occurrence enable

7 6 5 4 3 2 1 0 bit

ENA PKT RDY

ENA RX ERR

ENA FIL DROP

ENA RX LNG PKT

ENA RX SRT PKT

ENA ALG ERR

ENA CRC ERR

ENA OVRFLO


R/W R/W R/W R/W R/W R/W R/W R/W Attribute

ENA PKT RDY Mode

0 PKT RDY interrupt occurrence disable

1 PKT RDY interrupt occurrence enable

ENA RX ERR Mode

0 RX ERR interrupt occurrence disable

1 RX ERR interrupt occurrence enable

ENA FIL DROP Mode

0 FIL DROP interrupt occurrence disable

1 FIL DROP interrupt occurrence enable

ENA RX LNGPKT Mode

0 RX LNG PKT interrupt occurrence disable

1 RX LNG PKT interrupt occurrence enable

ENA RX SRTPKT Mode

0 RX SRT PKT interrupt occurrence disable

1 RX SRT PKT interrupt occurrence enable

53


bit 2: Alignment error interrupt occurrence enable

bit 1: CRC error interrupt occurrence enable

bit 0: Overflow interrupt occurrence enable

By setting the bit that corresponds to the status bit of DLCR1 to "1", it asserts the external interrupt IRQX

of FR core when setting the status bit.

ENA ALG ERR Mode

0 ALG ERR interrupt occurrence disable

1 ALG ERR interrupt occurrence enable

ENA CRC ERR Mode

0 CRC ERR interrupt occurrence disable

1 CRC ERR interrupt occurrence enable

ENA OVRFLO Mode

0 OVRFLO interrupt occurrence disable

1 OVRFLO interrupt occurrence enable

54


Transmit Mode Register:DLCR4DLCR4: Address 0110_0004h (access: Byte/Half-word)

This is the register to display the setting of operation mode of transmitter and number of

occurrences of collision.

bit 7-4: Collision count

• It displays the number of times of collisions occurred by the time of transmission

complete. It is cleared when the transmission is complete.


bit 1: Loop back control

• Data is also output to the external during loop back operation.


7 6 5 4 3 2 1 0 bit

COL3 COL2 COL1 COL0 - - LBC -0 0 0 0 0 0 1 0 Initial

valueR R R R R0,WX R0,WX R/W R0,WX Attribute

LBC Read operation/Write operation

0 Loop back mode

1 Normal sending and receiving operation

55


Receive Mode Register:DLCR5DLCR5: Address 0110_0005h (access: Byte/Half-word)

This is the register to display the setting of operation mode of receiver and the status of the

receive buffer memory.

bit7: Undefined....Writing does not affect the operation. The read value is always "0".

bit 6: Buffer empty


bit 3: Enable short packet reception

bit 2: Enable remote reset....Writing does not affect the operation. The read value isalways "0".

bit 1-0: Address match mode

7 6 5 4 3 2 1 0 bit

- BUF EMP - - ENA SRT PKT

- AM1 AM0


R0,WX R,WX R0,WX R0,WX R/W R0,WX R/W R/W Attribute

BUF EMP Read operation

0 Valid data are still in the receive buffer memory

1 Valid data are not in the receive buffer memory

ENA SRT PKT Read operation/Write operation

0 Receive the packet of data length (address+data length+data body) 60 byte or more and not over 1514 byte.

1 Receive the packet of data length (address+data length+data body) 16 byte or more and not over 1514 byte.

AM1 AM0 Address match detection mode

0 0 Not receive packet. Reject all the packets received for unmatched address

0 1

1 0 Receive the packet that is of physical address, broadcast address, multicast address and that is selected by multicast address register.

1 1 Receive all the packets irrespective of destination address

56


Control Register 1:DLCR6DLCR6: Address 0110_0006h (access: Byte/Half-word)

This is the register to set the sending and receiving operation start of LAN controller.

bit 7: Enable data link controller

• When this bit is 0, disable accessing to node ID register and filter table.


7 6 5 4 3 2 1 0 bit

ENA DLC - - - - - - -1 0 0 0 0 0 0 0 Initial

valueR/W R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX Attribute

ENA DLC Read operation/Write operation

0 LAN controller is ready for sending and receiving operation

1 LAN controller is not ready for sending and receiving operation

57


Control Register 2:DLCR7DLCR7: Address 0110_0007h (access: Byte/Half-word)

This is the register to set each operation mode of LAN controller.


bit 3-2: Register bank

• LAN controller has three types of internal register set, and from FR core side, each

register set is accessible by bank switching with this bit.

• DLCR0-DLCR7 and BMPR8 are always accessible irrespective of register bank.


bit 0: Byte swap

• Register access other than BMPR8 will not be byte swapped even if this bit is set.

7 6 5 4 3 2 1 0 bit

- - - - RBNK1 RBNK0 - BYTE SWAP


R0,WX R0,WX R0,WX R0,WX R/W R/W R0,WX R/W Attribute

RBNK1 RBNK0 Mode

0 0 Use register set of bank 0 (DLCR0-DLCR7, DLCR8-DLCR15)

0 1 Use register set of bank 1 (DLCR0-DLCR7, MAR8-MAR15)

1 - Use register set of bank 2 (DLCR0-DLCR7, BMPR10- MPR14)

BYTE SWAP Mode

0 Not byte swap for access to BMPR8(Little endian)

1 Byte swap for access to BMPR8 and reverse high-order data and low-order data (Big endian)

58


Node ID Register 1-6:DLCR8-13DLCR8 : Address 0110_0008h (access: Byte/Half-word)

DLCR9 : Address 0110_0009 (access: Byte/Half-word)

DLCR10: Address 0110_000A (access: Byte/Half-word)

DLCR11: Address 0110_000B (access: Byte/Half-word)

DLCR12: Address 0110_000C (access: Byte/Half-word)

DLCR13: Address 0110_000D (access: Byte/Half-word)

This is the register to store local node ID.

• This is the register to store local node ID

• DLCR8-DLCR13 is the register to store local node ID. It compares the destination address

in the received packet with the value of this register, and receives the matched packet

according to the setting of address match mode bit (DLCR5:AMn).

• DLCR8 will be LSB of node ID and DLCR13 will be MSB of node ID.

• For Ethernet, destination address is sent from LSB side.

• Only when the enable data link controller bit (DLCR6.-ENA DLC) is "1", it is possible to

read/write.

7 6 5 4 3 2 1 0 bit

DLCR8 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0DLCR9 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8DLCR10 ID 23 ID 22 ID 21 ID 20 ID 19 ID 18 ID 17 ID 16DLCR11 ID 31 ID 30 ID 29 ID 28 ID 27 ID 26 ID 25 ID 24DLCR12 ID 39 ID 38 ID 37 ID 36 ID 35 ID 34 ID 33 ID 32DLCR13 ID 47 ID 46 ID 45 ID 44 ID 43 ID 42 ID 41 ID 40



59


Multicast Address Register 1-8:MAR8-15MAR8 :Address 0110_0008h (access: Byte/Half-word)

MAR9 :Address 0110_0009h (access: Byte/Half-word)

MAR10:Address 0110_000Ah (access: Byte/Half-word)

MAR11:Address 0110_000Bh (access: Byte/Half-word)

MAR12:Address 0110_000Ch (access: Byte/Half-word)

MAR13:Address 0110_000Dh (access: Byte/Half-word)

MAR14:Address 0110_000Eh (access: Byte/Half-word)

MAR15:Address 0110_000Dh (access: Byte/Half-word)

This is the register to select the multicast address packet that is received when the address

match mode bit [DLCR5:BIT1-0] is set to "1,0".

• This is the register to select the multicast address packet that is received when the address

match mode bit [DLCR5.AMn] is set to "1,0".

• Multicast address is input to CRC circuit of 32 bits, and will be grouped into 64 groups by

low-order 6 bits of CRC calculated. The xx of MIDxx is corresponding to the figure of CRC

low-order 6 bits, therefore, if you set "1" to MID0, the packet for CRC low-order 6 bits

"000000" will be enabled, and if you set "1" to MID63, the packet for CRC low-order 6 bits

"111111" will be enabled.

• Only when the enable data link controller bit (DLCR6.-ENA DLC) is "1", it is possible to

read/write.

Multicast operation

With this function, if the first bit of destination address of the packet received is 1, CRC of

destination address 48 bits is calculated by CRC circuit and low-order 6 bits is internally

latched. And the value of this 6 bits is compared with multicast address register, then if the

bits of the corresponding multicast register is set, the multicast packet will be received, and

if the bits is not set, it will be dropped. This will enable all the multicast addresses to be

divided into 64 groups and you can receive the multicast packet of a given group only. If all

the bits of multicast addess register are 0, you cannot receive the multicast address packet.

Or conversely, if you set all the bits to 1, you will receive all the multicast address packets.

7 6 5 4 3 2 1 0 bit

MAR8 MID 7 MID 6 MID 5 MID 4 MID 3 MID 2 MID 1 MID 0MAR9 MID 15 MID 14 MID 13 MID 12 MID 11 MID 10 MID 9 MID 8MAR10 MID 23 MID 22 MID 21 MID 20 MID 19 MID 18 MID 17 MID 16MAR11 MID 31 MID 30 MID 29 MID 28 MID 27 MID 26 MID 25 MID 24MAR12 MID 39 MID 38 MID 37 MID 36 MID 35 MID 34 MID 33 MID 32MAR13 MID 47 MID 46 MID 45 MID 44 MID 43 MID 42 MID 41 MID 40MAR14 MID 55 MID 54 MID 53 MID 52 MID 51 MID 50 MID 49 MID 48MAR15 MID 63 MID 62 MID 61 MID 60 MID 59 MID 58 MID 57 MID 56



60


• Caution with multicast address function

- Generator polynomial of CRC is the same as CRC of 32 bits that is added to the end of

packet.

- G(x) = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

- When all the bits of destination address are 1, the packets will be received irrespective of

multicast address because they are broadcast address packets.

61


Buffer Memory Port Register: BMPR8BMPR8: Address 0110_0010h (access: Byte/Half-word)

This is the data port to transfer send and receive data between FR core and buffer memory.

• This is the data port to transfer send and receive data between FR core and buffer memory.

This register can be accessed using word access only.

• Setting byte swap bit (DLCR7.BYTE SWAP) will enable you to transpose the byte order of

MSB and LSB of this register.

7 6 5 4 3 2 1 0 bit

BMP 7 BMP 6 BMP 5 BMP 4 BMP 3 BMP 2 BMP 1 BMP 0BMP 15 BMP 14 BMP 13 BMP 12 BMP 11 BMP 10 BMP 9 BMP 8BMP 23 BMP 22 BMP 21 BMP 20 BMP 19 BMP 18 BMP 17 BMP 16BMP 31 BMP 30 BMP 29 BMP 28 BMP 27 BMP 26 BMP 25 BMP 24



62


Transmitted Packet Count Register: BMPR10BMPR10:Address 0110_000Ah (access: Byte/Half-word)

This is the register to set start transmission bit and transmitted packet count.

bit 7: Start transmission bit

• Set it after transferring the transmitted packet from FR core to the send buffer.

bit 6-0: Transmitted packet count

• Each time one packet transmission is completed after the start of transmission, the count

is decremented, and it displays the number of packets yet to be transmitted. When the

transmission of all the packets is complete, the count will become 00H.

• LAN controller is able to start the multiple packets transmission in a single command

for the transmission. Write into this register the number of transmitted packets (the

number of packets transferred to the buffer memory) while setting TMST bit.

7 6 5 4 3 2 1 0 bit

TMST TX PKTCNT 6

TX PKTCNT 5

TX PKTCNT 4

TX PKTCNT 3

TX PKTCNT 2

TX PKTCNT 1

TX PKTCNT 0


R0/W R/W R/W R/W R/W R/W R/W R/W Attribute

TMST Write operation

0 No effect

1 Start packet transmission

63


DMA Enable Register:BMPR12BMPR12:Address 0110_000Ch (access: Byte/Half-word)

This is the register to control DMA transfer between FR core and LAN controller.


bit 1: DMA RENA


7 6 5 4 3 2 1 0 bit- - - - - - DMA

RENA-


R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R/W R0,WX Attribute

TMST Write operation

0 DMA read operation disable

1 DMA read (read the receive buffer) operation enable

64


Receive Buffer Pointer Control Register: BMPR14BMPR14:Address 0110_000Eh (access: Byte/Half-word)

This is the register to control DMA transfer between FR core and LAN controller.


bit 2: Receive buffer pointer skip

• When the receive buffer pointer skip bit is "1", it means that the status is transient from

the time 1 was written into this bit until the skip is complete.

• After setting the receive buffer pointer skip bit to "1", this bit will be automatically

cleared when the skip operation is complete. And if the packet you tried to skip is the

end packet in the receive buffer, the receive buffer pointer will set buffer empty bit

(DLCR5.BUF EMP) after skipping.

bit 1-0: Undefined....Writing does not affect the operation. The read value is always “0”.

7 6 5 4 3 2 1 0 bit

- - - - - SKI PRX PKT

- -


R0,WX R0,WX R0,WX R0,WX R0,WX R/W R0/WX R0,WX Attribute

SKI PRX PKT Read operation Write operation

0 Receive buffer pointer skip complete No effect, the receive buffer pointer is not skipped.

1 Receive buffer pointer being skipped (being updated)

Skip the receive buffer pointer to the top of the next packet

65


3.3 Operation

Figure 3.3-1 About buffer memory

For LAN'3fBuffer memory transfer, since it is processed by hardware,

users send and receive between register'3fbuffer memory register.

Buffer memory report register(BNPR8)

Receive buffer memory(3072Byte)

Send buffer memory(1536Byte)

Receive data packet n

Receive data packet n+1



Free spaceNext receive datapacket is stored

Packet length

Packet length

Packet length

Packet length

Mem

ory

LAN

Data link controller

(Hardware processing)

Buffer m

emory m

anager (H

ardware processing)

Send data packet n

Send data packet n+1

Send data packet n+2

Free spaceNext send datapacket is stored

Packet length

Packet length

Packet length

DMA<- ->FR

Processing which is done automatically

- Conversion from parallel data to serial data

- Generate and add 64 bit preamble code

- Generate and add 32 bit CRC code

- Output to LAN

Processing which is done automatically

- Conversion from serial data to parallel data

- Compare addresses- Check and remove 32 bit

CRC code- Remove 64 bit preamble

code- Transfer to the receive

buffer

66


Format For The Receive Data Packet

Format For Packet Length (4 byte)

• Packet length is denoted in 11 bits, so write "0" into the first 2 byte and high-order 5 bits of

the third byte.

• In transmission: Write into packet length the data length of address+data lengh+data body.

• In reception: Into the head of each receive data, data length (address+data length+data

body) information of 4 byte will be written.

Packet Format

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bitPacket length

Destination address (high-order 4 byte)

Destination address (low-order 2 byte) Source address (high-order 2 byte)

Source address (low-order 4 byte)

Length/type Data bodyData body

Snip

Data body

CRC

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Packet length

11Bits

Preamble Destination Address

Source Address

Length/Type *1

Data Body CRC

Start Frame Delimiter

7 bytes 1 byte 6 bytes 6 bytes 2 bytes 46 - 1500 bytes 4 bytes

IEEE802.3 packet format

Send data *2

Transmitted packet

Received packet

Receive data *3

1 byte = 8 bits

*1: This is the field to set length/type of data body. In LAN controller operation, this value has nomeaning.

*2: Add byte count information of this send data to the head of send data and transfer to the send buffer.

*3: Byte count of this receive data will be set to the data length in the reception status.

67


3.3.1 Transmission Flow (Host → Buffer Memory)

Figure 3.3-2 Main processing

Figure 3.3-3 Interrupt

7. Automatically added by the hardware- Preamble- Start Frame Delimiter- CRC

4. Put the built send data on the buffer(Transfer by program/DMA transfer)

Have all the packets in

the buffer been transmitted? (Hardware processing)

5. Enable Transmit O.K. interrupt occurrence(Interrupt occurs when transmission is completed.)

Yes

6. Write the number of transmitted packets to register(Start transmission)

1. Clear status

3. Setting the operation mode of LAN controller

2. Build send data on memory (RAM)- Destination Address- Source Address- Data Length- Data Body

Start interrupts

TMT OK

9. Disable interrupts

8. Clear various types of status (transmit O.K. status, etc.)

10. Notify the transmission completion to the upper network protocol

RETI (Return)

Start interrupts

ERROR

Error processing

RETI (Return)

68


Procedure

[Packet transmission]

Main processing

1. Clear each status

1) Setting the transmission status register (DLCR0):Setting value0x8A

2) Write "1" (normal sending and receiving operation) into loop back control bit (DLCR4.-

LBC).

2. Build send data on memory (RAM)

1) Destination address

2) Source address

3) Length/type

4) Data body setting

*If the send data length cannot be divided by 4 byte, add dummy data to the end of the

send data.

3. Setting the operation mode of LAN controller

Bit Value Position of DLCR0

TMT OK "1" bit 7:

LTE COL "1" bit 3:

RETRY OVER "1" bit 1:

Table 3.3-1 Setting the control register 2 (DLCR7)


RBNK1 "1" (select bank 2) bit 3

RBNK2 "1" (select bank 2) bit 2

BYTESWAP Set byte swap if necessary bit 0

Preamble Destination Address

Source Address

Length/Type

Data Body CRC

Start Frame Delimiter

7 bytes 1 byte 6 bytes 6 bytes 2 bytes 46 - 1500 bytes 4 bytes

69


4. Conduct DMA transfer to put send data on the buffer from external memory.

DMA setting (transmission example)

Configure the following settings for DMAC of FR core.

1) Transfer-source address setting:

Set transfer-source address in transfer-source address setting register

(DMASAn.DMASA).

2) Transfer-destination address setting:

Set buffer memory port register (BMPR8) of MAC in transfer-destination address setting

register (DMADAn.DMADA).

3) Enable DMA operation

Set "1" (enable all the channels DMA transfer) in DMAC total operation enable register

(DMACR,DMAE).

4) DMAC control/status register B (DMACBn) settings

*Setting other than shown below means initial value.

a. TYPE: Transfer type setting

TYPE[1:0] = "00"(two-cycle transfer)

b. MODE: Transfer mode setting

MOD[1:0] = "01"(burst transfer mode)

c. WS: Transfer data width selection

WS[1:0] = "10"(transfer in WORD unit)

d. SADM: Specifying transfer-source address count mode

SADM = "0"(transfer-source address will increase)

Note) It is necessary to be compliant with the transfer-source buffer.

e. Reload and interrupt settings

Configure the settings if necessary.

f. SASZ: Specifying transfer-source address count size

SASZ = "0x04"(transfer address increase and decrease range :4)

Note) It is necessary to be compliant with the transfer-source buffer.

g. DASZ: Specifying transfer-destination address count size

DASZ = "0x00"(transfer address increase and decrease range :0)

5) DMAC control/status register A (DMACAn) settings


a. DENB : DMA operation enable bit

DENB = "1"(enable corresponding channel DMA operation)

b. IS : Select transfer trigger

IS[4:0] = "00000"(only software transfer request enabled)

c. BLK:Specifying block size

BLK[3:0] = "0x1"(block transfer is not conducted)

d. DTC : Transfer count register

Set send data length.

Example) For 1536byte,1536/word = 384

DTC = "0x180

70


6) Transfer request

DMACAn.STRG:Transfer request

STRG = "1"(DMA start request)

5. Transfer data to buffer (DMA setting) Write the number of transmitted packets

1) Setting the transmission interrupt enable register (DLCR2): Setting value0x8E

6. Start transmission

1) Write "0" (LAN controller is ready for sending and receiving) into enable data link

controller bit (DLCR6.-ENA DLC).

3) Write into transmitted packet count bit (BMPR10.TX PKT CNTn) the number of packets

to be transmitted from now.

4) Write "1" (start packet transmission) into start transmission bit (BMPR10.TMST).

(Do not transfer the next send data to the send buffer or start the transmission operation

until the packet transmission is completed)

5) Calculating the rest of the send buffer, repeat the processing of 3) and 4) until all the data

is transferred.

(7. Hardware processing)

1) Convert to packet transmission format

By adding preamble, start frame delimiter and CRC, it is transmitted onto LAN network.

2) Packet transmission is carried out until the transmitted packet count bit (BMPR10.TX

PKT CNTn) becomes "0".

(Each time one packet is transmitted, the count is automatically decremented)

3) When the transmission is completed, transmission O.K. bit (DLCR0.TMT OK) becomes

"1".


ENA TMT OK "1" bit 7

ENA LTE COL "1" bit 3

ENA COL "1" bit 2

ENA RETRY OVER "1" bit 1

71


Transmission complete (interrupt occurred)

8. Status clear

1) Setting the transmission status register (DLCR0):Setting value0x8A


1) Write "0" (TMT OK interrupt occurrence disable) into Transmit O.K. interrupt

occurrence enable bit (DLCR2.ENA TMT OK).

10. Notify to upper level

1) If necessary, notify the transmission complete to the upper level network protocol.


TMT OK "1" bit 7

LTE COL "1" bit 3

RETRY OVER "1" bit 1

72


3.3.2 Reception Flow (Buffer Memory → Host)Main processing

Interrupts

2. Enable different types of interrupts

4. Start reception (automatically)(Interrupt occurs when reception is completed.)

5. Hardware processing- Checks the packet is to the local.- Deletes the preamble and CRC, and transfers it to the buffer memory.

3. Setting LAN controller register

1. Initial process (Clearing status)

Start interrupts

PKT-RDY

6. Switch to disable interrupts

10. Buffer empty

9. Read data (DMA transfer) (Hardware processing) Receive 1 packets

12. Clear various types of status

13. Enable interrupts

RETI (Return)

Start interrupts

ERROR

Error processing

RETI (Return)

No

Yes (Buffer area is empty)

7. Read packet length

11. DMA operation disable

8. DMA operation enable

73


Procedure

[Packet received]

Main processing

1. Clear each status

1) Setting the receive status register (DLCR1):Setting value0xFF

2. Enable different types of interrupts

1) Setting the receive interrupts enable register (DLCR3): Setting value0xCA

3. Setting LAN controller register

1) Write "1" (normal sending and receiving operation) into loop back control bit

(DLCR4.LBC).

2) In address match mode bit (DLCR5.AM[1:0]), set to "10" (receive the packet selected)

or to "11" (receive all the packets).

3) Write "0" (LAN controller is ready for sending and receiving) into enable data link

controller bit (DLCR6.ENA DLC).


• Start receiving


• Check destination address with data link controller and confirm if the packet is

addressed to the local.


PKT RDY "1" bit 7

RX ERR "1" bit 6

FIL DROP "1" bit 5

RX LNG PKT "1" bit 4

RX SRT PKT "1" bit 3

ALG ERR "1" bit 2

CRC ERR "1" bit 1

OVRFLO "1" bit 0


ENA PKT RDY "1" bit 7

ENA RX ERR "1" bit 6

ENA FIL DROP "0" bit 5

ENA RX LNG PKT "0" bit 4

ENA RX SRT PKT "1" bit 3

ENA ALG ERR "0" bit 2

ENA CRC ERR "1" bit 1

ENA OVRFLO "0" bit 0

74


• For the packet addressed to the local, transfer to the buffer memory by removing preamble

and CRC.

• At the same time, check for error in CRC, short packet, alignment, respectively, and if an

error is detected, set the corresponding error status bit of the receive status register

(DLCR1) and erase the packet data transmitted to the buffer memory.

• When the reception is properly completed and all of the packet data is transferred to the

buffer memory, the buffer memory manager will write the status information of 4 byte into

the head of the packet data in the buffer memory, and packet ready bit (DLCR1.PKT RDY)

will become "1".

Reception complete (interrupts occur)


1) Write "00"H into reception interrupts enable register (DLCR3). (Disable all reception

interrupts)

7. Read to disable packet

1) Read packet length from buffer memory port register (BMPR8).

DMA transfer processing

8. DMA operation enable

1) DMA setting (reception example)

Configure the following settings for DMAC of FR core.

1. Transfer-source address setting:

Set buffer memory port register (BMPR8) of MAC in transfer-source address setting

register (DMASA0.DMASA).

2. Transfer-destination address setting:

Set transfer-destination address in transfer-destination address setting register

(DMADA0.DMADA).

3. Enable DMA operation

Set "1" (enable all the channels DMA transfer) in DMAC total operation enable

register (DMACR,DMAE).

DMAC control/status register B (DMACB0) settings


a. TYPE: Transfer type setting

TYPE[1:0] = "10"(fly-by:IO to memory transfer)

b. MOD[1:0] = "10"(demand transfer mode)

c. WS: Transfer data width selection

WS[1:0] = "10"(transfer in WORD unit)

d. DADM: Specifying transfer-destination address count mode

DADM = "0"(transfer-source address will increase)

Note) It is necessary to be compliant with the transfer-destination buffer.

e. Reload and interrupt settings

Configure the settings if necessary.

75


f. SASZ: Specifying transfer-source address count size

SASZ = "0x00"(transfer address increase and decrease range :0)

g. DASZ: Specifying transfer-destination address count size

DASZ = "0x04"(transfer address increase and decrease range :4)

Note) It is necessary to be compliant with the transfer-destination buffer.

5. DMAC control/status register A (DMACA0) settings


a. DENB : DMA operation enable bit

DENB = "1"(enable corresponding channel DMA operation)

b. IS : Select transfer trigger

IS[4:0] = "01110"(DREQ H level)

c. BLK:Specifying block size

BLK[3:0] = "0x1"(block transfer is not conducted)

d. DTC : Transfer count register

Set receive data length.

Example)For 1536byte,1536/word = 384

DTC = "0xh180

6. Transfer request

• Write "1" (DMA read operation enable) into DMA enable bit (BMPR12 -DMA

RENA).

9. Read data (DMA transfer)

*If the data length of the packet received cannot be divided by 32 bits, dummy data (value

is indeterminate) is added to the end of the receive data and is stored in the buffer

memory. If the value of data length in the receive status is 007FH, for example, in host

system, read 32 word of buffer memory port register (BMPR8) and delete the last 1

byte.

10. Judgment of buffer empty

1) If buffer empty bit (DLCR5.BUF EMP) is "0" (valid data are still in the receive buffer

memory)

2) Repeat the processing for 1) until buffer empty bit (DLCR5.BUF EMP) becomes "0"

(valid data are not in the receive buffer memory).

11. DMA operation disable

1) Write "0" (DMA operation disable) into DMA REMA bit (BMPR12. DMA RENA).

76


12. Clear status

1) Setting the receive status register (DLCR1): Setting value0xFF

13. Enable interrupts

1) Setting the receive interrupts enable register (DLCR3): Setting value0xCA


PKT RDY "1" bit 7

RX ERR "1" bit 6

FIL DROP "1" bit 5

RX LNG PKT "1" bit 4

RX SRT PKT "1" bit 3

ALG ERR "1" bit 2

CRC ERR "1" bit 1

OVRFLO "1" bit 0


ENA PKT RDY "1" bit 7

ENA RX ERR "1" bit 6

ENA FIL DROP "0" bit 5

ENA RX LNG PKT "0" bit 4

ENA RX SRT PKT "1" bit 3

ENA ALG ERR "0" bit 2

ENA CRC ERR "1" bit 1

ENA OVRFLO "0" bit 0

77


3.4 Packet Filter

3.4.1 Overview

Overview, Features

This LAN controller is provided with two types of tables, [protocol type] and [L3/L4 filter

table], and enables the filtering based on the following information.

• Protocol type

(Type field of Ethernet)Protocol type(Type field of Ethernet)

• IP address

• TCP/UDP port number

• ICMP message typeL3/L4 filter table (16 items registerable)

Chip MB91401L3/L4 filter table

16 items registerableIn L3/L4 filter table, registration must have been made in advance. 1) Write the registration data into data register (FL_DATA).2) Give write instructions by command register (FL_CMD).

Destination address: 192.168.1.1

Packet

Pass

Destination address: 192.168.1.2 Drop because it is registered in L3/L4 filter table

Destination address: Drop 192.168.1.2Transmission source address: Drop 163.170.2.3

78


3.4.2 Table

3.4.2.1 Protocol Type TableThis is used in filtering by protocol type (the number of up to 8 items is registerable).

Overall view

It is the table of 8 entries in total.

Comparisons with table is made in the order of record number 0 to 7 and the comparisons will

be terminated at the time they are matched.

Configuration

Items to be settable for table

1) [P_TYPE field] [P_TYPE:16bit]

Set the value to denote the protocol that will be for filtering.

The value of IP protocol (IPv4:0x0800,IPv6:0x86DD) is not referred by this protocol type

table. So configuring the settings will be meaningless.

And, PPPoE (discovery stage:0x8863, session stage:0x8864)

is processed by the designation from filter mode setting register, so it is not set in this filed.

2) [P_Pass_Drop field] [P_Pass_Drop:1bit]

This is the setting for filtering. Specify whether to drop or pass when it is matched with the

value of P_TYPE field.

When it is "1" --- Drop (this protocol does not use this record)

When it is "0" --- Pass (this protocol is used)

3) [P_Valid field] [P_Valid:1bit]

This is entry valid flag. Set "0" to P_ Valid field for the entry number unused.

When it is "0" --- This record is invalid.

When it is "1" --- This record is valid.

Record 0 Record 1 - Record 7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit- (2) - (1) - (3)

79


3.4.2.2 L3/L4 Filter Table

This is used when filtering by L3/L4 packet information. (Up to 16 items are registerable)

Overall view

Twelve data registers constitute one record and the table is of 16 entries in total.

Comparisons with table is made in the order of record number 0 to 15 and the comparisons will

be terminated at the time they are matched.

Configuration of one record

Record 0 Record 1 - Record 15SRC0

SRC1

SRC2

SRC3

DES0

DES1

DES2

DES3

PORT LOWER

SRC0SRC1SRC2SRC3DES0DES1DES2DES3DES PORT LOWER SRC PORT LOWERDES PORT UPPER SRC PORT UPPER

P Filter setting M T VPD ACK

80


3.4.2.2.1 Table Details

SRC0,SRC1,SRC2,SRC3:Transmission Source IP fieldThis is the field to set transmission source IP address.

SRC0,SRC1,SRC2,SRC3: Transmission source IP address

Set transmission source IP address.

However, if you make comparisons by masking for range specification, set "0" to the range of

the IP address that is not masked.

(Example)

• If you specify the range of 192.168.1.0-192.168.1.255, define 192.168.1.0 for IP field. (Set

255.255.255.0 for filter subnet register (FL_SUBNET))

• If you also specify the range of 192.168.1.0-192.168.1.31, define 192.168.1.0 for IP field.

(Set 255.255.255.224 for filter subnet register (FL_SUBNET))

DES0,DES1,DES2,DES3: Destination IP FieldThis is the field to set destination IP address.

DES0,DES1,DES2,DES3: Destination IP address

Set destination IP address.

However, if you specify the range, set "0" to the range of the IP address that is not masked.

(The method to specify is the same as transmission source IP filed)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bitSRC0

SRC1

SRC2

SRC3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bitDES0

DES1

DES2

DES3

81


PORT LOWER: Lower Limit Port Number FieldThis is the field to set the lower limit of PORT number.

bit31-16: DES PORT LOWER

• Specify the lower limit of destination PORT number.

• For the comparison of destination port number of TCP or UDP, if you do not specify

the range, set the destination port number.

- If filtering is for TCPSet the lower limit of destination number if you specify the range.

- If filtering is for ICMPInput the message type of ICMP.

If MR16bit of data register is "1"(specify the range), set DES PORT UPPER, too.

bit15-0: SRC PORT LOWER

• Specify the lower limit of transmission source PORT number.

• For the comparison of transmission source port number of TCP or UDP, if you do not

specify the range (when MR15 bit of data register is "0"), set the transmission source

port number. Set the lower limit of tansmission source port number if you specify the

range.

If MR15 bit of data register is "1" (specify the range), set SRC PORT UPPER, too.

Setting example

• If you specify the range of transmission source PORT number (if you set 10-20)

• If you specify singularly instead of specifying the range of transmission source PORT

number (if you set 15)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bitDES PORT LOWER SRC PORT LOWER

MR15 1

SRC PORT LOWER 10

SRC PORT UPPER 20

MR15 0

SRC PORT LOWER 15

SRC PORT UPPER 0

82


PORT UPPER:Upper Limit Port Number FieldThis is the field to set the upper limit of PORT number.

bit31-16: DES PORT UPPER

• Specify the upper limit of destination PORT number.

• Set it if you specify the range(if MR16 bit of data register is "1")

• Set "0" as initial value.

• Set the value larger than lower limit port number (DES PORT LOWER). In the case of

lower limit port number > upper limit port number, it will be ignored.

bit15-0: SRC PORT UPPER

• Specify the upper limit of transmission source PORT number.

• Set it if you specify the range(if MR15 bit of data register is "1")

• Set "0" as initial value.

• Set the value larger than lower limit port number (SRC PORT LOWER). In the case of

lower limit port number > upper limit port number, it will be ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bitDES PORT UPPER SRC PORT UPPER

83


FILTERING1: Filtering Field 1This is the field to configure the settings for filtering.

bit22-20: P

• Specify the protocol that is for filtering.

bit 19: MR16

• Specify the range for destination port number of TCP/UDP and make comparisons

bit 18: MR15

• Specify the range for transmission source port number of TCP/UDP and make

comparisons

bit 17: MR14

• Comparison of destination port number of TCP/UDP

bit 16: MR13

• Comparison of transmission source port number of TCP/UDP

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bitP MR

16MR15

MR14

MR13

MR12

MR11

MR10

MR9

MR8

MR7

MR6

MR5

MR4

MR3

MR2

MR1

MR0

T V

P Description

0 All the protocols

1 TCP

2 UDP

3 TCP or UDP

4 ICMP

MR16 Description

0 Make no comparisons

1 Make comparisons

MR15 Description


1 Make comparisons

MR14 Description

0 Make comparisons


MR13 Description

0 Make comparisons


84


bit 15: MR12

• Comparison of IPv6 destination address[127:112] (FP,TLA ID)

bit 14: MR11

• Comparison of IPv6 destination address[111:80] (NLA, ID)

bit 13: MR10

• Comparison of IPv6 destination address[79:64] (SLA ID)

bit 12: MR9

• Comparison of IPv6 destination address[63:0] (interface ID)

bit 11: MR8

• Comparison of IPv6 transmission source address[127:112] (FP,TLA ID)

bit 10: MR7

• Comparison of IPv6 transmission source address[111:80] (NLA ID)

MR12 Description

0 Make comparisons


MR11 Description

0 Make comparisons


MR10 Description

0 Make comparisons


MR9 Description

0 Make comparisons


MR8 Description

0 Make comparisons


MR7 Description

0 Make comparisons


85


bit 9: MR6

• Comparison of IPv6 transmission source address[79:64] (SLA ID)

bit 8: MR5

• Comparison of IPv6 transmission source address[63:0] (interface ID)

bit 7: MR4

• Make comparisons by masking IPv4 destination address for specifying the range

bit 6: MR3

• Make comparisons by masking IPv4 transmission source address for specifying the

range

bit 5: MR2

• Comparison of IPv4 destination address

bit 4: MR1

• Comparison of IPv4 transmission source address

MR6 Description

0 Make comparisons


MR5 Description

0 Make comparisons


MR4 Description


1 Make comparisons

MR3 Description


1 Make comparisons

MR2 Description

0 Make comparisons


MR1 Description

0 Make comparisons


86


bit 2: MR0

• Comparison of ICMP Type

bit 1: T

• Configure the settings for which mode to communicate in, IPv4 or IPv6.

bit 0: V

• Entry Valid Flag

• Set "0" for entry that is not used.

MR0 Description

0 Make comparisons


T Description

0 IPv6

1 IPv4

V Description

0 This record is invalid.

1 This record is valid.

87


FILTERING2: Filtering Field 2This is the field to configure the settings for filtering.

bit 8: PD

• Specify the handling of the message matching the criteria.

bit 5: ACK1

• It is used to check ACK flag for the case of TCP.

bit 4: ACK0

• It is used to configure the settings for the filtering according to ACK flag for the case of

TCP.

31 8 7 6 5 4 3 2 1 0 bitPD ACK

1ACK

0

PD Description

0 Pass

1 Drop

ACK1 Description

0 Make a check on ACK flag.

1 Make no check on ACK flag.

ACK0 Description

0 Filter the packet for which ACK flag is not on.

1 Filter the packet for which ACK flag is on.

88


For MR field, there is setting enabled/disabled relationship as shown in the following table. In

the table, O means that setting is enabled and the setting of bit is required for the protocol that

is covered. X means that setting is disabled and the setting is not required. For the ones that do

not require the setting, set them to "Make no comparisons".

IPv4 IPv6

Bit TCP UDP ICMP TCP UDP ICMP

16 Make comparisons by specifying the range for destination port number of TCP/UDP

O O - - O O - -

15 Make comparisons by specifying the range for transmission source port number of TCP/UDP

O O - - O O - -

14 Comparison of destination port number of TCP/UDP O O - - O O - -

13 Comparison of transmission source port number of TCP/UDP O O - - O O - -

12 Comparison of IPv6 destination address[127:112] (FP,TLA ID) - - - - O O O O

11 Comparison of IPv6 destination address[111:80] (NLA ID) - - - - O O O O

10 Comparison of IPv6 destination address[79:64] (SLA ID) - - - - O O O O

9 Comparison of IPv6 destination address[63:0] (interface ID) - - - - O O O O

8 Comparison of IPv6 transmission source address[127:112] (FP,TLA ID)

- - - - O O O O

7 Comparison of IPv6 transmission source address[111:80] (NLA ID)

- - - - O O O O

6 Comparison of IPv6 transmission source address[79:64] (SLA ID)

- - - - O O O O

5 Comparison of IPv6 transmission source address[63:0] (interface ID)

- - - - O O O O

4 Make comparisons by masking IPv4 destination address for specifying the range

O O O O - - - -

3 Make comparisons by masking IPv4 transmission source address for specifying the range

O O O O - - - -

2 Comparison of IPv4 destination address O O O O - - - -

1 Comparison of IPv4 transmission source address O O O O - - - -

0 Comparison of ICMP type - - O - - - O -

89


3.4.3 Register List

White space: Unallocated portion

Word access only

Address 32 00x0110_0014 FL_CMD Filter command register

0x0110_0018 FL_STATUS Filter status register

0x0110_001C FL_DATA Filter data register

0x0110_0020 FL_CONTROL Filter control register

0x0110_0024 FL_SUBNET Filter subnet register

90


3.4.4 Register DetailExplanation of the code expressing access limits to each bit of the register

[Code]

R : Read permitted

R0 : Always 0

R1 : Always 1

RX: Indeterminate

W : Write permitted

W0: Always write 0

W1: Always write 1

WX: Write invalid

[Combination] "/" and ",


R,W: The significance of the bit changes according to whether it is read or write

[Support for read modify write] using "(" ")

R(RM1)/W: Possible to read written value (The reading is always 1 during RMW)

R(RM1),W: Read is possible (always 1 during RMW), write is possible

91


FL_CMD: Command registerFL_CMD: Address 0110_0014h (Access: Word)

This register indicates the table access.

bit31-16: Undefined

• The read value is indeterminate.

• The written value has no effect on the operation.

bit15-12: id

• A field that indicates the entry position (number) of the filter.

• When the value of item [bit:11-8] is 12, specify a range of 0 - 7 for setting the protocol

type table (as protocol type table has 8 entries).

• The priority of the table is top to bottom (according to the id).

bit11-8: item

Item is a field to specify the content to be written in each table. In L3/L4 filter table, this is

a required field to specify which part of one entry will be written, as writing of the table

need to be done more than once in case of 1 word (32 bits) data. Entry specification of

protocol type table is also merged in this field.

bit 7-5: Undefined


• The written value does not affect the operation.

31 16 12 11 8 7 5 4 3 1 0 bit

reserved id item reserved table reserved cmdX 0 0 X 0 X 0 Initial

valueRX/WX R/W R/W RX/WX R/W RX/WX R/W Attribute

id Write operation

0 - 15 The instruction to write in the set position

itemWrite operation

Table to be written location

0 - 3 L3/L4 Filter table(For table bit [Bit:4], set 0)

Instruction to write in the SRC0 part

4 - 7 Instruction to write in the DES0 part

8 Instruction to write in the PORT LOWER part

9 Instruction to write in the PORT UPPER part

10 Instruction to write in the FILTERING1 part

11 Instruction to write in the FILTERING2 part

12 Protocol type table(For table bit [Bit:4], set 1)

Instruction to write in the P_TYPE part

92


bit4: table

• Specify a table according to the location where above item bit [Bit11-8] is written

bit 3-1: Undefined



bit 0: cmd

• Command field is the write/read instruction.

table Write operation

0 L3/L4 filter table is the target (for item bit [Bit 11:8], set 0-11)

1 Protocol type table is the target (for item bit [Bit 11:8], set 12)

cmd Write operation

0 read instruction

1 write instruction

93


FL_STATUS: Status registerFL_STATUS: Address 0110_0018h (Access: Word)

This register is used for access controlling to the table.

bit31-1: Undefined



bit 0: status

• When new data is going to be written, be sure that this status value is "0".

31 1 0 bit

reserved statusX 0 Initial

valueRX/WX R Attribute

status Read operation

0 Write operation is not being carried out now

1 Write operation is running now

94


FL_DATA: Data registerFL_DATA: Address 0110_001Ch (Access: Word)

This is a 32 bit data field that read and write to/from the L3/L4 filter table and the protocol type

table.

The content of the data to be written to the data register depends on the value in the item field

of FL_CMD register.

31 0 bit

0 Initial value

R/W Attribute

Table 3.4-1 Setting of L3/L4 Filter table (1 / 2)

item bitCorrespondence

to L3/L4 filter tableTarget Function

0 [31:0] SRC0 IPv4/IPv6 Transmission source IP address

1 [31:0] SRC1 IPv6 Transmission source address (only IPv6)

2 [31:0] SRC2 IPv6

3 [31:0] SRC3 IPv6

4 [31:0] DES0 IPv4/IPv6 Destination IP address

5 [31:0] DES1 IPv6 Destination IP address (only IPv6)

6 [31:0] DES2 IPv6

7 [31:0] DES3 IPv6

8 [31:16] DES PORT LOWER IPv4/IPv6 Lower limit of destination IP address PORT number

[15:0] SRC PORT LOWER IPv4/IPv6 Lower limit of transmission source PORT number

9 [31:16] DES PORT UPPER IPv4/IPv6 Upper limit of destination PORT number

[15:0] SRC PORT UPPER IPv4/IPv6 Upper limit of transmission source PORT number

95


10 [31:23] reserved

[22:20] P IPv4/IPv6 Protocol to be filtered

[19] MR16 IPv4/IPv6 Make comparisons by specifying the range for destination port number of TCP/UDP

[18] MR15 IPv4/IPv6 Make comparisons by specifying the range for transmission source port number of TCP/UDP

[17] MR14 IPv4/IPv6 Comparison of destination port number of TCP/UDP

[16] MR13 IPv4/IPv6 Comparison of transmission source port number of TCP/UDP

[15] MR12 IPv6 Comparison of IPv6 destination address[127:112] (FP,TLA ID)

[14] MR11 IPv6 Comparison of IPv6 destination address[111:80] (NLA ID)

[13] MR10 IPv6 Comparison of IPv6 destination address[79:64] (SLA ID)

[12] MR9 IPv6 Comparison of IPv6 destination address[63:0] (interface ID)

[11] MR8 IPv6 Comparison of IPv6 transmission source address[127:112] (FP,TLA ID)

[10] MR7 IPv6 Comparison of IPv6 transmission source address[111:80] (NLA ID)

[9] MR6 IPv6 Comparison of IPv6 transmission source address[79:64] (SLA ID)

[8] MR5 IPv6 Comparison of IPv6 transmission source address[63:0] (interface ID)

[7] MR4 IPv4 Make comparisons by masking IPv4 destination address for specifying the range

10 [6] MR3 IPv4 Make comparisons by masking IPv4 transmission source address for specifying the range

[5] MR2 IPv4 Comparison of IPv4 destination address

[4] MR1 IPv4 Comparison of IPv4 transmission source address

[3] reserved

[2] MR0 IPv4/IPv6 Comparison of ICMP type

[1] T IPv4/IPv6 Communication mode

[0] V IPv4/IPv6 Valid entry flag

11 [31:9] reserved

[8] PD IPv4/IPv6 Response to the message that matches the condition

[7:6] reserved

[5] ACK1 IPv4/IPv6 Check ACK flag

[4] ACK_0 IPv4/IPv6 Relationship between the ACK flag and the packet filter(Active when ACK flag is checked)

[3:0] reserved

Table 3.4-1 Setting of L3/L4 Filter table (2 / 2)

item bitCorrespondence

to L3/L4 filter tableTarget Function

96


Table 3.4-2 Setting of the protocol type table

item bitCorrespondence to protocol type table

Target Function

12 [31:25] reserved

[24] P_Pass_Drop IPv4/IPv6 Response to the message that matches the condition

[23:20] reserved

[19:4] P_TYPE[15:0] IPv4/IPv6 Value that shows the protocol

[3:1] reserved

[0] P_Valid IPv4/IPv6 Valid entry flag

97


FL_CONTROL: Register for filter mode settingFL_CONTROL: Address 0110_0020h (Access: Word)

This register specifies how to handle the packets relevant to each operation mode of the filters.

bit 10: UDF field

• There should not be a situation that TCP/UDP/IP headers are not successfully identified,

but it happens when IP header is broken up in the middle of the IP address.

bit 9: tunnel field

Process setting for packets where IPv6 is encapsulated in IPv4

bit 8: fragment field

• When the value is "0," first fragment packet including TCP/UDP header will be filtered

in L3/L4 table. Packets after the second one will not be filtered out with the parameter of

TCP/UDP port number.

10 9 8 7 6 5 4 3 2 1 0 bit

UDF tunnel fragment L3/L4 table

p_type discovery IPv4 drop IPv4 pass IPv6 drop IPv6 pass IP i/o

0 0 0 0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Attribute

UDF Write operation

0 -

1 Unidentified TCP/UDP/IP packet will be dropped.

tunnel Write operation

0 (IPv4 mode) IPv6 is considered to be an unknown protocol, and the IP address is compared against L3/L4 filter table at IPv4 address which is the tunnel header of the packet, but IPv6 address is not compared. In this case, only IPv4 address is filtered by L3/L4 filtering.

1 (IPv6 mode) IP address is compared against L3/L4 filter table at IPv6 address of the packet, but IPv4 address is not compared.

fragment Write operation

0 Fragment packet will pass through.

1 Fragment packet will be unconditionally dropped.

98


bit 7: L3/L4 table field

Process setting for packets without entries that match the L3/L4 table

bit 6: p_type field

Process setting for packets without entries that match to the protocol type table

bit 5: discovery field

xbit 4: IPv4 drop field

Process setting when "0" is set to discovery field [Bit5] and the upper layer of the packets

in the PPPoE session stage is IPv4 protocol

bit 3: IPv4 pass field

Process setting when "0" is set to discovery field [Bit5] and the upper layer of the packets


bit 2: IPv6 drop field

Process setting when the upper layer of the packets in the PPPoE session stage is IPv6

protocol

bit 1: IPv6 pass field

Process setting when "0" is set to IPv6 drop field [Bit2] and the upper layer of the packets

L3/L4 table Write operation

0 Packets will pass through.

1 Packets will be dropped.

p_type Write operation



discovery Write operation

0 Will pass through unconditionally.

1 Data packet in PPPoE discovery stage will be dropped.

IPv4 drop Write operation

0 Follows the setting of IPv6 pass field [bit3] below.


IPv4 pass Write operation

0 L3/L4 filter table will be referred.

1 Passed through without processing.

IPv6 drop Write operation

0 Follows the setting of IPv6 pass field [bit1] below.


99



bit 0: IP i/o field

Process setting when the upper layer of the packets in the PPPoE session stage is neither

IPv4 nor IPv6 protocol

IPv6 pass Write operation

0 L3/L4 Filter Table will be referred.

1 Passed through without processing.

IP i/o Write operation



100


FL_SUBNET: Filter subnet registerFL_SUBNET: Address 0110_0024h (Access: Word)

This is a register to register the range specification of the filter.

This register is used to register the range specification of the filter that is used when filter

requires the net mask of IPv4 address. If you want to extract only the rangespecification from IPv4 address, you can apply a mask of filter specification to the address

registered to the register, if you set FILTRING 1 field MR4, MR3 of the L3/L4Filter Table

to 1. This register can be registered with the range specification mask in bit units.

bit31-0: FL_SUBNET

• Specifies the range specification of the filter.

31 0 bitFL_SUBNET0xFFFFFFFF Initial

valueR/W Attribute

101


3.4.5 Caution for Accessing the TablePackets cannot be referred correctly while CPU is accessing the table. So, when you access the

table, you must set the enable data link controller [DLCR6:BIT7] to "1," and keep the LAN

controller in the state in which send/receive operation is not available.

3.4.6 How to Set the Filter

3.4.6.1 How to Access the L3/L4 Filter Table1. Confirm that the status value of the status register (FL_STATUS) is set to "0" (no

write operation is running now).

2. To write data which is to register to the filter table into data register (FL_DATA),you have to process it in 12 times as all of it will not be written once. In the case ofthe item field of FL_CMD register is 0, write the data to be registered to the firstpart of SRC_IP [bit127-96] (the first 32 bit [bit:127-:96]of the transmission sourceIP address (Src IP address)) into the data register (FL_DATA).

FL_DATA: data register

3. Setting the command register

1) Set the location that you want to register into the table to the id of the command register

(entry number of the table) (in this case, "1").

2) Set "0" to item.

3) Set "0" (L3/L4 filter table is the target) to table.

4) Set "1" (write instruction) to cmd.

0010010011111110...

(first 32 bits of the IP address)

itemCorrespondence to L3/L4 filter

tableFunction

0 SRC0 Transmission source IP address

1 SRC1 Transmission source address (only IPv6)

2 SRC2

3 SRC3

4 DES0 Destination IP address

5 DES1 Destination IP address (only IPv6)

6 DES2

7 DES3

8 PORT LOWER Lower limit of PORT number

9 PORT UPPER Upper limit of PORT number

10 FILTERING Filtering

11 FILTER MODE Filter mode

102


FL_CMD: command register

4. As the hardware will start the write instruction, wait until the status value of thestatus register (FL_STATUS) is turned into "0" (no write operation is runningnow).

5. Repeat the steps 2-4 by changing the item number and fill the filter table.

31 16 12 8 5 4 0 bitreserved id item reserved table reserved cmd

1 0 0 1X X X X X X X X X X

103


3.4.6.2 Setting Method(1) In case L3/L4 Filter Table is to be initialized

1. Setting of the data register (FL_DATA)

Set "1" to bit 0.(set record invalid)

2. Setting of the command register (FL_CMD): Setting value 0x0000_0A01

3. Set just as same as step 2. for id bit 1-15.(all the entries will be invalid)

Bit Value FL_CMD Position

id "0000" bit15-12

item "1010" bit11-8

table "0" bit4

cmd "1" bit0

104


3.4.6.3 Setting of the Entire L3/L4 Filter TableSetting example for passing through only the data with the following conditions.

• With destination port number 12, all the destination IP address will pass through.

• With destination port number 11 - 20, the destination IP address 192.168.1.1 will pass

through.

• With destination port number 15, only the destination IP address 192.168.1.2 will pass

through.

As the table is referred from the top of the table (in numerical sequence of the IDs) and the

packet filtering is processed when the condition is met, detailed conditions should be set in the

first part of the table number.

1) Setting to drop the packets without entries that match to the protocol type table in filter

mode setting register.

2) Enable the destination port number 15 and destination IP address 192.168.1.2 (set table

number 0)

3) Enable the destination port number 11 - 14 and destination IP address 192.168.1.1 (set table

number 1)

4) Enable the destination port number 16 - 20 and destination IP address 192.168.1.1 (set table

number 2)

5) Enable the destination port number 12 (set table number 3)

6) Disable the other table setting. (table number 4 -15)

Setting for filter mode setting register1. Setting for the filter mode setting register (FL_CONTROL): Setting value

0x0000_0080

Enable the port number 15 and IP address 2 (set table number 0)

Setting for the destination IP address

1. Setting for the data register (FL_DATA) Set IP address to "192.268.1.2".

2. Setting for the command register (FL_CMD): Setting value 0x0000_0401

Bit Value fi_control position

L3/L4 table "1" bit 7


id "0000" bit15-12

item "0100" bit11-8

table "0" bit4

cmd "1" bit0

105


Setting for the lower limit port number field

3. Setting for the data register (FL_DATA) Set the destination port number "15" of TCP to pass through into bit 31-16.


Setting for the filtering field 1

5. Setting for the data register (FL_DATA): Setting value 0x0011_FF17

31 16 15 0 bitDES PORT LOWER SRC PORT LOWER


id "0000" bit15-12

item "1000" bit11-8

table "0" bit4

cmd "1" bit0

Bit Value FL_DATA Position

p "001" bit22-20

MR16 "0" bit19

MR15 "0" bit18

MR14 "0" bit17

MR13 "1" bit16

MR12 "1" bit15

MR11 "1" bit14

MR10 "1" bit13

MR9 "1" bit12

MR8 "1" bit11

MR7 "1" bit10

MR6 "1" bit9

MR5 "1" bit8

MR4 "0" bit7

MR3 "0" bit6

MR2 "0" bit5

MR1 "1" bit4

MR0 "1" bit2

t "1" bit1

V "1" bit0

106


6. Setting for the command register (FL_CMD): Setting value 0x0000_0A01


7. Setting for the data register (FL_DATA): Setting value 0x0000_0000

8. Setting for the command register (FL_CMD): Setting value 0x0000_0B01

Enable the port number 10 - 14 and IP address 1 (set table number 1)


1. Setting for the data register (FL_DATA) Set destination IP address to "192.268.1.1".



id "0000" bit15-12

item "1010" bit11-8

table "0" bit4

cmd "1" bit0


PD "0" bit8


id "0000" bit15-12

item "1011" bit11-8

table "0" bit4

cmd "1" bit0


id "0001" bit15-12

item "0100" bit11-8

table "0" bit4

cmd "1" bit0

107



3. Setting for the data register (FL_DATA) Set the lower limit of "11" for the destination port number of TCP to drop.


Setting for the upper limit port number field

5. Setting for the data register (FL_DATA) Set the upper limit of "14" for the destination port number of TCP to drop.




id "0001" bit15-12

item "1000" bit11-8

table "0" bit4

cmd "1" bit0

31 16 15 0 bitDES PORT UPPER SRC PORT UPPER


id "0001" bit15-12

item "1001" bit11-8

table "0" bit4

cmd "1" bit0

108




8. Setting the command register (FL_CMD)

Set 0x0000_1A01.




p "001" bit22-20

MR16 "1" bit19

MR15 "0" bit18

MR14 "0" bit17

MR13 "1" bit16

MR12 "1" bit15

MR11 "1" bit14

MR10 "1" bit13

MR9 "1" bit12

MR8 "1" bit11

MR7 "1" bit10

MR6 "1" bit9

MR5 "1" bit8

MR4 "0" bit7

MR3 "0" bit6

MR2 "0" bit5

MR1 "1" bit4

MR0 "1" bit2

t "1" bit1

V "1" bit0


id "0001" bit15-12

item "1010" bit11-8

table "0" bit4

cmd "1" bit0


PD "0" bit8

109



Enable the port number 16 - 20 and IP address 1 (set table number 3)


1. Setting for the data register (FL_DATA) Set destination IP address to "192.168.1.1".



3. Setting for the data register (FL_DATA) Set the lower limit of "16" for the destination port number of TCP to drop.


Setting for the upper limit port number field

5. Setting for the data register (FL_DATA) Set the upper limit of "20" for the destination port number of TCP to drop.


id "0001" bit15-12

item "1011" bit11-8

table "0" bit4

cmd "1" bit0


id "0010" bit15-12

item "0100" bit11-8

table "0" bit4

cmd "1" bit0



id "0010" bit15-12

item "1000" bit11-8

table "0" bit4

cmd "1" bit0

31 16 15 0 bitDES PORT UPPER SRC PORT UPPER

110







id "0010" bit15-12

item "1001" bit11-8

table "0" bit4

cmd "1" bit0


p "001" bit22-20

MR16 "1" bit19

MR15 "0" bit18

MR14 "0" bit17

MR13 "1" bit16

MR12 "1" bit15

MR11 "1" bit14

MR10 "1" bit13

MR9 "1" bit12

MR8 "1" bit11

MR7 "1" bit10

MR6 "1" bit9

MR5 "1" bit8

MR4 "0" bit7

MR3 "0" bit6

MR2 "0" bit5

MR1 "1" bit4

MR0 "1" bit2

t "1" bit1

V "1" bit0


id "0010" bit15-12

item "1010" bit11-8

table "0" bit4

cmd "1" bit0

111





Enable the destination port number 12 (set table number 3)


1. Setting for the data register (FL_DATA) Set "12" for the destination port number of TCP to pass through.



PD "0" bit8


id "0010" bit15-12

item "1011" bit11-8

table "0" bit4

cmd "1" bit0



id "0011" bit15-12

item "1000" bit11-8

table "0" bit4

cmd "1" bit0

112








p "001" bit22-20

MR16 "1" bit19

MR15 "0" bit18

MR14 "0" bit17

MR13 "1" bit16

MR12 "1" bit15

MR11 "1" bit14

MR10 "1" bit13

MR9 "1" bit12

MR8 "1" bit11

MR7 "1" bit10

MR6 "1" bit9

MR5 "1" bit8

MR4 "0" bit7

MR3 "0" bit6

MR2 "1" bit5

MR1 "1" bit4

MR0 "1" bit2

t "1" bit1

V "1" bit0


id "0011" bit15-12

item "1010" bit11-8

table "0" bit4

cmd "1" bit0


PD "0" bit8

113



Disable the other table setting. (table number 4 -15)




3. Repeat the step 1. and 2. with changing id bits (FL_CMD.bit15-12).


id "0011" bit15-12

item "1011" bit11-8

table "0" bit4

cmd "1" bit0


V "0" bit0


id "0100" bit15-12

item "1010" bit11-8

table "0" bit4

cmd "1" bit0

114


3.5 SMI Interface3.5.1 Overview

SMI interface has the following features.

SMI interface accesses the MII register of PHY chip via SMI I/F (serial communication) and

periodically monitors the link status. As the result of the polling is transferred to MAC block,

get the PHY status using the polling function. The host accesses the PHY register by setting the

values to the command register and the data register in this block.

<Notes>

PHY is a function to change digital '3f analog for transferring internal data to LAN.

115


3.5.2 Register List

White space: Unallocated portion

Word access only

Address 32 00x0110_0028 SMI_CMD SMI Command Register

0x0110_002C SMI_CMD_ST SMI Command Status Register

0x0110_0030 SMI_DATA SMI Data Register

0x0110_0034 SMI_POLLINTVL SMI Polling Register

0x0110_0038 SMI_PHY_ADD SMI PHY Address Register

0x0110_003C SMI_CONTROL SMI Control Register

0x0110_0040 SMI_STATUS SMI Status Register

0x0110_0044 SMI_INTENABLE SMI Link Register

0x0110_0048 SMI_MDCDIV SMIMDC Clock Selection Register

116


3.5.3 Register Detail SMI command register: SMI_CMD

SMI_CMD: Address 0110_0028h (Access: Word)

Command register is a register that issues the write or read command when accessing MII

Register of PHY device.

bit 31-16: Undefined



bit 15: Access type




bit 12-8: reg add

• Specify the address of MII register.

bit 7-5: Undefined



bit 4-0: phy add

• Specify the address of PHY chip.

31 16 15 14 13 12 8 7 5 4 0 bitreserved Access

typereserved reg add reserved phy add

X 0 X 0 X 0 Initial value

RX/WX R/W RX/WX R/W RX/WX R/W Attribute

Access type Write operation

0 read

1 write

117


SMI command status register: SMI_CMD_STSMI_CMD_ST: Address 0110_002Ch (Access: Word)

Control status register for accessing the PHY device.

bit 31-2: Undefined


bit 1: cmd_er

• The main reason for failure of accessing is that the PHY device is down.

• This will not be cleared until the following command succeeds.

bit 0: cmd_st

• This is cleared at the same time as the completion of the command execution.

31 2 1 0 bitreserved cmd_er cmd_st

X 0 0 Initial value

RX R R Attribute

cmd_er Read operation

0 When there is no error

1 When the accessing to MII register of PHY device failed

cmd_st Read operation

0 No access to PHY device

1 The hardware is accessing the PHY device now.

118


SMI data register: SMI_DATASMI_DATA: Address 0110_0030h (Access: Word)

Command register is a register that issues the write or read command when accessing MII

Register of PHY device.




bit 15-0: data

• Stores the data to be written to MII register of PHY device specified by smi_cmd.

31 16 15 0 bitreserved data

X 0 Initial value

RX/WX R/W Attribute

119


SMI polling register: SMI_POLLINTVLSMI_POLLINTVL: Address 0110_0034h (Access: Word)

This register sets the cycle for accessing the PHY device.




bit 15-0: Pollintvl

• Register the cycle for accessing (polling) the PHY device periodically. 320µs

(128cyclex 5 @ 2MHz) is one unit.

• The Value 2MHz is related to the division clock value supplied by MDC, and set by

MDC register. Refer to this section for details. (MDC, an abbreviation for Management

Data Clock, is a clock between PHY and link layer.)

31 16 15 0 bitreserved Pollintvl

X 0 Initial value

RX/WX R/W Attribute

Pollintvl Write operation

0 Means that no polling will be executed.

1 - Indicates the cycle for the polling.

120


SMI PHY address register: SMI_PHY_ADDSMI_PHY_ADD: Address 0110_0038h (Access: Word)

Register to set the address of the PHY device that is used for polling.

bit 31-5: Undefined



bit 4-0: phy_add

• Specifies the address for the PHY device.

31 5 4 0 bitreserved phy_add

X 0 Initial value

RX/WX R/W Attribute

121


SMI control register: SMI_CONTROLSMI_CONTROL: Address 0110_003Ch (Access: Word)

This register determines the operation mode of the PHY device.

bit 31-3: Undefined



bit 2: LS_mode

bit 1: LD_mode

• Even if "1" is set, it is not reflected to MAC block, unless you conduct polling and get

the status of the PHY device.

bit 0: LA_mode

• If Bit0 is set to 1, the settings for LS_mode [bit2] and LD_mode [bit1] are invalid.

31 3 2 1 0 bitreserved LS_

modeLD_

modeLA_

modeX 1 1 1 Initial

valueRX/WX R/W R/W R/W Attribute

LS_mode Write operation

0 Communicates at a speed of 10BASE

1 Communicates at a speed of 100BASE

LD_mode Write operation

0 half duplex mode

1 full duplex mode

LA_mode Write operation

0 Disables the autolink

1 Enables the autolink

122


SMI status register: SMI_STATUSSMI_STATUS: Address 0110_0040h (Access: Word)

This is a status register related to the link status.

bit 31-4: Undefined


bit 4: Link Status Change

• If "1" is set to Link Status [Bit0] of SMI_INTENABLE register, interrupt is asserted

when Link Status Change turns into "1.(Read clear)

• This is valid when auto-negotiation is enabled.

bit 3: Link Status

bit 2: Link Speed

bit 1: Link Duplex

bit 0: Link Auto

31 5 4 3 2 1 0 bitreserved Link

Status Change

Link Status

Link Speed

Link Duplex

Link Auto

X 1 0 1 1 0 Initial value

RX/WX R/WX R/WX R/WX R/WX R/WX Attribute

Link Status Read operation

0 There is no change in link up or link down/speed/duplex mode/auto-negotiation

1 There is change in link up or link down/speed/duplex mode/auto-negotiation

Link Status Read operation

0 Indicates Link Down

1 Indicates Link Up

Link Speed Read operation

0 Communicating at a speed of 10BASE

1 Communicating at a speed of 100BASE

Link Duplex Read operation

0 Communicating in half duplex mode.

1 Communicating in full duplex mode.

Link Auto Read operation

0 Autolink is disabled

1 Autolink is enabled

123


Interrupt enable register: SMI_INTENABLESMI_INTENABLE: Address 0110_0044h (Access: Word)

bit 31-1: Undefined



bit 0: Link Status Change

• If bit[0] is set to "1", interrupt is asserted when the bit[4] of SMI_STATUS register turns

to "1".

31 0 0 bitreserved Link Status

ChangeX 0 Initial

valueRX/WX R/W Attribute

Link Status Change Write operation

0 Disables the link status change interrupt.

1 Enables the link status change interrupt.

124


SMI MDC clock selection register: SMI_MDCDIVSMI_MDCDIV: Address 0110_0048h (Access: Word)

This register is used to generate divided clock for MDC from a system clock.

bit 31-5: Undefined



bit 4-0: mdcdiv

• Determines the value to generate division clock. (This value is used for the calculation

when generating.)

[formula]

Divide value (Hz) = System clock (Hz) ÷ (smi_mdcdiv register value + 1) ÷ 2

31 5 4 0 bitreserved mdcdiv

X 01011 Initial value

RX/WX R/W Attribute

125


3.5.4 OperationAccessing the PHY device (register) by the SMI register.

Read procedure for MII register of PHY device

1) Check the cmd_st bit (smi_cmd_st. cmd_st) is "0" (no accessing to PHY device).

2) Set "0" (to read) to Access type bit (smi_cmd. Access type).

Set the address of PHY chip to phy add bit (smi_cmd. phy add).

Set all "0" (no polling) to the polling cycle bit (smi_pollintvl.Pollintvl).

(If polling is implemented from SMI control block, the command from the host is ignored.

If you set 16’h0000 to the smi_pollintvl register, you can stop the polling from the SMI

control block.)


3) According to the setting written to the Command register, communication with the PHY

device will be started. PHY device reads the data from PHY register with the specified

address in accordance with the command.

(The cmd_st bit (smi_cmd_st. cmd_st) will be "1" (the hardware is accessing the PHY

device now).)

4) Check the cmd_st bit (smi_cmd_st. cmd_st) is "0" (no accessing to PHY device). (reading

completed)

5) Check the cmd_er bit (smi_cmd_st.cmd_er) is "0" (no error).

(If the bit 1 of smi_cmd_st register is "1," this means the read operation has failed. In this

case, no correct value has obtained into the smi_data register. )

6) Read data bit (smi_data.data). (Read the value from smi_data register. )

Write procedure for MII register of PHY device

1) Store the data that you want to write into the PHY device in the data bit (smi_data.data).

2) Check the cmd_st bit (smi_cmd_st. cmd_st) is "0" (no accessing to PHY device).

Set "1" (to write) to Access type bit (smi_cmd. Access type).

Set all "0" (no polling) to the polling cycle bit (smi_pollintvl.Pollintbl).

(For smi_pollintvl register, configure the same setting for the read procedure.)


3) According to the setting written to the smi_data and smi_cmd registers, communication

with the PHY device will be started. PHY device writes the data into the PHY register with

the specified address in accordance with this command. (The cmd_st bit

(smi_cmd_st.cmd_st) will be "1" (the hardware is accessing the PHY device now).)

126


4) Check the cmd_st bit (smi_cmd_st. cmd_st) is "0" (no accessing to PHY device). (writing

completed)

Polling

First, the SMI I/F block initiates the PHY chip before polling. This initiation will be written to

MII register 0 (control register) and 4 (autonegotiation advertise register) of the PHY device

according to the setting of the control register. To enable the auto-negotiation, restart the auto-

negotiation. After that, wait for the auto-negotiation to complete, then move to polling

operation.

The following is the description of this operation.

1) If the content of the control register has changed (auto-negotiation enable, speed, duplex

mode), configure the setting of MII register 0 and 4.

2) If this is not the case, read the MII register 1 (status register).

3) If link is down, set the corresponding interrupt bit.

4) If auto-negotiation is not supported, set the corresponding interrupt bit, and move to the

next interface.


5) If auto-negotiation has not completed, don't do anything.

6) If auto-negotiation has been completed, read MII register 5 and determine the operation

mode (speed, duplex).

7) The result will be reflected to the status register.

127


128

Chapter4 EXTERNAL IF/GPIO

Overview, Features

129


4.1 Overview

External IFIt functions as a slave bus and can communicate in 16 bits or 8 bits as a port for direct data

communication with an external MCU.

It consists of a communication register and a high-capacity send-and-receive FIFO buffer that

realizes massive data sending/receiving. It implements efficient communication as well as

alleviating the CPU load.

GPIOA 4 bit dedicated general purpose I/O port (Port A) and a general purpose I/O port with a maxi-

mum of 22 bits (Port B) that shares the External IF pins are installed and may be utilized for a

variety of purposes.

For Port A, when the input port is initialized an interrupt generation function for signal changes

is installed.

130


4.2 Features 8/16 bit data interface

As it is shared with the GPIO (General Purpose IO: Port B), it may be used as follows.

• External IF only (16 bits)

• External IF (8 bits), GPIO (8 bits)

• GPIO (22 bits)

768 bite single port RAM and two-side configured RX_FIFO

The RX_FIFO is configured on two sides; one side can read while the other side is writing.To

avoid competition between reading and writing actions during the writing process, data size

during the operation is stored in read-disabled data size.

1536 byte dual port RAM and single-side configured TX_FIFO

TX_FIFO is configured as a dual port RAM (single side) and can simultaneously write inter-

nal data from this chip and read data from an external source.

Send and receive register

Besides the FIFO which implements large volume data sending/receiving, the send and receive

registers intended for communication control each possess 16 bits. This makes communication

control possible during data sending/receiving, too.

DMA send/receive function

It is possible to perform DMA transfer for RX_FIFO and TX_FIFO using the FR core DMA

controller.

In addition, only during DMA transfer to RX_FIFO, Fly-by (IO to Memory) transfer by the

DMA controller is possible and high-speed data sending/receiving is achieved.

Dedicated general purpose IO port (Port A)

A dedicated general purpose (4-bit) IO port is installed in addition to the general purpose IO

port (Port B) shared with the external IF.

It is possible to select the input and output for each bit via the register settings. In addition,

when selecting input, there is a function to generate an interrupt signal in response to changes

in input signals.

131


4.3 Configuration Diagram Overview block diagram

PA[3:0]

EXD[15:0]/PB[15:0]

EXCSX/PB[21]EXA/PB[20]

EXRDX/PB[19]EXWRX/PB[18]

DREQRX/PB[17]DREQTX/PB[16]

FR COREOther CPU

Rx_REG

Rx FIFO

External IF

Control Block

Reception interrupt

REG Data In RxFIFO Full

BU

S IF

Tx_REG

Tx FIFO

Serial communication

External IF communication

GPIO(Port B)

Data S

elector

GPIO(Port A)

Input signal change interrupt

MB91402

132


4.4 Signals

Pin name NameInput and

outputFunction

EXD [15:0]/PB [15:0]

Input/Output data bus/General purpose IO port

Input and output

Inputs/outputs data. / General purpose input/output port.

EXCSX/PB [21]

Chip select signal/General purpose IO port

Input/Input and

output

Inputs chip select signal. It is low active. / General purpose input/output port.

EXA/PB [20]

Address signal/General purpose IO port

Input/Input and

output

Inputs address signal. Selects register when it is '0'. Selects data when it is '1'. / General purpose input/output port.

EXRDX/PB [19]

Read strobe signal/General purpose IO port

Input/Input and

output

Inputs read strobe signal. It is low active. / General purpose input/output port.

EXWRX/PB [18]

Write byte strobe signal/General purpose IO port

Input/Input and

output

Inputs write byte strobe signal. It is low active. / General purpose input/output port.

DREQRX/PB [17]

Receive data request signal

/General purpose IO port

Output/Input and

output

Ös receive data request signal. It is low active. It is a data request from external MCU to MB91403. This signal shows to the outside that it is possible to receive data. / General purpose input/output port.

DREQTX/PB [16]

Send data request signal/General purpose IO port

Output/Input and

output

Outputs send data request signal. It is low active. It is a data request from MB91403 to external MCU. This signal shows to the outside that there is data to send. / General purpose input/output port.

PA [3:0] General purpose IO port Input and output

General purpose input/output port.

133


4.5 Address List

Block Address Register Name Abbreviation Size R/W Initial Value

External IF

0x0114 _0000 EX.IF RX Data Register EXIFRXDR 32 bit R 32'hxxxxxxxx

_0004 EX.IF TX Data Register EXIFTXDR 32 bit W 32'h0

_0008 EX.IF RX Register EXIFRXR 16 bit R 16'h0

_000C EX.IF TX Register EXIFTXR 16 bit W 16'h0

_0010 EX.IF Control Register EXIFCR 11 bit W 9'b0

_0014 EX.IF Status Register EXIFSR 10 bit R 10'b0

_0018EX.IF RX FIFO Status Register

EXIFRXSR 32 bit R 32'h0

_001CEX.IF TX FIFO Status Register

EXIFTXSR 32 bit R 32'h06000000

GPIO (PORT A)

_0020 PA Control Register PACR 9 bit R/W 9'b0

_0024 PA Data Register PADR 8 bit R/W* Depends on the

access point

GPIO (PORT B)

_0030 PB Control Register PBCR 9 bit R/W 22'b0

_0034 PB Data Register PBDR 8 bit R/W* Depends on the

access point

134


4.6 Detailed Explanation of the RegisterExplanation of the code expressing access limits to each bit of the register

[Code]

R : Read permitted

R0 : Always 0

R1 : Always 1

RX : Indeterminate

W : Write permitted

W0 : Always write 0

W1 : Always write 1

WX : Write invalid

[Combination] "/" and ","


R,W: The significance of the bit changes according to whether it is read or write

[Support for read modify write] using "(" ")"

R(RM1)/W: Possible to read written value (The reading is always 1 during RMW)

R(RM1),W: Read is possible (always 1 during RMW), write is possible

135


EXIF RX Data Register: EXIFRXDREXIFRXDR: Address 0x0114_0000h

It is the data register that is connected to RX_FIFO.

bit 31-0: RD DATA Register

• It is the data register that is connected to RX_FIFO.

• At each time of access, the address is incremented internally and it outputs the

RX_FIFO data.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

0000H RD31 RD30 RD29 RD28 RD27 RD26 RD25 RD24 RD23 RD22 RD21 RD20 RD19 RD18 RD17 RD16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value

R R R R R R R R R R R R R R R R Attribute

0002H RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value


136


EXIF TX Data Register: EXIFTXDREXIFTXDR: Address 0x0114_0004h

It is the data register that is connected to TX_FIFO.

bit 31-0: TX DATA Register

• It is the data register that is connected to TX_FIFO.

• At each time of access, the address is incremented internally, and it writes the TX_FIFO

data.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

0004H TD31 TD30 TD29 TD28 TD27 TD26 TD25 TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 TD16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value

W W W W W W W W W W W W W W W W Attribute

0006H TD15 TD14 TD13 TD12 TD11 TD10 TD9 TD8 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value

W W W W W W W W W W W W W W W W Attribute

137


EXIF RX Register: EXIFRXREXIFRXDR: Address 0x0114_0008h

It is the register that shows values input into the RX_REG from the outside.

bit 31-16: RX_REG

• It shows values entered into the RX_REG from the outside.

• When the EXIFCR register' bit [11:10]:SEL is "00", RR15 - RR0 become valid.


• When the EXIFCR register' bit [11:10]:SEL is "1x", it becomes invalid.

bit 15-0: Undefined (reserved)


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

0008H RR15 RR14 RR13 RR12 RR11 RR10 RR9 RR8 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value


000AH Undefined (reserved)

X Initial value

RX Attribute

138


EXIF TX Register: EXIFTXREXIFTXR: Address 0x0114_000Ch

It is the input register to TX_REG.

bit 31-16: RX_REG

• It is the input register to TX_REG.



• When the EXIFCR register' bit [11:10]:SEL is "1x", it becomes invalid.



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

000CH TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value

W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R Attribute

000EH Undefined (reserved)

X Initial value

WX Attribute

139


EXIF Control Register: EXIFCREXIFCR: Address 0x0114_0010h

It is the register that directs TX_FIFO and RX_FIFO operations.



Bit 10-9: IF selection control

bit 8: TX_FIFO DMA transfer control

• The DREQ signal is invalidated after completion of the DMA write before it becomes

full.

bit 7: RX_FIFO DMA transfer control

• RX_FIFO is configured on two sides and the DREQ signal is output whenever one of

them is full. The DREQ signal reads RX_FIFO and is invalidated after completion of the

penultimate DMA read before it becomes empty.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

0010H Undefined (reserved)

X Initial value

WX Attribute

0012H Undefined (reserved) SELTX_

DMA_ENA\

RX_DMA_ENA

TX_DMA_ENA

INT_TX_EMP

INT_RX_FULL

TX_CLR

RX_CLR

TX_STAT

RX_STAT

X 0 0 0 0 0 0 0 0 0 0 Initial value

WX W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R Attribute

SEL Mode

00 External IF: 16 bit bus mode becomes valid.

01 External IF: 8 bit bus mode + Port B [7:0] become valid.

1x Port B [21:0] becomes valid.

TX_DMA_ENA Mode

0When the TX_FIFO domain is empty, the DREQ signal (the TX_FIFO data DMA transfer request signal) is not validated.

1When the TX_FIFO domain is empty, the DREQ signal (the TX_FIFO data DMA transfer request signal) is validated.

RX_DMA_ENA Mode

0The DREQ signal is not output when the RX_FIFO domain (Side A or Side B) is full.

1The DREQ signal is output when the RX_FIFO domain (Side A or Side B) is full.

140


bit 6: TX_FIFO empty interrupt control

• The DREQ signal is invalidated after completion of the DMA write before it becomes

full.

bit 5: RX_FIFO full interrupt control

• RX_FIFO is configured on two sides and the interrupt signal is generated whenever one

of them is full.

bit 4: RX_REG data in interrupt control

bit 3: TX_REG/FIFO clear control

• If "1" has been set, after they are cleared it is automatically reset to "0".

bit 2: RX_REG/FIFO clear control

• If "1" has been set, after they are cleared it is automatically reset to "0".

INT_TX_ENA Mode

0 The interrupt is not generated when the TX_FIFO domain is empty.

1 The interrupt is generated when the TX_FIFO domain is empty.

INT_RX_FULL Mode

0The interrupt is not generated when the RX_FIFO domain (Side A or Side B) is full.

1The interrupt is generated when the RX_FIFO domain (Side A or Side B) is full.

INT_RX_REG_I Mode

0The interrupt is not generated when data has been input into the RX_REG.

1The interrupt is generated when data has been input into the R RX_REG.

TX_CLR Mode

0 No program.

1 Clears the TX_REG and the TX_FIFO address.

RX_CLR Mode

0 No program.

1 Clears the RX_REG and the RX_FIFO address.

141


bit 1: External data send control

bit 0: External data receive control

TX_STAT Mode

0 Data is not sent from the external interface.

1 Data is sent from the external interface.

RX_STAT Mode

0 Data is not received from the external interface.

1 Data is received from the external interface.

142


EXIF Status Register: EXIFSREXIFSR: Address 0x0114_0014h

This register shows the status conditions of TX_FIFO and RX_FIFO.



bit 7-6: TX_FIFO status

bit 5-4: RX_FIFO status SIDE-B (the status condition of the B side of the two-sidedRX_FIFO domain)

bit 3-2: RX_FIFO status SIDE-A (the status condition of the A side of the two-sidedRX_FIFO domain)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit


X Initial value

RX Attribute

0016H Undefined (reserved) TX_FIFO RX_FIFO_B RX_FIFO_ATX_

REG_OUT

RX_REG_

IN

X 0 0 0 0 0 0 0 0 Initial value

RX R R R R R R R R Attribute

TX_FIFO Mode

00There is no data in the TX_FIFO domain. (Including when it has been cleared)

01 There is data in the TX_FIFO domain.

10 The TX_FIFO domain has become full of data.

11 Reserved

RX_FIFO_B Mode

00There is no data in the RX_FIFO domain (Side B). (Including when it has been cleared)

01 There is data in the RX_FIFO domain (Side B).

10 The RX_FIFO domain (Side B) has become full of data.

11 Reserved

RX_FIFO_A Mode

00There is no data in the RX_FIFO domain (Side A). (Including when it has been cleared)

01 There is data in the RX_FIFO domain (Side A).

10 The RX_FIFO domain (Side A) has become full of data.

11 Reserved

143


bit 1: TX_REG output status

• When read processing is carried out it is reset to '0'.

bit 0: RX_REG input status

• When read processing is carried out it is reset to '0'.

TX_REG_OUT Mode

0There is no data output from the TX_REG (including when it has been cleared).

1 There was data output from the TX_REG.

RX_REG_OUT Mode

0There is no data input to the RX_REG from the external host. (Including when it has been cleared)

1 There was data input to the RX_REG from the external host.

144


EXIF RX FIFO Status Register: EXIFRXSREXIFRXSR: Address 0x0114_0018h

This register shows the readable data size of RX_FIFO.

bit 31-16: AP_RXSIZE: RX_FIFO read-enabled data size (the units are in bytes)

• This shows the readable data size from RX_FIFO.

• If data reading that exceeds the read-enabled data size is performed, the correct data will

not be used.

bit 15-0: DISAP_RXSIZE: RX_FIFO read-disabled data size (the units are in bytes)

• This shows the unreadable data size from RX_FIFO.

<Note>

RX_FIFO configures two sides of a single port RAM; while one side is reading, the otherside assumes writing (as a ping-pong FIFO).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

0018H AP_RXSIZE

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value


001AH DISAP_RXSIZE

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value


145


EXIF TX FIFO Status Register: EXIFTXSREXIFTXSR: Address 0x0114_001Ch

This register shows the writable data size of TX_FIFO.

bit 31-16: AP_TXSIZE: TX_FIFO write-enabled data size (the units are in bytes)

• This shows the writable data size writable to TX_FIFO.

<Note>

The TX_FIFO, with its structure of a single side using a dual port RAM, cansimultaneously write data from within this chip and read data from the external interface.



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

001CH AP_TXSIZE

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value


001EH Undefined (reserved)

X Initial value

RX Attribute

146


Port A Control Register: PACRPACR: Address 0x0114_0020h

This is the Port A control register.

Bit 31-9: Undefined (reserved)


Bit 8: Interrupt enabling control

• This is the control bit to enable generation of interrupt signals during input initialization

and signal changes.


Bit 3-0: Port A direction control

• This controls the direction of each Port A bit.

Each bit is assigned to the pins below.

Bit [3]: PA [3]

Bit [2]: PA [2]

Bit [1]: PA [1]

Bit [0]: PA [0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit


X Initial value

RX Attribute

0022H Undefined (reserved) INTEN Undefined (reserved) PADIR

X 0 0 0 Initial value

RX R/W R/W R/W Attribute

INTEN Mode

0 The interrupt signal is not generated during signal changes.

1 An interrupt signal is generated during signal changes.

PADIR[x] Mode

0 Input

1 Output

147


Port A Data Register: PADRPADR: Address 0x0114_0024h

This is the Port A data register.



Bit 7-0: Port A data

• Data of each Port A bit is stored.

* Each bit is assigned to the pins below.

Bit [3]: PA [3]

Bit [2]: PA [2]

Bit [1]: PA [1]

Bit [0]: PA [0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit


X Initial value

RX Attribute

0026H Undefined (reserved) PADIR

X - Initial value

RX R/W Attribute

148


Port B Control Register: PBCRPBCR: Address 0x0114_0030h

This is the Port B control register.



Bit 21-0: Port B direction control

• This controls the direction of each Port B bit.

Each bit is assigned to the pins below.

Bit [21:0] PB[21:0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

0030H Undefined (reserved) PBDIR

X 0 Initial value

RX R/W Attribute

0032H PBDIR

0 Initial value

R/W Attribute

PBDIR[x] Mode

0 Input

1 Output

149


Port B Data Register: PBDRPBDR: Address 0x0114_0034h

This is the Port B data register.



Bit 21-0: Port B data

• The data of each Port B bit is stored.

* Each bit is assigned to the pins below.

Bit [21:0] PB[21:0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit

0034H Undefined (reserved) PBDATA

X - Initial value

RX R/W Attribute

0036H PBDATA

- Initial value

R/W Attribute

150


4.7 External IF Operation

Receiving operation• When the data receive request signal (DREQRX) is valid and the writing of data from

outside is performed, then it is written into RX_REG and RX_FIFO according to the

address signal (EXA).

• When writing into RX_REG occurs, '1' is written into EXIFSR: BIT 0.

• Data is received alternately using the RX_FIFO on the two sides. When either RX_FIFO is

full, '10' is written into RX-FIFO status SIDE-B [EXIFSR: BIT 5-4] and RX-FIFO status

SIDE-A [EXIFSR: BIT 3-2].

• The receive request signal (DREQRX) for RX_FIFO data becomes invalid only when the

RX_FIFO is full on both sides.

Sending operation• When the data sending request signal (DREQTX) is valid and a data read operation is

performed from outside, data is read out into TX_REG and TX_FIFO according to the

address signal (EXA) and the data is output to outside.

• When a read is generated for TX_REG from outside, the TX_REG output status bit

[EXIFSR:BIT1] becomes '1' (there has been data output from the TX_REG register). Once

the TX_REG has been read, there is no data output unless the TX_REG has been written in

again.

• When the TX_FIFO has become empty, '00' is written into the status register [EXIFSR:BIT

7-6]. The interrupt control generates an interrupt when the interrupt bit for TX_FIFO empty

[EXIFSR:BIT6] is '1'.

• When all the data in the TX_REG and TX_FIFO has been read, the send request signal for

TX_FIFO data (DREQTX) becomes invalid.

151


4.7.1 Setting procedureThe essential items (summary) for using the External IF are shown below.

1. To request receiving of data?

→

1) Set the data receive initiation bit [EXIFCR:BIT0] to '1'.

This validates the receive request signal for RX_FIFO data (DREQRX) and requests data

writing from outside. (Except when RX_FIFO is full on both sides)

<Note>

When the receive request signal (DREQRX) is invalid, writing actions to the RX_REG andRX_FIFO performed from outside do not cause actual data writing into the RX_REG andRX_FIFO.

2. To read the received data?

→

1) Read the EXIF data register (EXIFRXDR).

However, when the RX_FIFO status SIDE-B [EXIFSR:BIT5-4] and RX_FIFO status

SIDE-A [EXIFSR:BIT3-2] are '01', which means that the volume of receive data does

not make the RX_FIFO full, take the following course of actions to read the received

data:

(1) Set the data receive initiation bit [EXIFCR:BIT0] to '0' and stop receiving data from

outside.

(2) Read the RX_FIFO read-enabled data size bit [EXIFRXSR:BIT31-16].

Table 4.7-1 Setting for sending

Operation Referent Register

To request receiving of data? 1. EXIFCR [BIT 0]

To read the received data? 2. EXIFXDR

To clear the receive data? 3. EXIFCR [BIT2,0]

To use the DMA receive function? 4. EXIFCR [BIT 8]

To generate an interrupt during receiving? 5. EXIFCR [BIT 6,4]

Table 4.7-2 Setting for sending

Operation Referent Register

To request data sending? 6. EXIFCR [BIT 1]

To terminate the data sending request? 7. EXIFCR[BIT3,1]

To clear send data? 8. EXIFCR[BIT3,1]

To generate an interrupt during sending? 9. EXIFCR[BIT5]

152


3. To clear the receive data?

→

1) Set the data receive initiation bit [EXIFCR:BIT0] to '0' and stop receiving data from

outside.

2) Set the RX_REG/FIFO clear bit [EXIFCR:BIT2] to '1' and clear the RX_REG/RX_FIFO

addresses.

<Note>

The clear bit is automatically cleared to '0'.

Once the data receive initiation bit [EXIFCR:BIT0] has been set to '0', when setting thedata receive initiation bit [EXIFCR:BIT0] to '1' again it is necessary to first set the clear bit[EXIFCR:BIT2] to '1' and clear the receive data. Since the data in the receive FIFO iscleared at this time, it is necessary to read in all the data in the receive FIFO beforesetting the clear bit to '1'.

4. To use the DMA receive function?

→

1) Set the RX_FIFO DMA transfer control bit [EXIFCR:BIT8] to '1' and initiate receiving

data; if the RX_FIFO on either side is full, the DMA transfer request signal (DREQ

signal) is validated for the DMA controller in the FR core.

5. To generate an interrupt during receiving?

→

To generate an interrupt when either SIDE-A or SIDE-B of the RX_FIFO has become full

and data has become readable?

1) Set the RX_FIFO full interrupt signal [EXIFCR:BIT5] to '1'.

To generate an interrupt when data has been input into the RX_REG?

1) Set the RX_REG data in interrupt control bit [EXIFCR:BIT4] to '1'.

6. To request data sending?

→

1) Set the data send initiation bit [EXIFCR:BIT1] to '1'.

The send request signal (DREQTX) for TX_FIFO data is validated by this. Then, when

writing into the TX_FIFO occurs within MB91403, a data read request is made to the

outside.

7. To terminate the data send request?

→

1) Set the TX_REG/FIFO clear bit [EXIFCR:BIT3] to '1' and clear the TX_REG register

and TX_FIFO address.

2) Set the data send initiation bit [EXIFCR:BIT1] to '0' and invalidate the DREQTX signal.

153


8. To clear the send data?

→

1) Set the TX_REG/FIFO clear bit [EXIFCR:BIT3] to '1' and clear the TX_REG register

and TX_FIFO address.

2) Set the data send initiation bit [EXIFCR:BIT1] to '0' and stop data sending to the outside.

<Note>

The clear bit is automatically cleared to '0'.

9. To generate an interrupt during sending?

→

To generate an interrupt when the TX_FIFO domain is empty?

1) Set the TX_FIFO empty interrupt control bit [EXIFCR:BIT6] to '1' and an interrupt is

generated when the TX_FIFO becomes empty.

<Note>

The specification that the interrupt signal is disabled by reading the status register(EXIFSR) means that the interrupt signal becomes invalid when reading of the statusregister has been completed.

154


4.7.2 Signal waveform diagram

data2

Ext

erna

l sid

e EXA

EXCSX

EXWRX

EXRDX

EXD[15:0]

MB

9140

2 In

tern

al s

ide A[3:0]

CSX[4]

WRX[3:0] 4'hf

RDX

D[31:0](Read)

D[31:0](Write)

data1

MB

9140

2 In

tern

al s

ide

Sending operation

Ext

erna

l sid

e EXA

EXCSX

EXWRX

EXRDX

EXD[15:0]

data1

4'h0

CSX[4]

WRX[3:0]

Receiving operation

D[31:0](Write)

RDX

D[31:0](Read)

A[3:0]

4'hf

4'h0

data2

4'h0

2cycle

> 3cycle

> 5cycle

> 4cycle

> 3cycle

155


4.8 GPIO (Port A) Operation GPIO(Port A) is a general purpose IO port loaded with a function to generate an interrupt sig-

nal in response to a change in the input signal.

4.8.1 Interrupt specifications Set the input pin specifications in Register PADIR (Port A Control Register [7:0]); when the

register INTEN bit is set to "1", an interrupt signal is generated in response to a change in the

input signal.

4.8.2 Interrupt waveform The input signal from outside is double-latched inside and the value is stored in the register.

A change in the signal is detected by performing XOR on the 3rd latch step and 2nd latch step.

An interrupt signal is generated using a value obtained by performing OR operation on these

bits.

The interrupt signal is cleared by reading PADR register.

156


4.9 GPIO (Port B) Operation GPIO (Port B) is a general purpose IO port.

GPIO (Port B) shares the External IF pins.It can be set using the SEL bit of the EXIFCR

register.

EXIFCR register

Bit 10-9: IF selection control

SEL Mode

00 External IF: 16 bit bus mode becomes valid.

01 External IF: 8 bit bus mode + Port B [7:0] become valid.

1x Port B [21:0] becomes valid.

157


4.9.1 Pin selection specificationsPort B shares the External IF pins.

Selector specifications for the Port B pins and the External IF pins are shown below.

SEL[1] | SEL[0]

EXDOE_L[7:0] PBOE[7:0] : Port B output control

EX_DOE : External IF output control

EXD[7:0] PBDO[7:0] : Port B data output/PB[7:0] EXDO[7:0]

EX_DO[7:0] : External IF data output

PBDI[7:0] : Port B data input

EX_DI[7:0] : External IF data input

SEL[1]



EXD[15:8] PBDO[15:8] : Port B data output/PB[15:8] EXDO[15:8]

EX_DO[15:8] : External IF data output


EX_DI[15:8] : External IF data input

1

0

1

0

1

0

1

0


SEL[1]

PBDO[21:18] : Port B data output

/PB[21:18] PBDI[21:18] : Port B data input

EXCSX,EXA,EXRDX,EXWRX : External IF control input

EXCSX,EXA,EXRDX,EXWRX

SEL[1]



PBDO[17:16] : Port B data outputEXDO[17:16]

DREQTX,DREQRX: External IF control output


DREQTX,DREQRX/PB[17:16]

1

0

1

0

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I2C IF

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5.1 OverviewThis document is the external specification for the I2C IF of the MB91403.

This interface is a serial interface that supports the Inter-IC BUS. It works as a master/slave

device on the I2C bus.

5.2 FeaturesThe features of this interface are as follows:

• Master send and receive function

• Slave send and receive function

• Arbitration function

• Clock synchronization function

• Slave address detection function

• General call address detection function

• Transfer direction detection function

• Repeated Start condition generation and detection function

• Bus error detection function

• Supports standard mode (Max.100Kbps) and high-speed mode (Max.400Kbps).

Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to

use,these components in an I2C system provided that the system conforms to the I2C Standard

Specification as defined by Philips.

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5.3 Block diagram

SDA

SCL

Start condition/stop condition

detection circuit

Noise filter

Start condition/stop condition

generation circuit

Shift Clockgeneration circuit

Arbitration lostdetection circuit

ADR BSR

BCR

CCRDAR

Comparator

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5.4 Function Description Start and stop condition detection circuit

This circuit detects the start and stop conditions by sensing SDA and SCL status changes.

Start and stop condition generation circuit

This circuit generates the start and stop conditions by changing the SDA and SCL statuses.

Arbitration lost detection circuit

When data is being sent, this circuit compares the data output to the SDA line and the data

input from the SDA line to ensure that the output and the input match. If they do not match, the

circuit generates Arbitration Lost (i.e., sets the Arbitration Lost bit).

Shift clock generation circuit

This circuit generates timing clock pulses for serial data transfer and controls SCL clock out-

put based on the setting of the clock control register.

Comparator

The comparator checks the received address to see whether it matches the self address con-

tained in the address register or the global address.

ADR

This is a 7-bit register that specifies the slave address.

DAR

This is an 8-bit register used for serial data transfer.

BSR

This is an 8-bit register used to indicate the I2C bus status and other information. Its functions

are as follows:

• Repeated Start condition detection

• Arbitration Lost detection

• Acknowledgement bit storage

• Data transfer direction

• Addressing detection

• General call address detection

• First byte detection

BCR

This is an 8-bit register used to control the I2C bus and control interrupts. Its functions are as

follows:

• Interrupt request/permission

• Start condition generation

• Master/slave selection

• Acknowledgement generation permission

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CCR

This is a 7-bit register that sets a frequency of the serial data transfer clock.

• Operation permission

• Serial clock frequency setting

• Standard only enabled (fast mode unselectable)

Noise filter

This noise filter consists of a three-stage shift register circuit. The SCL/SDA input signal is

sampled in succession through the three stages. If all of the three values from the three stages

are "1", the filter output will be "1". If all of the three values are "0", the filter output will be

"0". Otherwise, the filter retains the status that stood one clock earlier.

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5.5 Register Map Configuration

5.5.1 Register map

Note: I2C IF registers are only accessible in byte units.

Block Address Register name Abbreviation Size R/W Initial value

I2C IF

0x010F _0000 Bus Status Register BSR 8 bits R 8'b0

_0001 Bus Control Register BCR 8 bits R/W 8'b0

_0002 Clock Control Register CCR 8 bits R/W 8'b10000000

_0003 ADress Register ADR 8 bits R/W 8'b1-------

_0004 DAta Register DAR 8 bits R/W 8'b--------

_0005 enhanced CS Register CSR 8 bits R/W 8'b0

_0006 bus clock Freq. Select Register FSR 8 bits R/W 8'b1

_0007 Bus Control2 Register BC2R 8 bits R/W 8'b00--0000

_0008

Access forbidden-

_FFFF

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5.5.2 Register description

5.5.2.1 Bus Status Register (BSR)This register indicates the I2C bus status.

Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

0000H BB RSC AL LRB TRX AAS GCA FBT

R/W R R R R R R R R

Initial value 0 0 0 0 0 0 0 0

Bit Bit nameInitial value

R/W Function

7 BB 0 R

Bus Busy

This bit indicates the I2C bus status.0: The stop condition has been detected.1: The start condition has been detected (the bus is busy).

6 RSC 0 R

Repeated Start ConditionThis bit indicates that the Repeated Start condition has been detected.0: The Repeated Start condition has not been detected.1: The Start condition has been detected again during bus use.* This bit will be cleared in one of the following conditions: "0" is written

to the INT bit; addressing is skipped in slave mode; the Start condition is detected when the bus is inactive; and the Stop condition is detected.

5 AL 0 R

Arbitration LostThis bit indicates that the Arbitration Lost condition has been detected. 0: The Arbitration Lost condition has not been detected. 1: The Arbitration Lost condition has occurred during master sending, or"1" is written to the MSS bit when the bus is being used by another system.* This bit will be cleared when "0" is written to the INT bit.[Restriction]In any multiple-master environment, this interface cannot use such a mode that this interface and another master send a general call address while this interface treats the second and subsequent bytes as Arbitration Lost.

4 LRB 0 R

Last Received BitThis bit stores the ninth bit of the data that indicates Acknowledge (ACK) or Negative Acknowledge (NACK). 0: Acknowledge (ACK) detected. 1: Negative Acknowledge (NACK) detected.* This bit is cleared upon Start or Stop condition detection.

3 TRX 0 R

Transfer/ReceiverThis bit indicates whether data is being sent or received. 0: Receiving. 1: Sending.

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2 AAS 0 R

Address As SlaveThis bit indicates that the Arbitration Lost condition has been detected. 0: In slave mode, this interface has not been addressed. 1: In slave mode, this interface has been addressed.* This bit is cleared upon Start or Stop condition detection.

1 GCA 0 R

General Call AddressThis bit indicates that a general call address (00H) has been detected. 0: In slave mode, this interface has not received a general call address. 1: In slave mode, this interface has received a general call address.* This bit is cleared upon Start or Stop condition detection.

0 FBT 0 R

First Byte TransferThis bit indicates that the first byte has been detected. 0: The receive data is not the first byte. 1: The receive data is the first byte (address data).* This bit will be set to "1" upon Start condition detection. This bit will be

cleared when "0" is written to the INT bit or when the interface has not been addressed in slave mode.

* All bits of this register will be cleared while the EN bit of CCR is "0".


R/W Function

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5.5.2.2 Bus Control Register (BCR) This register controls the I2C bus.


0001H BER BEIE SCC MSS ACK GCAA INTE INT

R/W R/W R/W R/W R/W R/W R/W R/W R/W


Bit Bit name Initial value

R/W Function

7 BER 0 R/W

Bus ERrorThis bit is a bus error interrupt request flag.

• Write

0: Clears the bus error interrupt request flag.1: Not relevant.

• Read

0: No bus error has been detected.1: Incorrect Start or Stop condition has been detected during data

transfer.* If this bit is set, the EN bit of CCR is cleared to stop this interface.

Data transfer will then be suspended.

6 BEIE 0 R/W

Bus Error Interrupt EnableThis bit enables bus error interrupts.0: Bus error interrupts disabled.1: Bus error interrupts enabled.* if this bit is "1", an interrupt will occur when the BER bit is set to

"1".

5 SCC 0 R/W

Start Condition ContinueThis bit indicates that Start condition has occurred.

• Write

0: Not relevant.1: Start condition is regenerated in master transfer mode.* This bit is always "0" when read.

4 MSS 0 R/W

Master Slave SelectThis bit indicates the master or slave selection

• Write

0: The interface generates Stop condition and will enter slave mode when transfer ends.

1: The interface enters master mode, generates Start condition, and begins transfer.

* When an arbitration lost condition occurs during master transfer, this bit will be cleared to cause the interface to enter slave mode.

[Restriction]In any multiple-master environment, this interface cannot use such a mode that this interface and another master send a general call address while this interface treats the second and subsequent bytes as Arbitration Lost.

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Chapter5 I2C IF

3 ACK 0 R/W

ACKnowledgeThis bit permits Acknowledge to be generated when data has been received. 0: Acknowledge is not generated. 1: Acknowledge is generated.* This bit is invalid when the interface is receiving address data in

slave mode.

2 GCAA 0 R/W

General Call Address AcknowledgeThis bit permits Acknowledge to be generated when a general call address has been received.0: Acknowledge is not generated.1: Acknowledge is generated.

1 INTE 0 R/W

INTerrupt EnableThis bit enables interrupts.0: Interrupts disabled.1: Interrupts enabled.* if this bit is "1", an interrupt will occur when the INT bit is set to

"1".

0 INT 0 R/W

INTerruptThis bit requests a transfer end interrupt.

• Write

0: Clears the transfer end interrupt request flag.1: Not relevant.

• Read

0: Transfer has not ended.1: When the transfer of one byte including the Acknowledge bit ends,

this bit will be set if one of the following conditions is satisfied: - The interface is a bus master.- The interface is an addressed slave.- The interface has received a general call address. (Only with

GCAA = 1)- Arbitration Lost has occurred. (Only when the use of the bus is

acquired)- The interface has attempted to generate Start condition when

another system is using the bus.* While this bit is "1", the SCL line is held low (at "L" level). This bit

is cleared when "0" is written to it. As a result, the SCL line will be released for the transfer of the next byte. In master mode, this bit will be reset to "0" upon Start or Stop condition detection.

* All bits of this register except bits 7 and 6 will be cleared while the EN bit of CCR is "0".


R/W Function

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<Notes>

When an instruction to generate Start condition based on the timing specified in Figure5.5-1 and Figure 5.5-2 is executed (to set 1 on the MSS bit), no interrupt (INT bit = 1)due to Arbitration Lost detection (AL bit = 1) will occur.

• Condition 1 for inhibiting the generation of an interrupt (INT bit = 1) due to Al bit = 1detection

Executing an instruction to generate Start condition (setting the MSS bit of BCR to "1")when Start condition has not been detected (BB bit = 0) and the SDA or SCL pin is low

Figure 5.5-1 Timing chart for not generating an interrupt due to the detection of AL bit = 1

SCL pin

SDA pin

I2C operation permitted (EN bit = 1)

Master mode (MSS bit = 1)

Arbitration Lost detected (AL bit = 1)

Bus Busy (BB bit)

Interrupt (INT bit)

1

"L"

"L"

0

The SCL or SDA pin is low.

0

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Chapter5 I2C IF

• Condition 2 for inhibiting the generation of an interrupt (INT bit = 1) due to Al bit = 1detection

Executing an instruction to generate Start condition (setting the MSS bit of BCR to 1)

by permitting the I2C to perform operation (setting the EN bit = 1) when another

master is exclusively using the I2C bus.

This is because, as shown in Figure 5.5-2 , if another master on the I2C bus beginscommunication when the I2C is disabled from performing operation (EN bit = 0), the

I2C bus is exclusively used for the reason of Start condition not detected (BB bit = 0).

Figure 5.5-2 Timing chart for not generating an interrupt due to the detection of AL bit = 1

If the above event could occur, perform the following procedure as a softwareworkaround.

1)Execute an instruction to generate Start condition (set the MSS bit to "1").

2)Using a timer or similar function, wait* for the time required to send 3 bits of data

based on I2C transfer frequency set on CCR.

Example: If the I2C frequency is 100 kHz:Time required to send 3 bits of data: 1/(100 x 103) x 3 = 30 us

3)Observe the AL and BB bits of BSR. If AL bit = 1 and BB bit = 0, set the EN bit of

CCR to "0" to initialize the I2C.If the AL and BB bits are in other state, the interfacewill perform ordinary processing.

ACK ACKSLAVE ADDRESS DAT

SCL pin

SDA pin

BBbit

INTbit

Start ConditionStop ConditionAt the ninth clock pulse,

no INT bit interrupt occurs

ENbit

MSSbit

ALbit

0

0

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Chapter5 I2C IF

A flow example is shown below.

* Once Arbitration Lost is detected, it is ensured that AL bit =1 will result after the time

required to send 3 bits of data based on the I2C transfer frequency elapsessubsequent to the setting of the MSS bit to "1".

• Example of generating an interrupt (INT bit = 1) due to Al bit = 1 detection

Once an instruction to generate Start condition (to set the MSS bit to "1") is executedto cause Arbitration Lost after Bus Busy (BB bit = 1) has been detected, an INT bitinterrupt will occur when AL bit = 1 is detected.

Figure 5.5-3 Timing chart for generating an interrupt when AL bit = 1 is detected

Set master mode.Set the MSS bit of the

Bus Control Register (BCR) to "1"

Wait for the time required to send 3 bits of data based on the I2C transfer

frequency specified on the clock control register (ICCR).

BB bit = 0 and AL bit = 1

Yes

No

To ordinary processingInitialize I2C by

setting the EN bit to "0".

ACKSLAVE ADDRESS DAT

SCL pin

SDA pin

BBbit

INTbit

Start Condition

Release CSL by clearing the INT bit under software control

Interrupt at the ninth clock pulse

ENbit

MSSbit

ALbit

Clearing the AL bit under software control

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5.5.2.3 Clock Control Register (CCR)

The fscl value must not exceed the following when the interface works as a master.

Standard mode: 100 kHz

Fast mode: 400 kHz

• Standard mode

fscl = /((2 x m) + 2 ) : System clock*

• Fast mode

fscl = /(int(1.5 x m) + 2) : System clock *

int() means rounding down to a whole number.

* System clock means the external interface clock (MCLKO) described in Chapter 2, "FR

CORE FUNCTIONS."


0002H HSM EN CS4 CS3 CS2 CS1 CS0

R/W - R/W R/W R/W R/W R/W R/W R/W



R/W Function

7 - 1 -Not used.Always "1" when read.

6 HSM 0 R/W

High Speed ModeThis bit sets standard or fast mode.0: Standard mode1: Fast mode

5 EN 0 R/W

ENableThis bit permits operation.0: Operation inhibited.1: Operation permitted.* If this bit is "0", the bits in BSR and BCR (except the BER and BEIT

bits) are cleared. This bit will be cleared when the BER bit is set.

4:0CS4 - CS0

00000 R/W

Clock Period Select 4 to 0These bits specify the serial transfer clock frequency.The bus clock frequency limit can be increased by setting CSR. (For further information, see the description of CSR.)If CSR is not used (used as initialized), the serial transfer clock frequency fscl is specified by the equation on the next page.

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Chapter5 I2C IF

<Notes>

Two more cycles are minimum overhead required to check that the SCL pin output levelhas changed. The overhead will be greater if the delay involved in the SCL pin startup issignificant or if the clock is prolonged by a slave device.

The m value relates to each combination of CS4 to CS0 values as follows:

CS4 CS3 CS2 CS1 CS0m

Standard Fast

0 0 0 0 0 65 Cannot be set








0 1 0 0 0 73 9

0 1 0 0 1 74 10

0 1 0 1 0 75 11

0 1 0 1 1 76 12

0 1 1 0 0 77 13

0 1 1 0 1 78 14

0 1 1 1 0 79 15

0 1 1 1 1 80 16

1 0 0 0 0 81 17

1 0 0 0 1 82 18

1 0 0 1 0 83 19

1 0 0 1 1 84 20

1 0 1 0 0 85 21

1 0 1 0 1 86 22

1 0 1 1 0 87 23

1 0 1 1 1 88 24

1 1 0 0 0 89 25

1 1 0 0 1 90 26

1 1 0 1 0 91 27

1 1 0 1 1 92 28

1 1 1 0 0 93 29

1 1 1 0 1 94 30

1 1 1 1 0 95 31

1 1 1 1 1 96 32

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5.5.2.4 Address Register (ADR)

5.5.2.5 Data Register (DAR)


0003H A6 A5 A4 A3 A2 A1 A0

R/W - R/W R/W R/W R/W R/W R/W R/W



R/W Function

7 - 1 -Not used.Always "1" when read.

6:0 A6 - A0 - R/W

Address 6 to 0These bits contain the slave address.* In slave mode, after address data is received, it is compared with the

contents of DAR. If the two match, Acknowledge is sent to the master.


0004H D6 D6 D5 D4 D3 D2 D1 D0


Initial value - - 0 0 0 0 0 0

Bit Bit name

Initial value

R/W Function

7:0 D7 - D0 - R/W

Data 7 to 0These bits contain serial data.* This is a data register used for serial transfer that begins with MSB and

proceeds towards LSB. When data is received (TRX = 0), the data output is "1". Double buffering is used on the write side of this register. If the bus is being used (BB = 1), the write data for each byte to be transferred is loaded to the serial transfer register. Since, at the time of reading, the serial transfer register is directly read, the received data is only valid when the INT bit is set.

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Chapter5 I2C IF

5.5.2.6 Extended CS Register (CSR)

The fscl value must not exceed the following when the interface works as a master.

Standard mode: 100 kHz

Fast mode: 400 kHz

• Standard mode

fscl = /((2 x m) + 2 ) : System clock*

• Fast mode

fscl = /(int(1.5 x m) + 2) : System clock *

int() means rounding down to a whole number.


CORE FUNCTIONS."

Notes:

Two more cycles are minimum overhead required to check that the SCL pin output levelhas changed. The overhead will be greater if the delay involved in the SCL pin startup issignificant or if the clock is prolonged by a slave device.

When the extended CS register is used, the m value is the value specified by CS10 - CS0 plus

1.


0005H TST1 TST0 CS10 CS9 CS8 CS7 CS6 CS5




R/W Function

7:6TST1 - TST0

00 R/W

Test ModeThis bit indicates test mode.00: Normal mode.Other than 00: Test mode.

5:0 CS10 - CS5 000000 R/W

Clock Period Select 10 to 5These bits are set to increase the bus clock frequency limit by extending CS4-CS0 of CCR.The initial value of CS10 - CS5 is "000000". Setting these bits to another value causes frequency limit increase mode to be in effect.000000 : The bus clock frequency limit cannot increase.

(Only CS4 - CS0 are used.)Other than "000000": The bus clock frequency limit can be increased.

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Chapter5 I2C IF

5.5.2.7 Bus clock frequency register (FSR)


0006H FS3 FS2 FS1 FS0

R/W - - - - R/W R/W R/W R/W



R/W Function

7:4 - 0000- Not used.

Always "0000" when read.

3:0 FS3 - FS0 0001 R/W

Bus Clock Frequency Select 3 to 0These bits are used to select the bus clock frequency to be used. Setting this register specifies noise filter characteristics. Typical values are indicated below. However, adjustment may be required depending on the

noise status on the I2C bus.

Table 5.5-1 Bus Clock Frequency Select

FS3 FS2 FS1 FS0 Frequency [MHz]

0 0 0 0 Cannot be set

0 0 0 1 At least 14 and less than 20











1 1 0 0 -

1 1 0 1 -

1 1 1 0 -

1 1 1 1 -

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Chapter5 I2C IF

5.5.2.8 Bus Control 2 Register (BC2R)


0007H SDAS SCLS SDAL SCLL

R/W - - R R - - R/W R/W



R/W Function

7:6 - 00 -Not used.Always "00" when read.

5 SDAS - R

SDA StatusThis bit indicates the signal level of the SDA line subsequent to the noise filter.0: The SDA line is "0".1: The SDA line is "1".

4 SCLS - R

SCL StatusThis bit indicates the signal level of the SCL line subsequent to the noise filter.0: The SCL line is "0".1: The SCL line is "1".

3:2 - 00 -Not used.Always "00" when read.

1 SDAL 0 R/W

SDA Low driveThe SDA output is forced to become low.0: The SDA output works normally.1: The SDA output is forced to become low.

0 SCLL 0 R/W

SCL Low driveThe SCL output is forced to become low.0: The SCL output works normally.1: The SCL output is forced to become low.

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5.6 OperationThe I2C bus includes one serial data line (SDA) and one serial clock line (SCL) for bidirec-

tional communication. This interface is furnished with an SDA input (SDAI) and SDA output

(SDAO) for SDA and connects to the SDA line via an open-drain IO cell. The interface is also

furnished with an SCL input (SCLI) and SCL output (SCLO) for SCL and connects to the SCL

line via an open-drain IO cell. The interface connects to the SDA and SCL lines using wired

logic.

5.6.1 Start conditionWhen "1" is written to the MSS bit while the bus is open (BSR BB = 0 and BCR MSS = 0),

this interface enters master mode and generates Start condition. In master mode, Start condi-

tion can be generated again by writing "1" to the SCC bit even when the bus is being used (BB

= 1).

Start condition is generated in one of the following two conditions:

(i) When the bus is not being used (BSS = 0, BB = 0, INT = 0, and AL = 0), "1" is written to

the MSS bit.

(ii)After an interrupt has occurred (MSS = 1, BB = 1, INT = 1, and AL = 0) in bus master

mode, "1" is written to the SCC bit.

When "1" is written to the MSS bit while the interface is idling, the AL bit is set to "1".

Except in the condition described in (i) or (ii) above, writing "1" to the MSS or SCC bit is

ignored.

Start condition on the I2C busStart condition is defined as the condition that the SDA line changes from "1" to "0" when the

SCL line remains "1".

Start condition

SDA

SCL

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5.6.2 Stop conditionWhen "1" is written to the MSS bit in master mode (MSS = 1), the interface generates Stop

condition and becomes a slave.

The requirement for Stop condition generation is as follows:

• After an interrupt has occurred (MSS = 1, BB = 1, INT = 1, and AL = 0) in bus master

mode, "0" is written to the MSS bit.

If the above requirement is not satisfied, writing "0" to the MSS bit will be ignored.

Stop condition on the I2C busStop condition is defined as the condition that the SDA line changes from "0" to "1" when the

SCL line remains "1".

Stop condition

SDA

SCL

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Chapter5 I2C IF

5.6.3 AddressingIn master mode, after Start condition is generated, BB and TRX are set to "1" and the contents

of DAR are output, beginning with MSB. When Acknowledge is received from the slave after

sending the address data, the inversion of bit 0 of the send data (bit 0 of DAR after sending) is

stored in the TRX bit.

In slave move, after Start condition is generated, BB is set to "1" and RX is set to "0". The

send data from the master is assigned to DAR. The contents of DAR as it receives the address

data are compared with the ADR contents. If the two agree, AAS is set to "1" to send

Acknowledge to the master. Bit 0 of the receive data (bit 0 of DAR after reception) is then

assigned to the TRX bit.

Slave address transfer formatThe slave address transfer format is as follows:

Slave address mapThe slave address map is shown below.

*1 This macro does not support 10-bit slave addresses.

MSB LSB 0

6 5 4 3 2 1 0 R/W ACK

Slave address

Slave address R/W Description

0000 000 0 General call address

0000 000 1 Start byte

0000 001 X CBUS address

0000 010 X Reserved

0000 011 XReserved

0000 0XX X

0001 XXX

1110 XXX

X Available slave addresses

1111 0XX X 10-bit slave address*1

1111 1XX X Reserved

-

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5.6.4 SCL synchronization adjustmentIf multiple I2C devices become master devices at nearly the same times and drive the SCL line,

the individual devices sense the SCL line status and adjust the SCL line drive timing of all

devices automatically to that of late devices.

SCL line

Macro A

SCLO (before adjustment)

Once the SCL line becomes high, wait until the next condition SCLO = L occurs

Once the SCL line becomes high, wait until the next condition SCLO = L occurs.

SCLO (after adjustment)

SCLO (before adjustment)

SCLO (after adjustment)

Macro B

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5.6.5 ArbitrationArbitration occurs if this interface is sending data as a master when another master is also send-

ing data at the same time. If the interface recognizes that its send data is "1" when the data on

the SDA line is "0", it considers that it has lost arbitration and sets AL to "1".

If the interface attempts to generate Start condition when another master is using the bus, it is

assumed that the interface loses arbitration. As a result, AL is set to "1".

Also suppose that the interface ensures that the bus is not being used by another device and that

it writes "1" to MSS. If it detects a Start condition that has been generated by another master

before its own Start condition is generated, it is assumed that the interface has lost arbitration.

As a result, AL is set to "1".

When the AL bit is set to "1", MSS and TRX becomes "0", indicating that the interface has

entered slave receive mode.

A master that has lost arbitration (has lost the right to use the bus) stops driving SDA. How-

ever, SCL drive will remain effective until the transfer of the current byte ends and the

interrupt is cleared.

SDA line

SCL line

Macro A

SDAI

The interface has right to use the bus because the input and output match.

The interface has right to use the bus because the input and output do not match.

SDAO

SDAI

SDAO

Macro B

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5.6.6 Acknowledge and Negative AcknowledgeThe ninth bit of data indicates Acknowledge (ACK) or Negative Acknowledge (NACK). If it

is "0", it indicates Acknowledge, whereas if it is "1", it indicates Negative Acknowledge.

The receiving end sends Acknowledge or Negative Acknowledge to the sending end. When

data is received, Acknowledge or Negative Acknowledge is stored in the LRB bit.

If the slave sending end does not receive Acknowledge from the receiving end (instead, has

received Negative Acknowledge), TRX is set to "0", indicating that the slave sending end has

entered slave receive mode.

As a consequence, the master can generate Stop condition when the slave frees SCL.

The clock is generated by the mask.

ACK

ACK

The sending end frees the bus to ensure that the receiving end can output ACK/NACK.

The receiving end returns ACK/NACK to the sending end.

1 2 3 4 5 6 7 8 9

SDA line

SCL line

Macro A (sending)

SDAO

SCLO

SDAO

SCLO

Macro B (receiving)

183

Chapter5 I2C IF

5.6.7 Bus errorsIf one of the following conditions is satisfied, it is judged as a bus error, which leads to stop-

ping of this interface.

(i) Detection of basic rule violation on the I2C bus during data (including the ACK bit) transfer

(ii)Detection of Stop condition in master mode

(iii)Detection of basic rule violation on an I2C bus that is idling.

(iv)

5.6.8 Initialization

SDA line

SCL line

SDA changes because SCL goes high during data transfer.

D5

321START

D0D7

Start

Slave address setting

Clock frequency settingMacro enable setting

Interrupt setting

End

ADR: Write

CCR: Write CS [4:0]: Write EN: Write 1

BCR: Write BER: Write 0 BEIE: Write 1 INT: Write 0 INTE: Write 1

184

Chapter5 I2C IF

5.6.9 One-byte transfer from a master to a slave

Master SlaveStart

DAR: WriteMSS: Write 1

Start condition

BB set, TRX setBB set, TRX set

Address data transfer

AAS set

AcknowledgeLRB reset

INT set, TRX reset INT set, TRX set

Interrupt ACK: Write 1

INT: Write 0 INT: Write 0

Data transfer

Acknowledge

LRB resetINT set

INT set Interrupt INT: Write 0DAR: Read

DAR: Write

MSS: Write 0INT resetBB reset, TRX reset Stop condition

BB reset,TRX resetAAS reset

End

185

Chapter5 I2C IF

5.6.10 One-byte transfer from a slave to a maser

Master SlaveStart

DAR: WriteMSS: Write 1

Start condition

BB set, TRX setBB set, TRX set

Address data transfer

AAS set

AcknowledgeLRB reset

INT set, TRX reset INT set, TRX set

Interrupt DAR: Write

INT: Write 0 INT: Write 0

Data transfer

Negative Acknowledge

INT setINT set

LRB set, TRX set

DAR: Read Interrupt INT: Write 0

ACK: Write

MSS: Write 0INT resetBB reset, TRX reset Stop condition

BB reset,TRX resetAAS reset

End

186

Chapter5 I2C IF

5.6.11 Recovery after a bus error

5.6.12 Interrupt processing and wait request to the master deviceThe SCL output is left low while the INT flag in BCR remains high (an interrupt that has been

generated by this interface is being handled by the CPU). As long as the slave holds the SCL

line low, the master cannot generate the next transfer clock. This means that the slave forces

the master to wait.

Start

Error flag reset

Clock frequency settingMacro enable setting

Interrupt setting

End

ADR: Write BER: Write 0 BEIE: Write 01

CCR: Write CS [4:0]: Write EN: Write 1

BCR: Write BER: Write 0 BEIE: Write 1 INT: Write 0 INTE: Write 1

187

Chapter5 I2C IF

5.7 Caution

5.7.1 System clock and fsclThis interface should receive a system clock that is included in the following range:

If the system clock exceeds 18 MHz, CSR setting will be required for communication.

• Master operation: 14 MHz to 33 MHz

• Slave operation: 14 MHz to 33 MHz


CORE FUNCTIONS."

CCR setting is required to ensure that fscl will not exceed the following limit. If fscl exceeds

the limit in any mode, normal transfer will not be guaranteed because a timing rule on the I2C

bus is violated.

Standard: 100 KHz

Fast: 400 KHz

5.7.2 10-bit slave addressThis interface does not support 10-bit slave addresses. Therefore, do not specify slave

addresses 78H to 7bH when using this interface. If a slave address in this range is specified

inadvertently, normal transfer will not be guaranteed although Acknowledge is returned after

the reception of one byte.

188

Chapter5 I2C IF

5.7.3 Competition of the SCC, MSS, and INT bitsIf the SCC, MSS, and INT bits are set at the same time, Next byte transfer, Start condition gen-

eration, and Stop condition generation occur as competing events. These events are assigned

priorities as follows:

(i) Next byte transfer and Stop condition generation

If "0" is written to the INT and MSS bits, priority is placed on the MSS bit, meaning that

Stop condition is generated.

(ii)Next byte transfer and Start condition generation

If "0" is written to the INT bit and "1" is written to the SCC bit, priority is placed on the

SCC bit, meaning that Start condition is generated.

(iii)Start condition generation and Stop condition generation

Writing "1" to the SCC bit and "0" to the MSS bit at the same time is inhibited.

5.7.4 Serial transfer clock settingIf the delay involved in the SCL pin startup is significant or if the clock is prolonged by a slave

device, overhead will be generated. As a result, the serial transfer clock may be lower than the

theoretical value (setting).

5.7.5 Restriction on sending global call address when multiple masters are in useIf this interface is used by multiple masters, this interface cannot use such a mode that this

interface and another master send a general call address while this interface treats the second

and subsequent bytes as Arbitration Lost.

The following usage is permitted despite the above restriction.

• This interface is used in a single-master environment.

• This interface is used in a multiple-master environment, but does not send general call

addresses.

• This interface is used in a multiple-master environment, but anything other than this

interface does not send general call addresses.

• This interface is used in a multiple-master environment and this interface and another

master send general call addresses, but this interface does not treat the second and

subsequent bytes as Arbitration Lost.*

* Since the master that has sent a larger value of data encounters Arbitration Lost, the

requirement is that the second byte and subsequent send data be always smaller than that

sent by the other master.

189

Chapter5 I2C IF

5.8 Flowchart SampleShown below is a flowchart sample for communication using this interface.

Address setting

End

Interrupt setting

Clock and EN setting

Error reset setting

End

Interrupt setting

Clock and EN settingRemote party address

and send settingRemote party address

and receive setting

Start condition and address sendingWAIT

WAITError reset

BCR readBSR read

Arbitration fault?(MSS or MSB)

Temporary cancellation of EN setting

End

Receive

Send

Master sending

Error resetInitialization

* The bus may be hung because of a fixed low level. If the bus is hung, recovery or system reboot is required.

Send or receive?

(0)

(1)

190

Chapter5 I2C IF

WAIT(10*PCLK)

WAIT(10*PCLK)

WAIT(100*PCLK)

No

Yes

Temporary cancellation of EN setting

(OCR: B)

Slave?(BSR_AAS or OCL)

Send or receive?(BSR_TRX)

Error reset

Master communication (repeated)

Master communication

in progress?

* Wait until the interrupt is deactivated due after error reset.

End

Error reset

End

BCR readBSR read

Bus error?(BCRBER)

Arbitration fault?(BCRBER)

Master communication in progress?

(BCRMSS)

Send or receive?(BSRTRX)

4 6 2 3

Master data sending

Master data receiving

Slave data sending

Slave data receiving

Interrupt processing

(1)

(0)

(0)

(0)

(0)

(0)

(0)

(1)

(1)

(1)

(1)

(1)

* Since BCR MSS is cleared upon bus error detection, a judgment flag is required outside the macro.

* Before communication can resume, a wait period is required until the bus becomes stable at the high level.

Slave data sending

2

Slave data receiving

3

Address?(BSRFBT)

Received data read(Receive data: DAR)

Has the end of received data

reached?

ACK upon interrupt clearing and next

unit receiving(BCR: 0100_0110B)

NACK upon interrupt clearing and next


* Wait until the interrupt is actually deactivated after the issue of an interrupt clear instruction.

* During slave sending, a request to stop communication cannot be issued.

Any send data?

Send data setting(DAR: Communication

data)

Interrupt clearing and sending

(BCR*=0100_0100B)

WAIT (10*FCLE)

End

* GCA and ABB are used to judge whether the data is a global address call address or ordinary slave address.

Yes

No

(1)

(0)

Yes

No

191

Chapter5 I2C IF

End

Continue

(1)

(1)

(1)

(0)

(0)

(0)

Yes

No

Master data sending

Sending completed?

Slave NACK?(BBRLRB)

Send data setting(DAR: Send data)

Interrupt clearing and sending

(BCR: 0100_0110B)

WAIT(100*PCLE)

Interrupt clearing and Stop condition

(BCR: 0100_0110B)

WAIT (10*PCLK)

End

2

Master data receiving3

Address?(BSR_FTB)

Receive data read(Receive data: DAR)

Master NACK?(BSR_LRB)

Will receiving end with the next receive

data unit?

ACK upon interrupt clearing and next


NACK upon interrupt clearing and next


* The master can stop communication regardless of whether the reply is ACK or NACK.

* Wait until the interrupt is actually deactivated after the issue of an interrupt clear instruction.

192

Chapter5 I2C IF

Recovery from the condition that the macro is hung with SDA = low (the slave is in low-drive or bus-bypass status) when in ordinary master mode

(Forced clock input phase)

(Forced bus error phase)

Drive SDA low

Set SDA high

Wait for a one-bit period

Monitor SDA and SCL

SDA="1" and SCL="1"?

End

* Successful recovery

End

* Give up (recovery failure)

Start resetting system hung

condition

Master device absent?

Monitor SDA and SCL

SDA = D and SCL = L continued for a while?

End

* Communication with the master device is in progress.

Drive SCL low

Wait for a low-level period

Set SCL high

Wait for 0.6*[high-level period]

Monitor SDA

SDA="L"?

Wait for 0.6*[high-level period]

Have two clock pulses been supplied?

Yes

Yes

Yes

Yes

Yes

No

No

No

193

Chapter5 I2C IF

194

Chapter6BOOT ROM SELECTION

This LSI has a built-in boot ROM inside the chip, but it is possible to select an external device as a boot ROM.

195

Chapter6 BOOT ROM SELECTION

6.1 Built-in/External Boot ROM SelectionAfter reset cancellation, the FR core performs a boot access to the chip select 0 area: CSX0. In

this LSI, the CSX0 signal is normally selected to go to the built-in ROM and is not output

directly to the outside, however, by using the TEST signal pins, it is possible to switch to the

chip select signal (CSX[6]) which is output to the outside.

CSX[6]: When TEST[2:1] = 2’b11, CSX[0] is output.

At all other times it is CSX[6] output.

<Caution>

It is necessary to define the TEST pins before doing reset cancellation. Please refrainfrom altering the TEST pins after reset cancellation as this causes operational failures.

In addition, when selecting an external ROM, it is necessary to set the FR core internal

registers ACRO and MODR according to the device to be connected to CSX[6].

Furthermore, when an external ROM is selected, the CSX[6] area cannot be used.

Boot ROM selection block diagram

FR core

csx[6]csx[0]

CSX[6]

TEST[2]TEST[1]

Built-in ROM

csx[0]

01

196


TEST pin Boot ROM selection table

TEST[2] TEST[1] TEST[0] csx[0] (Boot ROM select signal)

1 0 0 Built-in ROM

1 0 1 Disabled

1 1 X CSX[6]

0 X X Disabled

197


198

Appendix

199

Appendix

Appendix AI/O MAP

The following table shows the memory space areas and the peripheral resources corresponding to each register.

[Legend of I/O map]

<Notes>

Register bit values indicate initial values as shown below:

"1": Initial value "1"

"0": Initial value "0"

"X": Initial value "X"

"-": Reserved area, cannot be accessed

Register

address +0 +1 +2 +3 block

0000_0000 H|

0000_003C H

- Reserved

0000_0040 H EIRR [R/W] ENIR [R/W] ELVR [R/W] Ext Int

00000000 00000000 00000000 00000000

Read/write attribute

Initial register value after reset

Register name (the register listed in the first column is at address 4n, the register listed in the second column is at address 4n + 2...)

Leftmost register address (the first column register is on the MSB sideof data in word access mode)

200

Appendix A I/O MAP

Appendix Table A-1 I/O Map (1 / 7)

addressRegister

block+0 +1 +2 +3

0000_0000 H|

0000_003C H

- Reserved

0000_0040 HEIRR [R/W]

00000000ENIR [R/W]

00000000ELVR [R/W]

00000000 00000000Ext Int

0000_0044 HDICR [R/W]

-------0HRCL [R/W]

0 - 11111- DLYI/I-unit

0000_0048 HTMRLR0 [W]

XXXXXXXX XXXXXXXXTMR0 [R]

XXXXXXXX XXXXXXXXReload Timer 0

0000_004C H -TMCSR0 [R/W]

----0000 00000000

0000_0050 HTMRLR1 [W]



0000_0054 H -TMCSR1 [R/W]

----0000 00000000

0000_0058 HTMRLR2 [W]



0000_005C H -TMCSR2 [R/W]

----0000 00000000

0000_0060 HSSR0 [R/W]

00001-00SIDR0 [R/W]XXXXXXXX

SCR0 [R/W]00000100

SMR0 [R/W]00----0-0-

UART0

0000_0064 HUTIM0 [R]00000000

(UTIMR0 [W])00000000

DRCL0 [W]--------

UTIMC0 [R/W]0-----00001

U-TIMER0

0000_0068 HSSR1 [R/W]

00001-00SIDR1 [R/W]XXXXXXXX

SCR1 [R/W]00000100

SMR1 [R/W]00-----0-0-

UART1

0000_006C HUTIM1 [R]00000000

(UTIMR1 [W])00000000

DRCL1 [W]--------

UTIMC1 [R/W]0-----00001

U-TIMER1

0000_0070 H|

0000_01FC H

- Reserved

201

Appendix

0000_0200 HDMACA0 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

DMAC

0000_0204 HDMACB0 [R/W]

00000000 00000000 00000000 00000000

0000_0208 HDMACA1 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

0000_020C HDMACB1 [R/W]

00000000 00000000 00000000 00000000

0000_0210 HDMACA2 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

0000_0214 HDMACB2 [R/W]

00000000 00000000 00000000 00000000

0000_0218 HDMACA3 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

0000_021C HDMACB3 [R/W]

00000000 00000000 00000000 00000000

0000_0220 HDMACA4 [R/W]

00000000 00000000 0000XXXX XXXXXXXX

0000_0224 HDMACB4 [R/W]

00000000 00000000 00000000 00000000

0000_0228 H|

0000_023C H

- Reserved

0000_0240 HDMACR [R/W]

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXXDMAC

0000_0244 H|

0000_0300 H

- Reserved

0000_0304 H -ISIZE [R/W]

------10Instruction Cache

0000_0308 H|

0000_03E0 H

- Reserved

0000_03E4 H -ICHRC [R/W]

0-000000Instruction Cache

0000_03E8 H|

0000_03EC H

- Reserved

0000_03F0 HBSD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search Module

0000_03F4 HBSD1 [R/W]


0000_03F8 HBSDC [W]


0000_03FC HBSRR [R]


0000_0400 H|

0000_043C H

- Reserved


addressRegister

block+0 +1 +2 +3

202

Appendix A I/O MAP

0000_0440 HICR00[R/W]

---11111ICR01[R/W]

---11111ICR02[R/W]

---11111ICR03[R/W]

---11111

Interrupt Control Unit

0000_0444 HICR04[R/W]

---11111ICR05[R/W]

---11111ICR06[R/W]

---11111ICR07[R/W]

---11111

0000_0448 HICR08[R/W]

---11111ICR09[R/W]

---11111ICR10[R/W]

---11111ICR11[R/W]

---11111

0000_044C HICR12[R/W]

---11111ICR13[R/W]

---11111ICR14[R/W]

---11111ICR15[R/W]

---11111

0000_0450 HICR16[R/W]

---11111ICR17[R/W]

---11111ICR18[R/W]

---11111ICR19[R/W]

---11111

0000_0454 HICR20[R/W]

---11111ICR21[R/W]

---11111ICR22[R/W]

---11111ICR23[R/W]

---11111

0000_0458 HICR24[R/W]

---11111ICR25[R/W]

---11111ICR26[R/W]

---11111ICR27[R/W]

---11111

0000_045C HICR28[R/W]

---11111ICR29[R/W]

---11111ICR30[R/W]

---11111ICR31[R/W]

---11111

0000_0460 HICR32[R/W]

---11111ICR33[R/W]

---11111ICR34[R/W]

---11111ICR35[R/W]

---11111

0000_0464 HICR36[R/W]

---11111ICR37[R/W]

---11111ICR38[R/W]

---11111ICR39[R/W]

---11111

0000_0468 HICR40[R/W]

---11111ICR41[R/W]

---11111ICR42[R/W]

---11111ICR43[R/W]

---11111

0000_046C HICR44[R/W]

---11111ICR45[R/W]

---11111ICR46[R/W]

---11111ICR47[R/W]

---11111

0000_0470 H|

0000_047C H

Reserved

0000_0480 HRSRR [R/W]

10000000 (*2)STCR [R/W]

00110011 (*2)TBCR [R/W]

00XXXX00 (*1)CTBR [R/W]XXXXXXXX

Clock Control Unit0000_0484 H

CLKR [R/W]00000000

WPR [W]XXXXXXXX

DIVR0 [R/W]00000011 (*1)

DIVR1 [R/W]00000000

0000_0488 H|

0000_063F H

- Reserved


addressRegister

block+0 +1 +2 +3

203

Appendix

0000_0640 HASR0 [R/W]

00000000 00000000ACR0 [R/W]

1111**00 00000000 (*3)

Memory IF

0000_0644 HASR1 [R/W]

XXXXXXXX XXXXXXXXACR1 [R/W]

XXXXXXXX XXXXXXXX

0000_0648 HASR2 [R/W]


XXXXXXXX XXXXXXXX

0000_064C HASR3 [R/W]


XXXXXXXX XXXXXXXX

0000_0650 HASR4 [R/W]


XXXXXXXX XXXXXXXX

0000_0654 HASR5 [R/W]


XXXXXXXX XXXXXXXX

0000_0658 HASR6 [R/W]


XXXXXXXX XXXXXXXX

0000_065C HASR7 [R/W]


XXXXXXXX XXXXXXXX

0000_0660 HAWR0 [R/W]

01111111 11111111AWR1 [R/W]

XXXXXXXX XXXXXXXX

0000_0664 HAWR2 [R/W]

XXXXXXXX XXXXXXXXAWR3 [R/W]

XXXXXXXX XXXXXXXX

0000_0668 HAWR4 [R/W]


XXXXXXXX XXXXXXXX

0000_066C HAWR6 [R/W]


XXXXXXXX XXXXXXXX

0000_0670 HMCRAMCRB

XXXXXXXX XXXXXXXX -

0000_0674 H -

0000_0678 HIOWR0 [R/W]XXXXXXXX

IOWR1 [R/W]XXXXXXXX

IOWR2 [R/W]XXXXXXXX

-

0000_067C H-

0000_0680 HCSER [R/W]

00000001CHER [R/W]XXXXXXX1

-TCR [R/W]

00000000 (*1)

0000_0684 HRCR

00XXXXXX 00XXXXXX- Memory IF

0000_0688 H|

0000_0FFC H

- Reserved


addressRegister

block+0 +1 +2 +3

204

Appendix A I/O MAP

0000_1000 HDMASA0 [R/W]


DMAC

0000_1004 HDMADA0 [R/W]


0000_1008 HDMASA1 [R/W]


0000_100C HDMADA1 [R/W]


0000_1010 HDMASA2 [R/W]


0000_1014 HDMADA2 [R/W]


0000_1018 HDMASA3 [R/W]


0000_101C HDMADA3 [R/W]


0000_1020 HDMASA4 [R/W]


0000_1024 HDMADA4 [R/W]


0000_1028 H|

0000_FFFC H

- Reserved

010F_0000 HBSR[R]

00000000BCR[R/W]00000000

CCR[R/W]10000000

ADR[R/W]1XXXXXXX

I2C010F_0004 HDAR[R/W]

XXXXXXXXCSR

00000000FSR

00000001BC2R[R/W]00XX0000

010F_0008 H|

010F_FFFF H

(Reserved)-

0110_0000 HDLCR0[*4]0X000000

DLCR1[R/W]00000000

DLCR2[*4]00000000

DLCR3[R/W]00000000

LAN controller0110_0004 HDLCR4[*4]00000010

DLCR5[*4]01000001

DLCR6[*4]10000000

DLCR7[*4]00000000

0110_0008 HDLCR8[R/W]

00000000DLCR9[R/W]

00000000DLCR10[R/W]

00000000DLCR11[R/W]

00000000

0110_000C HDLCR12[R/W]

00000000

DLCR13[R/W] --

--00000000


addressRegister

block+0 +1 +2 +3

Bank 0

205

Appendix

0110_0008 HMAR8[R/W]

00000000MAR9[R/W]

00000000MAR10[R/W]

00000000MAR11[R/W]

00000000

LAN controller

0110_000C HMAR12[R/W]

00000000MAR13[R/W]

00000000MAR14[R/W]

00000000MAR15[R/W]

00000000

0110_0008 H--

--

BMPR10[*]00000000

--

0110_000C HBMPR12[*]00000000

--

BMPR14[*]00000000

--

0110_0010 HBMPR8

00000000-00000000[R/W]

00000000-00000000

0110_0014 H--

tbl_filter_cmd[R/W]00000000-XXX0XXX0

0110_0018 H--

--

--

tbl_filter_status[R/W]

XXXXXXX0

0110_001C Htbl_filter_data[R/W]

00000000-00000000-00000000-00000000

0110_0020 H--

--

fl_control[R/W]XXXXX000-00000000

0110_0024 Hfl_subnet[R/W]

11111111-11111111-11111111-11111111

0110_0028 H--

--

SMI_CMD[R/W]00000000-00000000

SMI IF

0110_002C H--

--

--

SMI_CMD_ST[R]XXXXXX00

0110_0030 H--

--

SMI_DATA[R/W]00000000-00000000

0110_0034 H--

--

SMI_POLLINTVL[R/W]00000000-00000000

0110_0038 H--

--

--

SMI_PHY_ADD[R/W]

XXX00000

0110_003C H--

--

--

SMI_CONTROL [R/W]

XXXXX111

0110_0040 H--

--

--

SMI_STATUS[R]XXXXXXXX

0110_0044 H--

--

--

SMI_INTENABLE [R/W]

XXXXXXX0

0110_0048 H--

--

--

SMI_MDCDIV [R/W]

XXX01011


addressRegister

block+0 +1 +2 +3

Bank 1

Bank 2

206

Appendix A I/O MAP

0114_0000 HEXIFRXDR [R]

00000000-00000000 00000000-00000000

External IF

0114_0004 HEXIFTXDR [W]

00000000-00000000 00000000-00000000

0114_0008 HEXIFRXR[R]

00000000-00000000--

0114_000C HEXIFTXR[W]

00000000-00000000--

0114_0010 H--

EXIFCR[W]XXXXX000-00000000

0114_0014 H--

EXIFSR[R]XXXXXXXX-00000000

0114_0018 HEXIFRXSR

00000000-00000000[R]

00000000-00000000

0114_001C HEXIFTXSR[R]

00000110-00000000--

0114_0020 H --

PACR[R/W]XXXXXXX0-00000000

GPIO(PORT A)0114_0024 H -

---

PADR[R/W]0000XXXX

0114_0030 H--

PBCR[R/W]XX000000-00000000-00000000

GPIO(PORT B)0114_0034 H

--

PBDR[R/W]XXXXXXXX-XXXXXXXX-XXXXXXXX

(*1) A register having a different initial value depending on the reset level. The value shown is the one at the INIT level.(*2) A register having a different initial value depending on the reset level. The value shown is the one at the INIT level

using the INITX.(*3) The initial value is set by the WTH bit of the mode vector(*4)The attribute is different according to the bit.


addressRegister

block+0 +1 +2 +3

207

Appendix

Appendix BInterrupt Vector

The interrupt vector table shown below illustrates interrupt factors of MB91403 and interrupt vectors/interrupt control registers that are assigned to them.

ICR - - - The interrupt level for each interrupt request is set in the register within the interrupt

controller.

ICRs are available for each interrupt request.

TBR - - - A register indicating the first address of the vector table for EIT.

Vector address will be the one, to that the offset value set for each TBR and EIT

factor is added to the address.

The 1-KB area from the address shown by TBR is the vector area for EIT.

4 bites are allowed for one vector, and the relationship between the vector number and the vec-

tor address is described as shown below.

vctadr = TBR + vctofs

= TBR + (3FC H - 4 * vct )

vctadr : vector address

vctofs : vector offset

vct : vector number

Table 2.0-1 Interrupt vector (1 / 3)

Interrupt factor

Interrupt number

Interrupt levelOffSet

TBR default

RNDecimal

Hexadeci-mal

address

Reset 0 00 - 3FCH 000FFFFCH -

Mode vector 1 01 - 3F8H 000FFFF8H -

System reserved 2 02 - 3F4H 000FFFF4H -

System reserved 3 03 - 3F0H 000FFFF0H -

System reserved 4 04 - 3ECH 000FFFECH -

System reserved 5 05 - 3E8H 000FFFE8H -

System reserved 6 06 - 3E4H 000FFFE4H -

Coprocessor absent trap 7 07 - 3E0H 000FFFE0H -

Coprocessor error trap 8 08 - 3DCH 000FFFDCH -

INTE instruction 9 09 - 3D8H 000FFFD8H -

Instruction break exception 10 0A - 3D4H 000FFFD4H -

Operand break trap 11 0B - 3D0H 000FFFD0H -

Step trace trap 12 0C - 3CCH 000FFFCCH -

NMI Request (tool) 13 0D - 3C8H 000FFFC8H -

Undefined-instruction exception 14 0E - 3C4H 000FFFC4H -

NMI Request 15 0F FH fixed 3C0H 000FFFC0H -

Ethernet MAC IF 16 10 ICR00 3BCH 000FFFBCH 4

Authentication macro 17 11 ICR01 3B8H 000FFFB8H 5

208

Appendix B Interrupt Vector

Reserved 18 12 ICR02 3B4H 000FFFB4H 8

External IF 19 13 ICR03 3B0H 000FFFB0H 9

I2C IF 20 14 ICR04 3ACH 000FFFACH -

GPIO 21 15 ICR05 3A8H 000FFFA8H -

External interrupt 6 22 16 ICR06 3A4H 000FFFA4H -


Reload timer 0 24 18 ICR08 39CH 000FFF9CH 6

Reload timer 1 25 19 ICR09 398H 000FFF98H 7

Reload timer 2 26 1A ICR10 394H 000FFF94H -

UART0 (RX completed) 27 1B ICR11 390H 000FFF90H 0

UART1 (RX completed) 28 1C ICR12 38CH 000FFF8CH 1

UART0 (TX completed) 29 1D ICR13 388H 000FFF88H 2

UART1 (TX completed) 30 1E ICR14 384H 000FFF84H 3

DMAC0(end, error) Ethernet MAC IF 31 1F ICR15 380H 000FFF80H -

DMAC1(end, error)External IF 32 20 ICR16 37CH 000FFF7CH -

DMAC2 (end ,error) 33 21 ICR17 378H 000FFF78H -

DMAC3 (end, error) 34 22 ICR18 374H 000FFF74H -

DMAC4 (end, error) 35 23 ICR19 370H 000FFF70H -

System reserved 36 24 ICR20 36CH 000FFF6CH -

System reserved 37 25 ICR21 368H 000FFF68H -





System reserved 42 2A ICR26 354H 000FFF54H -

System reserved 43 2B ICR27 350H 000FFF50H -

System reserved 44 2C ICR28 34CH 000FFF4CH -

U-TIMER0 45 2D ICR29 348H 000FFF48H -

U-TIMER1 46 2E ICR30 344H 000FFF44H -

Time-base timer overflow 47 2F ICR31 340H 000FFF40H -












Interrupt factor

Interrupt number


TBR default

RNDecimal

Hexadeci-mal

address

209

Appendix

System reserved 58 3A ICR42 314H 000FFF14H -

System reserved 59 3B ICR43 310H 000FFF10H -

System reserved 60 3C ICR44 30CH 000FFF0CH -

System reserved 61 3D ICR45 308H 000FFF08H -

System reserved 62 3E ICR46 304H 000FFF04H -

Delay interrupt factor bit 63 3F ICR47 300H 000FFF00H -

System reserved (Used by REALOS *1) 64 40 - 2FCH 000FFEFCH -

System reserved (Used by REALOS *1) 65 41 - 2F8H 000FFEF8H -

System reserved 66 42 - 2F4H 000FFEF4H -

System reserved 67 43 - 2F0H 000FFEF0H -

System reserved 68 44 - 2ECH 000FFEECH -

System reserved 69 45 - 2E8H 000FFEE8H -



System reserved 72 48 - 2DCH 000FFEDCH -

System reserved 73 49 - 2D8H 000FFED8H -

System reserved 74 4A - 2D4H 000FFED4H -

System reserved 75 4B - 2D0H 000FFED0H -

System reserved 76 4C - 2CCH 000FFECCH -

System reserved 77 4D - 2C8H 000FFEC8H -

System reserved 78 4E - 2C4H 000FFEC4H -

System reserved 79 4F - 2C0H 000FFEC0H -

Used by INT Instruction80|

255

50|

FF-

2BCH

|000H

000FFEBCH

|000FFC00H

-


Interrupt factor

Interrupt number


TBR default

RNDecimal

Hexadeci-mal

address

210

Appendix C Pin Statuses for Each CPU State

Appendix CPin Statuses for Each CPU State

The terms describing pin statuses have the following meanings:

1) Invalid

Does not sample inputs.

2) Valid

Samples the inputs and uses them as valid values.

3) Previous state held

Continues outputting in the same condition as that immediately before entering this mode.

211

Appendix

*1 In stop mode, The setting of HIZ = 1 is prohibited.

Pin name Sleep modeStop mode INITX

RemarksHIZ = 0 (*1)

D[31:16] Input state: Invalid ← ←A[22:0] Previous state held ← "L

RDY Invalid ← ←RDX "H ← ←

WRX [1:0] "H ← ←MCLKE Previous state held ← "H

SRASX "H ← ←SCASX "H ← ←WEX "H ← ←

MCLK0 Previous state held ← "L

CSX [7:6] "H ← ←INT [7:6] Valid ← Invalid

SIN [1:0] SIN [1:0] Invalid ←

SOUT [1:0] SOUT [1:0] Previous state

held"H

SCK [1:0] SCK [1:0] Previous state

heldInvalid

TXCLK Invalid ← ←TXD [3:0] Previous state held ← "L

TXEN Previous state held ← "L

RXCLK Invalid ← ←RXER Invalid ← ←

RXD [3:0] Invalid ← ←RXDV Invalid ← ←RXCRS Invalid ← ←

COL Invalid ← ←MDCLK Previous state held ← "L

MDIO Previous state held ← Invalid

EXCSX/PB [21] Invalid / Previous state

held← Invalid

EXA/PB [20] Invalid / Previous state

held← Invalid

EXRDX/PB [19] Invalid / Previous state

held← Invalid

EXWRX/PB [18] Invalid / Previous state

held← Invalid

DREQRX/PB [17] Previous state held ← "H

DREQTX/PB [16] Previous state held ← "H

EXD [15:0]/PB [15:0] Previous state held ← Invalid

PA [3:0] Previous state held ← Invalid

SDA Previous state held ← Invalid

SCL Previous state held ← Invalid

212

Appendix D Precautions When Using a Little Endian Area

Appendix DPrecautions When Using a Little Endian Area

This topic describes precautions when using little endian area for following items:• C compiler• Assembler• Linker• Debugger

213

Appendix

D.1 C Compiler (fcc911)

Note that operation of MB91403 is not guaranteed if the following operations are performed on the little endian area in programming in C language:• Placing a variable with initial value• Structure assignment• Operations other than character arrangement using a character string

manipulation function• Specification of -K lib option when a character string manipulation function

is used• Use of double type or long double type• Placing a stack in a little endian area

Placing a Variable with Initial Value A variable with initial value cannot be stored in the little endian area. The complier does not

have a feature to generate an initial value for the little endian area. It can place a variable in

the little endian area but cannot set the initial value. Set the initial value at the top of the

program.

[Example] When setting the initial value to the variable little__data in the little endianarea

extern int little__data;

void little__init(void)

little__data = Initial value;

void main(void)

little__init();

...

214


Structure AssignmentWhen assigning structures, the compiler transfers data by byte, half-word, or word, by select-

ing the optimal transfer method from among them. Therefore, an assignment between the

structure variable allocated to the ordinary area and that to the little endian area leads incorrect

result. In such a case, assign the members of the structure respectively.

[Example] When assigning a structure to the structure variable little__st in the littleendian area

struct tag char c; int i; normal__st;

extern struct tag little__st;

#define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i;

void main(void)

STRMOVE(little__st,normal__st);

Because the structure member assignment differs for each compiler, it might be different from

one that has been compiled using another compiler. In this case, the correct result cannot be

obtained even using the method mentioned above. Do not assign the structure variable in the

little endian area if the structure member assignment doesn’t match.

Operations Other than Character Arrangement Using a Character String Manipulation Function

The character string manipulation function that are available as a standard library processes

data in unit of byte. For this reason, if you manipulate data in areas having types other than

char,unsigned char,and signed char types that are assined to the little endian area, incorrect

result will be obtained. Do not perform such processing.

[Example of trouble] Transfer of word data using memcpy

int big = 0x01020304; /* big endian area */

extern int little; /* little endian area */

memcpy(&little,&big,4); /* Transfer using memcpy */

If you run the above program, the following will result.

This transfer of word data results in an error as shown.

(Big endian area) (Little endian area)

01 02 03 04 → memcpy → 01 02 03 04

(Correct result) 04 03 02 01

215

Appendix

Specification of -K lib option when a character string manipulation function is used

If -K lib option is specified, the compiler performs inline expansion on some of the character

string manipulation functions. At this stage, the process may be changed to manipulate by

half-word or word because the optimal method is selected. For this reason, the process on the

little endian area cannot be performed properly. Do not specify the -K lib option when per-

forming a process by using a character string manipulation function on the little endian area.

Similarly, do not specify the -O 4 option or -K speed option that include the -K lib option in

this case.

Use of double type or long double typeThe double type and long double type variables are accessed by using an upper one word and

lower one word, respectively. Thus, incorrect result will be obtained by accessing to the dou-

ble type and long double type variables stored in the little endian area. While you can assign

variables of the same type within the little endian area, assignment of variables may be

replaced with that of constants as a result of optimization. Do not place the double type and

long double type variables in the little endian area.

[Example of trouble] Transfer of double type data

double big = 1.0; /* Big endian area */

extern int little; /* Little endian area */

little = big; /* Transfer of double type data */

If you run the above program, the following will result.

This transmission of double type data results in an error as shown.

Placing a Stack in a Little Endian AreaOperation is not guaranteed if a part or the whole of the stack is stored in the little endian area.

(Big endian area) (Little endian area)

3f f0 00 00 00 00 00 00 → 00 00 f0 3f 00 00 00 00

(Correct result) 00 00 00 00 00 00 f0 3f

216


D.2 Assembler (fasm911)

The followings are notes relating to the little endian area on programming in FR assembler language.

SectionThe little endian area is designed to exchange data mainly with CPUs employing little endian

system. Define the little endian area as a data section having no initial values. Access opera-

tion in MB91101 cannot be guaranteed if the code, stack, or the data section having initial

values is specified for the little endian area.

[Example]

/* Correct section definition for the little endian area */

.SECTION Little__Area, DATA, ALIGN=4

Little__Word:

.RES.W 1

Little__Half:

.RES.H 1

Little__Byte:

.RES.B 1

217

Appendix

Data AccessWhen accessing data in the little endian area, the data values can be encoded transparently irre-

spective of which endian system is used. However, be sure to access data in the little endian

area using the same size as that of the target data size.

[Example]

LDI #0x01020304, r0

LDI #Little__Word, r1

LDI #0x0102, r2

LDI #Little__Half, r3

LDI #0x01, r4

LDI #Little__Byte, r5

/* 32-bit data is accessed using ST instruction (or LD instruc-

tion or the like). */

ST r0, @r1

/* 16-bit data is accessed using STH instruction (or LDH

instruction or the like). */

STH r2, @r3

/* 8-bit data is accessed using STB instruction (or LDB

instruction or the like). */

STB r4, @r5

When the data is accessed using this macro with a different size from that of the data, the

resulting value cannot be guaranteed. For example, if two consecutive 16-bit data are accessed

at a time using a 32-bit access instruction, the resulting value cannot be guaranteed.

218


D.3 Linker (flnk911)

The followings are notes on developing a program that uses a little endian area when allocating sections for linking.

Limitations on Section TypeOnly data sections without initial values can be allocated in the little endian area. If a data sec-

tion, stack section or code section that has the initial value is stored in the little endian area,

behavior of the program cannot be guaranteed because the arithmetic processing such as

address resolution is performed within the linker using a big endian system.

No Detection of ErrorsSince the linker does not recognize the little endian area, allocating sections in a way that vio-

lates the above limitation will not cause error messages. When using a linker, be sure to

thoroughly review the contents of the sections allocated in the little endian area.

219

Appendix

D.4 Debugger (sim911, em1911, mon911) Simulator Debugger

There is no memory space specification command that indicates the little endian area. Thus,

memory operation commands and instruction executions to operate a memory are handled as

big endian.

Emulator Debugger, Monitor DebuggerNote that the data cannot be handled as normal values if data in the little endian area are

accessed using the following commands:

• set memory / show memory / enter / examine / set watch command

→ If floating point (single/double) data are handled, the specified values cannot be set or

displayed.

• search memory command

→ If halfword or word data are searched, the search cannot be performed using the

specified values.

• Line/reverse assemble (including reverse-assemble display of the source window)

→ Normal instruction codes cannot be set or displayed.

(Do not store instruction codes in the little endian area.)

• call/show call command

→ If the stack area is allocated in the little endian area, operation cannot be performed

normally. (Do not allocate stack areas in the little endian area.)

220

Appendix E Instruction List

Appendix EInstruction List

The instruction list of FR family is shown below.

[Legend of instruction list]

(1) Indicates the instruction name.

Instructions marked with * (asterisk) are not included in CPU specifications. These are

extended instruction codes added/extended at assembly language levels.

(2) Addressing mode specified as operands are listed in symbols.

For meanings of respective symbols, refer to "Addressing Mode Symbols (next topic)".

(3) Instruction formats.

(4) Hexadecimal expressions of instructions.

(5) The number of machine cycles needed for execution.

a: Memory access cycle. It has possibility of delay by Ready function.

b: Memory access cycle. It has possibility of delay by Ready function.

If an object register in an LD operation is referenced by an immediately following

instruction, the interlock function is activated, increasing the number of cycles for

execution by + 1.

c: If an immediately following instruction operates to an object of R15, SSP or USP in

read/write mode, or if the instruction belongs to instruction format A group, the

interlock function is activated, increasing the number of cycles for execution by 1 to

make the total number of 2 cycles.

d: If an immediately following instruction refers to MDH/MDL, the interlock function is

activated, increasing the number of cycles for execution cycle by 1 to make the total of

2 cycles.

If special purpose registers (TBR, RP, USP, MDH, MDL) are accessed using ST Rs,

@R15 instruction, the interlock function is always activated, increasing the number of

cycles for execution by 1 to make the total of 2 cycles.

For a, b, c, and d, minimum execution cycle is 1.

Mnemonic Type OP CYC NZVC Operation Remarks

ADD Rj, Rj A AG 1 CCCC Ri + Rj -> Rj

*ADD #s5, Rj C A4 1 CCCC Ri + s5 -> Rj

, , , , , ,

, , , , , ,

↓ ↓ (1) (2)

↓(3)

↓(4)

↓(5)

↓(6)

↓(7)

221

Appendix

(6) Indicates flag changes.

(7) Operation carried out by instruction.

Addressing Mode Symbols Ri : Register direct (R0 to R15, AC, FP, SP)

Rj : Register direct (R0 to R15, AC, FP, SP)

R13 : Register direct (R13, AC)

Ps : Register direct (program status register)

Rs : Register direct (TBR, RP, SSP, USP, MDH, MDL)

Cri : Register direct (CR0 to CR15)

CRj : Register direct (CR0 to CR15)

#i8 : Unsigned 8-bit immediate (-128 to 255) Note: The values from -128 to -1 are interpreted as 128 to 255.

#i20 : Unsigned 20-bit immediate (-0X80000 to 0XFFFFF) Note: -0X7FFFF to -1 are interpreted as 0X7FFFF to 0XFFFFF.

#i32 : Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: 0X80000000 to -1 are interpreted as 0X80000000 to 0XFFFFFFFF.

#s5 : Signed 5-bit immediate (-16 to 15)

#s10 : Signed 10-bit immediate (-512 to 508, multiple of 4 only)

#u4 : Unsigned 4-bit immediate (0 to 15)



#u10 : Unsigned 10-bit immediate (0 to 1020, multiples of 4 only)

@dir8 : Unsigned 8-bit direct address (0 to 0XFF)

@dir9 : Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)

@dir10 : Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)

label9 : Signed 9-bit branch address (-0X100 to 0XFC, multiple of 2 only)

label12 : Signed 12-bit branch address (-0X800 to 0X7FC, multiple of 2 only)

label20 : Signed 20-bit branch address (-0X80000 to 0X7FFFF)

label32 : Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF)

@Ri : Register indirect (R0 to R15, AC, FP, SP)

@Rj : Register indirect (R0 to R15, AC, FP, SP)

@(R13,Rj) : Register relative indirect (Rj: R0 to R15, AC, FP, SP)

@(R14,disp10) : Register relative indirect (disp10: -0X200 to 0X1FC, multiple of 4 only)

@(R14,disp9) : Register relative indirect (disp9: -0X100 to 0XFE, multiple of 2 only)

@(R14,disp8) : Register relative indirect (disp8: -0X80 to 0X7F)

@(R15,udisp6) : Register relative indirect (udisp6: 0 to 60, multiple of 4 only)

@Ri+ : Register indirect with post-increment (R0 to R15, AC, FP, SP)

@R13+ : Register indirect with post-increment (R13, AC)

C ... Changes- ... Does not change 0 ... Clear1 ... Set

N ... Negative flagZ ... Zero flag V ... Over flag C ... Carry flag

Flag change Flag meanings

222


@SP+ : Stack-pop

@-SP : Stack-push

(reglist) : Register list

Instruction Format

Type Instruction format

A

B

C

Cí

D

E

F

MSB LSB

16bit

OP Rj Ri

8 4 4

OP i8/o8 Ri

4 8 4

OP u4/m4 Ri

8 4 4

Only for the ADD, ADDN, CMP, LSL, LSR, and ASR

OP s5/u5 Ri

7 5 4

OP u8/rel8/dir/reglist

8 8

OP SUB-OP Ri

8 4 4

OP rel11

5 11

223

Appendix

Add/subtract Operation Instructions

Comparison operation Instructions

Logical Operation Instructions

Mnemonic Type OP CYCLE NZVC Operation Remarks

ADD Rj, Ri *ADD #s5, Ri

ADD #u4, Ri ADD2 #u4, Ri

A C’

C C

A6 A4

A4A5

11

11

CCCCCCCC

CCCCCCCC

Ri + Rj -> RiRi + s5 -> Ri

Ri + extu(i4) -> Ri Ri + extu(i4) -> Ri

In assembler format, a high order 1 bit is interpreted as a sign. Zero-extension Minus extension

ADDN Rj, Ri A A7 1 CCCC Ri + Rj + c -> Ri Add operation with carry

ADDN Rj, Ri*ADDN #s5, Ri

ADDN #u4, Ri ADDN2 #u4, Ri

A C’

C C

A2 A0

A0 A1

11

11

--------

--------

Ri + Rj -> RiRi + s5 -> Ri

Ri + extu(i4) -> Ri Ri + extu(i4) -> Ri


SUB Rj, Ri A AC 1 CCCC Ri - Rj -> Ri

SUBC Rj, Ri A AD 1 CCCC Ri - Rj - c -> Ri Subtract operation with carry

SUBN Rj, Ri A AE 1 ---- Ri - Rj -> Ri


CMP Rj, Ri *CMP #s5, Ri

CMP #u4, Ri CMP2 #u4, Ri

A C’

C C

AA A8

A8 A9

11

11

CCCCCCCC

CCCCCCCC

Ri - Rj Ri - s5

Ri - extu(i4) Ri - extu(i4)



AND Rj, Ri AND Rj, @RiANDH Rj, @RiANDB Rj, @Ri

A A A A

82848586

11 + 2a 1 + 2a 1 + 2a

CC-- CC-- CC-- CC--

Ri & = Rj(Ri) & = Rj(Ri) & = Rj(Ri) & = Rj

WordWordHalfwordByte

OR Rj, RiOR Rj, @RiORH Rj, @RiORB Rj, @Ri

A A A A

92949596

11 + 2a 1 + 2a 1 + 2a

CC-- CC-- CC-- CC--

Ri |= Rj(Ri) |= Rj(Ri) |= Rj(Ri) |= Rj


EOR Rj, RiEOR Rj, @RiEORH Rj, @RiEORB Rj, @Ri

A A A A

9A9C9D9E

11 + 2a 1 + 2a 1 + 2a

CC-- CC-- CC-- CC--

Ri ^= Rj(Ri) ^= Rj(Ri) ^= Rj(Ri) ^= Rj


224


Bit Manipulation Instruction

Note 1: Assembler generates BANDL if result of operation "u8&0x0F" leaves an active bit and

generates BANDH if "u8&0xF0" leaves an active bit. Both BANDL and BANDH may

be generated.

Note 2: Assembler generates BORL if result of operation "u8&0x0F" leaves an active bit and

generates BORH if "u8&0xF0" leaves an active bit. Both BORL and BORH may be

generated.

Note 3: Assembler generates BEORL if result of operation "u8&0x0F" leaves an active bit and

generates BEORH if "u8&0xF0" leaves an active bit. Both BEORL and BEORH may

be generated.

Multiply/divide Operation Instructions


BANDL #u4, @RiBANDH #u4, @Ri*BAND #u8, @RiNote 1 :

C C

8081

1 + 2a 1 + 2a

------------

(Ri)& = (0xF0 + u4)(Ri)& = ((u4<<4) + 0x0F)(Ri)& = u8

Manipulate lower 4 bits Manipulate higher 4 bits

BORL #u4, @RiBORH #u4, @Ri*BOR #u8, @RiNote 2 :

C C

9091

1 + 2a 1 + 2a

------------

(Ri) ⎪ = u4(Ri) ⎪ = (u4<<4)(Ri) ⎪ = u8


BEORL #u4, @RiBEORH #u4, @Ri*BEOR #u8, @RiNote 3 :

C C

9899

1 + 2a 1 + 2a

------------

(Ri) ^ = u4(Ri) ^ = (u4<<4)(Ri) ^ = u8


BTSTL #u4, @RiBTSTH #u4, @Ri

C C

8889

2 + a 2 + a

0C--CC--

(Ri) & u4(Ri) & (u4<<4)

Test lower 4 bits Test higher 4 bits


MUL Rj, Ri MULU Rj, RiMULH Rj, RiMULUH Rj, Ri

A A A A

AF AB BF BB

5533

CCC-CCC-CC-- CC--

Ri * Rj -> MDH,MDLRi * Rj -> MDH,MDLRi * Rj -> MDLRi * Rj -> MDL

32 bit * 32 bit = 64 bit Without sign 16 bit * 16 bit = 32 bit Without sign

DIV0S RiDIV0U RiDIV1 RiDIV2 RiDIV3 DIV4S*DIV RiNote 1: *DIVU RiNote 2:

E E E E E E

97-497-597-697-7

9F - 69F - 7

11d 111

36

--------

-C-C-C-C--------

-C-C

-C-C

MDL / Ri -> MDL , MDL % Ri -> MDH

MDL / Ri -> MDL , MDL % Ri -> MDH

Step calculation 32 bit/32 bit = 32 bit

225

Appendix

Shift Arithmetic Instructions

Immediate Value Set/16-bit/32-bit Immediate Value Transfer Instruction

Note 1: Generates DIV0S,DIV1 × 32, DIV2, DIV3, and DIV4S. The length of the instruction

code will be 72 bytes.

Note 2: Generates DIV0U, and DIV1 × 32. The length of the instruction code will be 66

bytes.

Note 3: If an immediate value is given in absolute, assembler automatically makes i8, i20, or

i32 selection.

If an immediate value contains relative value or external reference symbol, assembler

selects i32.


LSL Rj, Ri*LSL #u5, Ri(u5:0 to 31) LSL #u4, RiLSL2 #u4, Ri

A C’C C

B6 B4 B4 B5

1111

CC-CCC-CCC-CCC-C

Ri << Rj -> RiRi << u5 -> RiRi << u4 -> RiRi <<(u4 + 16) -> Ri

Logical shift operation

LSR Rj, Ri*LSR #u5, Ri(u5:0 to 31)LSR #u4, RiLSR2 #u4, Ri

A C’C C

B2 B0 B0 B1

1111

CC-CCC-CCC-CCC-C

Ri >> Rj -> RiRi >> u5 -> RiRi >> u4 -> RiRi >>(u4+16) -> Ri

Logical shift operation

ASR Rj, Ri*ASR #u5, Ri (u5:0 to 31)ASR #u4, RiASR2 #u4, Ri

A C’C C

BAB8 B8 B9

1111

CC-CCC-CCC-CCC-C

Ri >> Rj -> RiRi >> u5 -> RiRi >> u4 -> RiRi >>(u4+16) -> Ri

Arithmetic shift operation


LDI:32 #i32, RiLDI:20 #i20, RiLDI:8 #i8, Ri*LDI # i8|i20|i32,RiNote 3:

E C B

9F - 89BC0

321

------------

i32 -> Rii20 -> Rii8 -> Rii8 ⎪ i20 ⎪ i32 -> Ri

Higher 12 bits are zero-extendedHigher 24 bits are zero-extended

226


Memory Load Instructions

* Assembler calculates the values to set for the fields of o8 and o4 in the hardware specifica-

tions as follows:

disp10/4->o8, disp9/2->o8, disp8->o8, where disp10,disp9,and disp8 are with sign and

udisp6/4->o4 udisp6 is without sign.

Memory Store Instructions

* Assembler calculates the values to set for the fields of o8 and o4 in the hardware specifica-

tions as follows:

disp10/4->o8, disp9/2->o8, disp8->o8, where disp10, disp9, and disp8 are with sign and

udisp6/4->o4 udisp6 is without sign.

Transfer Instructions Between Registers

Note : Special-purpose register Rs : TBR, RP, USP, SSP, MDH, MDL


LD @Rj, RiLD @(R13,Rj), RiLD @(R14,disp10), RiLD @(R15,udisp6), RiLD @R15+, RiLD @R15+, RsLD @R15+, PS

A A B C E E E

04002003

07-007-807-9

bbbbbb

1 + a + b

------------------------

CCCC

(Rj) -> Ri(R13 + Rj) -> Ri(R14 + disp10) -> Ri(R15 + udisp6) -> Ri(R15) -> Ri, R15+ = 4 (R15) -> Rs, R15+ = 4(R15) -> PS, R15+ = 4

Rs: Special-purpose register Note :

LDUH @Rj, RiLDUH @(R13,Rj), RiLDUH @(R14,disp9), Ri

A A B

050140

bbb

------------

(Rj) -> Ri(R13 + Rj) -> Ri(R14 + disp9) -> Ri

Zero-extension Zero-extension Zero-extension

LDUB @Rj, RiLDUB @(R13,Rj), RiLDUB @(R14,disp8), Ri

A A B

060260

bbb

------------

(Rj) -> Ri(R13 + Rj) -> Ri(R14 + disp8) -> Ri

Zero-extension Zero-extension Zero-extension


ST Ri, @RjST Ri, @(R13,Rj)ST Ri, @(R14,disp10)ST Ri, @(R15,udisp6)ST Ri, @-R15ST Rs, @-R15ST PS, @-R15

A A B C E E E

14103013

17-017-817-9

aaaaaaa

----------------------------

Ri -> (Rj)Ri -> (R13 + Rj)Ri -> (R14 + disp10)Ri -> (R15 + udisp6)R15 - = 4, Ri -> (R15)R15 - = 4, Rs -> (R15)R15 - = 4, Ps -> (R15)

WordWordWord

Rs: Special-purpose register Note :

STH Ri, @RjSTH Ri, @(R13,Rj)STH Ri, @(R14,disp9)

A A B

151150

aaa

------------

Ri -> (Rj)Ri -> (R13 + Rj)Ri -> (R14 + disp9)

HalfwordHalfwordHalfword

STB Ri, @RjSTB Ri, @(R13,Rj)STB Ri, @(R14,disp8)

A A B

161270

aaa

------------

Ri -> (Rj)Ri -> (R13 + Rj)Ri -> (R14 + disp8)

ByteByteByte


MOV Rj, RiMOV Rs, RiMOV Ri, RsMOV PS, RiMOV Ri, PS

A A E E E

8BB7 B3

17-107-1

1111c

----------------

CCCC

Rj -> RiRs -> RiRi -> RsPS -> RiRi -> PS

Transfer between general-purpose registers Rs: Special-purpose registerRs: Special-purpose register Note :

227

Appendix

Normal Branch Instructions (no-delay)

Note : "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed

for non-branch.

Note : Assembler calculates the values to set for the fields of rel11 and rel8 in the hardware

specifications as follows:

(label12 - PC - 2)/2 -> rel11, (label9 - PC - 2)/2 -> rel8, where label12 and label9 are

with signs.

Note : RETI instruction must be executed while S flag is "0".


JMP @Ri E 97-0 2 ---- Ri -> PC

CALL label12CALL @Ri

E F

D097-1

22

--------

PC + 2-> RP ,PC + 2 + (label12 - PC - 2) -> PCPC + 2 -> RP ,Ri -> PC

RET E 97-2 2 ---- RP -> PC Return

INT #u8

INTE

D

E

1F

9F - 3

3 + 3a

3 + 3a

----

----

SSP - = 4, PS -> (SSP), SSP - = 4, PC + 2 -> (SSP),0-> I flag, 0 -> S flag(TBR + 0x3FC - u8 × 4) -> PCSSP - = 4, PS -> (SSP), SSP - = 4, PC + 2 -> (SSP),0-> S flag,(TBR + 0x3D8) -> PC

For emulator

RETI E 97-3 2 + 2A CCCC (R15) -> PC, R15 - = 4, (R15) -> PS, R15 - = 4

BRA label9BNO label9BEQ label9

BNE label9BC label9BNC label9BN label9BP label9BV label9BNV label9BLT label9BGE label9BLE label9BGT label9BLS label9BHI label9

DDD

DDDDDDDDDDDD

D

E0E1E2

E3E4E5E6E7E8E9EAEBECEDEEEF

21

2/1

2/12/12/12/12/12/12/12/12/12/12/12/12/1

------------

----------------------------------------------------

PC + 2 + (label9 - PC - 2) -> PCNon-branchif(Z == 1) thenPC + 2 + (label9 - PC - 2) -> PC↑ s/Z == 0↑ s/C == 1↑ s/C == 0↑ s/N == 1↑ s/N == 0↑ s/V == 1↑ s/V == 0↑ s/V xor N == 1↑ s/V xor N == 0↑ s/(V xor N) or Z == 1↑ s/(V xor N) or Z == 0↑ s/C or Z == 1↑ s/C or Z == 0

228


Branch Instruction with Delays

Note: Assembler calculates the values to set for the fields of rel11 and rel8 in the hardware

specifications as follows:

(label12 - PC - 2)/2 -> rel11, (label9 - PC - 2)/2 -> rel8, where label12 and label9 are

with signs.

Note: • Delayed branch operation always executes next instruction (delay slot) before mak-

ing a branch.

• Instructions allowed to be stored in the delay slot must be all the instructions

described "1" in the cycle column, and instructions described "a", "b", "c", or "d"

in the cycle column.

Instructions of multiple cycles cannot be stored in the delay slot.


JMP:D @Ri E 9F - 0 1 ---- Ri -> PC

CALL:D label12CALL:D @Ri

FED8

9F - 111

--------

PC + 4-> RP ,PC + 2 + (label12 - PC - 2) -> PCPC + 4 -> RP ,Ri -> PC

RET:D E 9F - 2 1 ---- RP -> PC Return

BRA:D label9BNO:D label9BEQ:D label9

BNE:D label9BC:D label9BNC:D label9BN:D label9BP:D label9BV:D label9BNV:D label9BLT:D label9BGE:D label9BLE:D label9BGT:D label9BLS:D label9BHI:D label9

DDD

DDDDDDDDDDDDD

F0 F1 F2

F3 F4 F5 F6 F7 F8 F9 FAFBFCFDFEFF

111

1111111111111

------------

----------------------------------------------------

PC + 2 + (label9 - PC - 2) -> PCNon-branchif(Z == 1) thenPC + 2 + (label9 - PC - 2) -> PC↑ s/Z == 0↑ s/C == 1↑ s/C == 0↑ s/N == 1↑ s/N == 0↑ s/V == 1↑ s/V == 0↑ s/V xor N == 1↑ s/V xor N == 0↑ s/(V xor N) or Z == 1↑ s/(V xor N) or Z == 0↑ s/C or Z == 1↑ s/C or Z == 0

229

Appendix

Other Instructions

Note : • The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is

"a*(n - 1) + b + 1",

where "n" is the number of registers specified.

• The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is

"a*n + 1",

where "n" is the number of registers specified.

Note 1 : Assembler calculates s10/4 to obtain s8 to set s10. s10 has a sign.

Note 2 : If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8

to R15 is specified in reglist, assembler generates LDM1. Both LDM0 and LDM1 may

be generated.

Note 3 : If either of R0 to R7 is specified in reglist, assembler generates STM0.

If either of R8 to R15 is specified in reglist, assembler generates STM1. Both STM1

and STM0 may be generated.

Note 4 : Assembler calculates u10/4 to obtain u8 to set u10. u10 has no sign.


NOP E 9F - A 1 ---- No changes

ANDCCR #u8ORCCR #u8

DD8393

cc

cccccccc

CCR and u8 -> CCRCCR or u8 -> CCR

STILM #u8 D 87 1 ---- i8 -> ILM Set ILM immediate value

ADDSP #s10 Note 1:

D A3 1 ---- R15 + = s10 ADD SP instruction

EXTSB RiEXTUB RiEXTSH RiEXTUH Ri

E E E E

97-897-9

97 - A97 - B

1111

----------------

Sign extension 8 -> 32 bitsZero extension 8 -> 32 bitsSign extension 16 -> 32 bitsZero extension 16 -> 32 bits

LDM0 (reglist)

LDM1 (reglist)

*LDM (reglist)

Note 2:

D

D

8C

8D

----

----

----

(R15) -> reglist,R15 increment(R15) -> reglist,R15 increment(R15) -> reglist,R15 increment

Load-multi R0 to R7

Load-multi R8 to R15

Load-multi R0 to R15

STM0 (reglist)

STM1 (reglist)

*STM (reglist)

Note 3:

D

D

8E

8F

----

----

----

R15 decrement,reglist -> (R15)R15 decrement,reglist -> (R15)R15 decrement,reglist -> (R15)

Store-multi R0 to R7



ENTER #u10

Note 4 :

D 0F 1 + a ----R14 -> (R15 - 4),R15 - 4 -> R14,R15 - u10 -> R15

Entrance processing of function

LEAVE E 9F - 9 b ----R14 +4 -> R15,(R15 - 4) -> R14,

Exit processing of function

XCHB @Rj, Ri A 8A 2a ----Ri -> TEMP(Rj) -> RiTEMP -> (Rj)

For semaphore managementByte data

230


20-bit Normal Macro Branch Instructions

[Ref. 1] CALL20

1) If label20 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows:

CALL label12

2) If label20 - PC - 2 is outside of the range given in 1) or includes external reference sym-

bol, instruction is generated as follows:

LDI:20 #label20,Ri

CALL @Ri

[Ref. 2] BRA20

1) If label20 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows:

BRA label9



Å@ LDI:20 #label20,Ri

JMP @Ri

[Ref. 3] Bcc20


Bcc label9



Bxcc false xcc is a revolt condition of cc

LDI:20 #label20,Ri

JMP @Ri

false:

Mnemonic Operation Remarks

*CALL20 label20,RiNext instruction address -> RP, label20 -> PC

Ri: Temporary register (refer to "Ref. 1")

*BRA20 label20,Ri*BEQ20 label20,Ri*BNE20 label20,Ri*BC20 label20,Ri*BNE20 label20,Ri*BN20 label20,Ri*BP20 label20,Ri*BV20 label20,Ri*BNV20 label20,Ri*BLT20 label20,Ri*BGE20 label20,Ri*BLE20 label20,Ri*BGT20 label20,Ri*BLS20 label20,Ri*BHI20 label20,Ri

label20 -> PCif(Z == 1) then label20 -> PC↑ s/Z == 0↑ s/C == 1↑ s/C == 0↑ s/N == 1↑ s/N == 0↑ s/V == 1↑ s/V == 0↑ s/V xor N == 1↑ s/V xor N == 0↑ s/(V xor N) or Z == 1↑ s/(V xor N) or Z == 0↑ s/C or Z == 1↑ s/C or Z == 0

Ri: Temporary register (refer to "Ref. 2") Ri: Temporary register (refer to "Ref. 3") ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑

231

Appendix

20-bit Delayed Macro Branch Instructions

[Ref. 1] CALL20:D


CALL:D label12



LDI:20 #label20,Ri

CALL:D @Ri

[Ref. 2] BRA20:D


BRA:D label9



LDI:20 #label20,Ri

JMP:D @Ri

[Ref. 3] Bcc20:D


Bcc:D label9




LDI:20 #label20,Ri

JMP:D @Ri

false:


*CALL20:D label20,RiNext instruction address + 2 -> RP, label20 -> PC


*BRA20:D label20,Ri*BEQ20:D label20,Ri*BNE20:D label20,Ri*BC20:D label20,Ri*BNC20:D label20,Ri*BN20:D label20,Ri*BP20:D label20,Ri*BV20:D label20,Ri*BNV20:D label20,Ri*BLT20:D label20,Ri*BGE20:D label20,Ri*BLE20:D label20,Ri*BGT20:D label20,Ri*BLS20:D label20,Ri*BHI20:D label20,Ri



232


32-bit Normal Macro Branch Instructions

[Ref. 1] CALL32


CALL label12



LDI:32 #label32,Ri

CALL @Ri

[Ref. 2] BRA32


BRA label9



LDI:32 #label32,Ri

JMP @Ri

[Ref. 3] Bcc32


Bcc label9




LDI:32 #label32,Ri

JMP @Ri

false:


*CALL32 label32,RiNext instruction address -> RP, label32 -> PC


*BRA32 label32,Ri*BEQ32 label32,Ri*BNE32 label32,Ri*BC32 label32,Ri*BNC32 label32,Ri*BN32 label32,Ri*BP32 label32,Ri*BV32 label32,Ri*BNV32 label32,Ri*BLT32 label32,Ri*BGE32 label32,Ri*BLE32 label32,Ri*BGT32 label32,Ri*BLS32 label32,Ri*BHI32 label32,Ri



233

Appendix

32-bit Delayed Macro Branch Instructions

[Ref. 1] CALL32:D

(1) If label32 - PC - 2 is between -0x800 and +0x7fe, instruction is generated as follows:

CALL:D label12

(2) If label32 - PC - 2 is outside of the range given in 1) or includes external reference sym-


LDI:32 #label32,Ri

CALL:D @Ri

[Ref. 2] BRA32:D

(1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows:

BRA:D label9



LDI:32 #label32,Ri

JMP:D @Ri

[Ref. 3] Bcc32:D

(1) If label32 - PC - 2 is between -0x100 and +0xfe, instruction is generated as follows:

Bcc:D label9




LDI:32 #label32,Ri

JMP:D @Ri

false:


*CALL32D label32,RiNext instruction address + 2 -> RP, label32 -> PC


*BRA32:D label32,Ri*BEQ32:D label32,Ri*BNE32:D label32,Ri*BC32:D label32,Ri*BNC32:D label32,Ri*BN32:D label32,Ri*BP32:D label32,Ri*BV32:D label32,Ri*BNV32:D label32,Ri*BLT32:D label32,Ri*BGE32:D label32,Ri*BLE32:D label32,Ri*BGT32:D label32,Ri*BLS32:D label32,Ri*BHI32:D label32,Ri



234


Direct Addressing Instructions

Note : Assembler calculates the values to set for the fields of dir8, dir9, and dir10 as follows:

dir8 -> dir, dir9/2 -> dir, dir10/4 -> dir dir8, dir9, and dir10 has no signs.


DMOV @dir10, R13DMOV R13, @dir10DMOV @dir10, @R13+DMOV @R13+, @dir10DMOV @dir10, @-R15DMOV @R15+, @dir10

DDDDDD

08180C1C0B1B

ba

2a2a2a2a

------------------------

(dir10) -> R13R13 ->(dir10)(dir10) -> (R13),R13 + = 4(R13) -> (dir10),R13 + = 4R15 - = 4, (R15) -> (dir10)(R15) -> (dir10),R15 + = 4

WordWordWordWordWordWord

DMOVH @dir9, R13DMOVH R13, @dir9DMOVH @dir9, @R13+DMOVH @R13+, @dir9

DDDD

09190D1D

ba

2a2a

----------------

(dir9) -> R13R13 -> (dir9)(dir9) -> (R13),R13 + = 2(R13) -> (dir9),R13 + = 2

HalfwordHalfwordHalfwordHalfword

DMOVB @dir8, R13DMOVB R13, @dir8DMOVB @dir8, @R13+DMOVB @R13+, @dir8

DDDD

0A1A0E1E

ba

2a2a

----------------

(dir8) -> R13R13 -> (dir8)(dir8) -> (R13),R13 + +(R13) -> (dir8),R13 + +

ByteByteByteByte

235

Appendix

Appendix FElectrical Characteristics

F.1 Absolute Maximum Ratings

*1 Maximum output current is a peak current value measured at a corresponding pin.

*2 Average output current is an average current for a 100 ms period at a corresponding pin.

*3 Average total output current is an average current for a 100 ms period for all correspond-

ing pins.

<Caution>

1. Semiconductor devices can be permanently damaged by application of stress inexcess of absolute maximum rating. In normal operation, it is recommended to usesemiconductor devices under the recommended operation conditions. If they are usedunder the environment beyond these conditions, reliability of LSIs may be degraded.

2. Voltages for VDDE pins must be the same.

3. Make sure to fix the voltage of all the VSS pins at 0 V.

4. Change N.C. to OPEN.

Parameter SymbolValue

Unit RemarksM IN M A X

Power supply voltage VDDE VSS - 0.3 VSS + 4.0 V

Input voltage VI VSS - 0.3 VDDE + 0.3 V

Output voltage VO VSS - 0.3 VDDE + 0.3 V

"L" level maximum output current IOL - T.B.D mA *1

"L" level average output current IOLAV - T.B.D mA *2

"L" level total maximum output current ∑IOL - T.B.D mA

"L" level total average output current ∑IOLAV - T.B.D mA *3

"H" level maximum output current IOH - T.B.D mA *1

"H" level average output current IOHAV - T.B.D mA *2

"H" level total maximum output current ∑IOH - T.B.D mA

"H" level total average output current ∑IOHAV - T.B.D mA *3

Power consumption PD - T.B.D mW

Operating temperature Ta -10 70 °C

Storage temperature Tstg -55 150 °C

236

Appendix F Electrical Characteristics

F.2 Recommended Operating Conditions

F.3 DC Characteristics


UnitM IN TYP M A X

Power supply voltage VDDE 3.0 3.3 3.6 V

Operating temperature Ta -10 70.0 °C


UnitM IN TYP M A X

"H" level input voltage VIH 2.0 VDDE + 0.3 V

"L" level input voltage VIL VSS - 0.3 0.8 V

"H" level output voltage VOHVDDE = 3.0 V, IOH = 4.0 mA

VDDE - 0.5 - V

"L" level output voltage VOLVDDE = 3.0 V, IOH = 4.0 mA

- 0.4 V

Input leak current ILIVDDE = 3.6 V, VSS<VI<VDDE

- - ±5 µA

Pull-up resistance RPULUPB[21:0]/PA[3:0]

10 33 80 kΩ

Pull-down resistance RPULDBREAK/ICD[3:0]

10 33 80 kΩ

Power supply current input capacitance

ICC VDDEVDDE = 3.3 V fc = 33 MHz

- - 150.0 mA

CINExcept power supply

- 18 - pF

237

Appendix

F.4 AC CharacteristicsThe following conditions apply to measurement items based on the power supply voltage

unless otherwise specified.

AC Measurement Conditions

Load Conditions

VCCVIH

VIL0V

Input VCCVOH

0V

Output

VOL

VIH VDDEX 0.8 VOH VDDE/2

VIL VDDEX 0.2 VOL VDDE/2

C = 50pF

238


F.5 Clock Timings

* 1 : The frequency must be set to a value exceeding 25 MHz when communicating with 100

Base devices in Ethernet MAC IF.

*2 : Frequency regulation stands for the maximum deviation ratio of the operating clock from

the center frequency in the clock multiplication system.

Parameter Symbol Pin name ConditionValue

Unit RemarksM IN M A X

Input clock frequencyFclkcyc X0 External clock 12.5 33.0 MHz T.B.D *1

Fclkcyc X0,X1 OSC oscillation 12.5 33.0 MHz T.B.D *1

Frequency regulation f - 5.0 %

Internal operating clock frequency (FR70E/perifheral module)

Fclkin - - 66/33 MHz T.B.D *1

External memory clock frequency

- MCLKO - 33.0 MHz T.B.D *1

| α |f0

f0Center frequency∆f = x 100 (%)

++ α

- α

X0,X1

Fclkcyc

239

Appendix

F.6 Reset

* tcp is an operation clock cycle for internal CPU and peripheral modules.


UnitM IN TYP M A X

Reset input time trstl INITXIAfter stabilizing power supply and input clock

tcpx5 - ns

INITXI

trstl, tprstl

240


F.7 MEMORY IF Normal Memory Access

* tcycp is a cycle period for external memory clock.

Parameter Symbol Pin nameReference

timing

ValueUnit Remarks

Min. Max.

Address delay time tchav MEMA[23:0] MCLKO ↑ - tcycp / 2 + 7 ns

CSX delay time tchcsl MEMCSX[2:0] MCLKO ↑ - tcycp / 2 + 7 ns

CSX delay time tchcsh MEMCSX[2:0] MCLKO ↑ - tcycp / 2 + 7 ns

WRX delay time tchwrl MEMWRX[3:0] MCLKO ↑ - 9 ns

WRX delay time tchwrh MEMWRX[3:0] MCLKO ↑ - 9 ns

Data delay time tchdv MEMD[31:0] MCLKO ↑ - tcycp / 2 + 7 ns

RDX delay time tchrdl MEMRDX MCLKO ↑ - 9 ns

RDX delay time tchrdh MEMRDX MCLKO ↑ - 9 ns

Data setup tdsrh MEMD[31:0] MCLKO ↑ 19 - ns

Data hold trhdx MEMD[31:0] MCLKO ↑ -1 - ns

trhdx

D[31:0](IN)

RDXtdsrh

tchrdl tchrdh

tchdvD[31:0](OUT)

WRX[3:0]

CSX[2:0]tchwrl tchwrh

tchcsl tchcsh

tchav

A[23:0]

tcycp

MCLKO

241

Appendix

Ready Input

UART

* timcycp is a operation clock cycle for the built-in peripheral module in FR70EM core.

Parameter Symbol Pin nameReference

timing

ValueUnit Remarks

Min. Max.

RDY setup trdys RDY MCLKO ↑ 19 - ns

RDY hold trdyh RDY MCLKO ↑ - - ns

trdys

trdyh

trdys

trdyh

MEMRDY

MCLKO


Unit RemarksMin. Max.

Serial clockcycle time

tscyc SCK[1:0]

Internal shift clock mode

8xtimcycp - ns

SCLK ↓ ⇒ SOUT delay time tslov SOUT[1:0] -80 80 ns

Valid SIN ⇒ SCLK ↓ tivsh SIN[1:0] 100 - ns

SCLK ↓ ⇒ Valid SIN hold time tshix SIN[1:0] 60 - ns

Serial clock "H" pulse width tshsl SCK[1:0]

External shift clock mode

4xtimcycp - ns

Serial clock "L" pulse width tslsh SCK[1:0] 4xtimcycp - ns

SCLK ↓ ⇒ SOUT delay time tslov SOUT[1:0] - 150 ns

Valid SIN ⇒ SCLK ↓ tivsh SIN[1:0] 60 - ns

SCLK ↓ ⇒ Valid SIN hold time tshix SIN[1:0] 60 - ns

242


Internal Shift Clock Mode

External shift clock mode

VOL

tshix

tslov

tivsh

tscyc

SIN

VOL VOH

SOUT

SCK

tsish tshsl

tshix

SIN

tivsh

tslov

SOUT

SCK

243

Appendix

F.8 Ethernet Mac Controller MII Interface

Send Timing

Parameter Symbol Pin name Reference timingValue


TXEN delay time tdel_txen TXEN TXCLK ↑ - 15 ns

TXD delay time tdel_txd TXD[3:0] TXCLK ↑ - 15 ns

RXDV setup time tsu_rxdv RXDV RXCLK ↑ 2 - ns

RXDV hold time thd_rxdv RXDV RXCLK ↑ 3 - ns

RXD setup time tsu_rxd RXD[3:0] RXCLK ↑ 2 - ns

RXD hold time thd_rxdv RXD[3:0] RXCLK ↑ 3 - ns

RXER setup time tsu_rxer RXER RXCLK ↑ 2 - ns

RXER hold time thd_rxer RXER RXCLK ↑ 3 - ns

5 5

Tdel_txd

x

TX_CLK

TX_EN

TXD[3:0]

Tdel_txen

xn

Tdel_txd

TX_CLK

TX_EN

TXD[3:0]

Tdel_txen

n-1

244


Receive Timing

0 5 5

Thd_rxdv

Tsu_rxdv Thd_rxd

Tsu_rxd

RX_CLK

RX_DV

RXD[3:0]

Thd_rxd

Tsu_rxd

Thd_rxdvTsu_rxdv

n

RX_DV

RXD[3:0] 0n-1

RX_CLK

Tsu_rxer

RX_CLK

RX_ER

Thd_rxer

Thd_rxer

Tsu_rxer

245

Appendix

MDIO Interface

Parameter SymbolPin

nameReference

timing

ValueUnit Remarks

Min. Max.

MDIO setup time tsu_mdio MDIO MDCLK ↑ 10 - ns

MDIO hold time thd_mdio MDIO MDCLK ↑ 0 - ns

MDIO delay time tdel_mdio MDIO MDCLK ↑ 10 30 ns

MDIO switch time (IN → OUT) tdel_turnon MDIO MDCLK ↑ 10 30 ns

MDIO switch time (OUT → IN) tdel_turnoff MDIO MDCLK ↑ 10 30 ns

Thd_mdio

Tsu_mdio

Tdel_mdioTdel_mdio

Tdel_turnon

MDC

MDIO(INPUT)

MDC

MDIO(OUTPUT -> INPUT)

MDC

MDIO(OUTPUT)

MDC

MDIO(INPUT -> OUTPUT)

Tsu_mdio

Thd_mdio

Tdel_turnoff

Input Mode

Input Mode Output Mode

Output Mode

246


F.9 External IF Read Access


Parameter Symbol Pin nameValue


EXReadCycletime texrc EXA,EXCSX 6xtcp - ns

EXAtoDataValid texadv EXA,EXD 5xtcp - ns

EXCSXtoDataValid texcsdv EXCSX,EXD 5xtcp - ns

EXRDXtoDataOutEnable texdoe EXRDX,EXD 5xtcp - ns

EXRDX"H"toHighZ texdhz EXRDX,EXD - 5xtcp + 8 ns

texadv

texcsdv

texrc

texdhz

texdoe

EXD[15:0]

EXWEX

EXA

EXCSX

EXRDX

247

Appendix

Write Access




EX Write Cycle time texwc EXA,EXCSX 5xtcp - ns

EXA to Data Set up time texads EXA,EXD 4xtcp - ns

EXCSX to Data Set up time texcsds EXCSX,EXD 4xtcp - ns

EXWRX"L" Pulse width texwp EXWRX,EXD 4xtcp - ns

EXD Setup time texds EXWRX,EXD 15 - ns

EXD Hold time texdh EXWRX,EXD 0 - ns

texcsds

texwp

texds

texwc

texads

EXA

EXCSX

EXWRX

EXD[15:0]

EXRDX

tchdv

texdh

248


F.10 I2C IF Input Timing Specifications

*1) I2C bus rating.

Output Timing Specifications

*2) Refer to "I2C IF Specifications : 4.2.3. Clock Control Register (CCR)" for the value of m.



SDA input setup time ts2sdai SDA 250 - ns *1)

SDA input hold time th2sdai SDA 0 - ns *1)

SCL input cycle time tcscli SCL 10 - µs *1)

SCL input "H" pulse width twhscli SCL 4 - µs *1)

SCL input "L" pulse width twlscli SCL 4.7 - µs *1)

SCL input setup time ts2scli SCL 4 - µs *1)

SCL input hold time th2scli SCL 4.7 - µs *1)

STOP START RESTART

th2scli ts2sdai th2sclith2sdaits2scli ts2scli

tsccli twhscli twlscli

SDA (input)

SCL (input)

ACKD3 D2 D1 D0D7 D6 D5 D4

Parameter SymbolPin

name

ValueUnit

Remarks

Min. Max.

SCL output cycle time tcsclo SCL (2xm) + 2 - PCLK *2)

SCL output "H" pulse width twhsclo SCL m + 2 - PCLK *2)

SCL output "L" pulse width twlsclo SCL m - PCLK *2)

SCL output setup time ts2sclo SCL m + 2 - PCLK *2)

SCL output hold time th2sclo SCL mx2 - PCLK *2)

SDA output hold time th2sdao SDA 5 - PCLK *2)

STOP START RESTART

th2sclo th2sclo

twlsclo

ts2scloth2sdao

tcsclo twhsclo

ACK

SCL (output)

ts2sclo

D1 D0SCL (output) D7 D6 D5 D4 D3 D2

249

Appendix

F.11 SDRAM IF

Note: Control output pins: SRASX, SCASX, WEX



Output delay tsddo D[31:0], SRASX, SCASX, WEX - 5 ns

Output hold tsdho D[31:0], SRASX, SCASX, WEX 0 - ns

Input setup tsdsi D[31:0], SRASX, SCASX, WEX 3 - ns

Input hold tsdhi D[31:0], SRASX, SCASX, WEX 3 - ns

MCLKO

Read data

Control outputWrite data

tsddo

tsdsi

tsdhi

tsdho

250

CM71-10131-1

FUJITSU SEMICONDUCTOR DEVICES - CONTROLLER MANUAL

MB91403 SERIES HARDWARE MANUAL

First Edition: April 2005

Published by: FUJITSU LIMITED ELECTRONIC DEVICE GROUP

Edited by: MARKETING DIVISION, SALES PROMOTION DEPARTMENT

FUJITSU Confidential

9

CHAPTER 2 OVERVIEW

2.1 DescriptionThe FR family is a series of microcontrollers based on a 32-bit high-performance RISC CPU, suitable for avariety of applications such as image process equipment requiring high-speed operations of massiveamounts of data, servo systems requiring single-chip, high-speed process, and portable informationterminals requiring a low operating voltage and low power consumption. Compared with FR70 core family,FR71E core family can perform operation at higher speed because of the review of the internal structure. Furthermore, except the external pin, the activate cause, and the debug support unit for DMAch3, com-pletely operation interchangeability is available.

2.2 Line-UpAccording to the operation frequency, size, and built-in memory capacity, there are many line-ups for FR71E core. For the partiuclar information of each core, refer to "FR71E Core Series Line-up Manual”.

2.3 FeaturesFR CPU Core

• Operating frequency: 33 MHz• 32-bit RISC, load/store architecture with a five-stage pipeline• 16-bit fixed-length instructions (basic instructions): 1 instruction per cycle• Memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for

embedded controllers• Function entrance/exit instructions, register content multi-load/store instructions: Instructions appli-

cable to high-level languages• Register interlock function: Facilitating coding in assemblers• On-chip multiplier supported at the instruction level

Signed 32-bit multiplication: 5 cyclesSigned 16-bit multiplication: 3 cycles

• Interrupt (saving PC and PS): 6 cycles, 16 priority levels• Harvard architecture allow program access and data access to be executed simultaneously• Vast memory space of 4 gigabytes can be linearly accessed• Instructions compatible with the FR family

Bus Interface

• Capable of up to 32-bit address output. 8-/16-/32-bit data output supported.• Capable of chip-select signal output for 8 completely independent area• Basic bus cycles: 2 cycles• Mechanism of generating various wait cycles for individual areas• External wait cycle by RDY input• Prefetch function• Burst access function• SDRAM, FCRAM control functions


10

Internal Data RAM• 2KB~ memory capacity integrated

The capacity of internal data RAM is different according to individual cores. Refer to “FR71E Core Series Line-up Manual”.

• 1 cycle for read/write access at high speed

Instruction Cache

• 4 kilobytes integrated

• Two-way set associative

• 4 words (16 bytes) per set

• Variable capacity (4/2/1 KB)

• Lock function enabling programs to be resident

• Available as instruction RAM of 1 cycle when not used as an instruction cache.

DMAC (DMA Controller)

• 5 channels (including 4 channels for external-to-external transfer)

• 3 types of transfer source (external pins/internal peripherals/software)

• Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed)

• Transfer mode (Demand transfer/burst transfer/step transfer/block transfer)

• Fly-by transfer supported (between external I/O and memory)

• Transferred data size is selectable from 8, 16, and 32 bits

Bit Search Module (Using REALOS)• Searching the first 1/0 inverted bit position from the MSB in each word

Reload Timer (including one channel for REALOS)• 16-bit timer: 3 channels

• Internal clock frequency: Selectable from divide-by-2/8/32 frequencies

• Event counter pin input/gate functions provided

• Square wave output

UART• Full-duplex double buffer

• 2 channels

• Parity enabled or disabled selectable

• Asynchronous or CLK synchronous communication selectable

• LSB/MSB first selectable

• Internal timer for dedicated baud rate

• Capable of using an external clock as the transfer clock

• Wealth of error detection features (parity, frame, overrun)

Interrupt Controller• A total of 9 external interrupt lines (1 nonmaskable interrupt pin and 8 normal interrupt pins)

• Interrupt from peripheral resource

• Priority levels are programmable except nonmaskable interrupt (16 levels)

• Capable of using the normal interrupt and nonmaskable interrupt pins for Wake Up in STOP mode


11

Debug Support Unit

• DSU4 is embedded and used as debug support unit.

Other Features• Clock input of divided by 2 or without division can be selected as the clock source.

• INITX (reset for initializing the settings) and RSTX (reset for initializing the operation) available as reset pins. Watchdog timer reset, software reset, hardware standby, and undervoltage detection standby pins are also available.

• Stop and sleep modes supported as low-power consumption modes

• Clock frequency division feature

• Internal timebase-timer

• Supply voltage: 1.8 V 0.15 V

• Maximum operating frequency: CPU and internal buses = 108 MHz~, External buses = 66 MHz, Internal resources = 54 MHzThe maximum operating frequency is different according to individual cores. Refer to “FR71E Core Series Line-up Manual”.

• Current consumption: 120 mA at 108 MHz (Typical)The current consumption is different according to individual cores. Refer to “FR71E Core Series Line-up Manual”.

±


12

2.4 Block Diagram

E

B

T

I2C Bus

PORT

External IF/PORT

MB91403

8/16bit bus

Code/attestation macro

DES/3DES/AES

HMAC-MD5/SHA1

DH

ROM256KByte

Crystal oscillator/Internal clo

RAM64KByte

MU

X

GPIO

External IF

10/100 EthernetMAC Controller

L2/L3/L4 Filtering

I-Cache(4KB)

DMACR

Serial IF(2ch)

DSU IFINT(2ch)

D-RAM(8KB)

OSC

DSUFR CORE

I2C IF

CLKCont

PLL

UART

INT

Timer

PHY

ROM/FLASH

SRAM/SDRAM


33

CHAPTER 4 CPU and Control Units

4.1 Internal ArchitectureThe FR71 CPU is a high performance core based on the RISC architecture, and incorporating a set of advanced instruction for embedded controller applications.

4.1.1 Features• RISC architecture

Basic instructions: 1 instruction per cycle

• 32-bit architecture32-bit general-purpose register x 16

• 4 gigabytes of linear memory space

• On-chip multiplier

32-bit x 32-bit multiplication: 5 cycles16-bit x 16-bit multiplication: 3 cycles

• Enhanced interrupt services

Quick response (6 cycles)

Multiple-interrupt supportLevel mask function (16 levels)

• Enhanced I/O instructions

Memory-memory transfer instructionBit manipulation instruction

• High coding efficiencyBasic instruction word length: 16 bits

• Low power consumptionSleep mode and stop mode supported

• Clock frequency divide ratio setting function

• Instruction compatible with the FR family


34

4.1.2 Internal ArchitectureThe FR71 CPU uses the Harvard architecture that the instruction and data buses are separated. The instruction bus (I-bus) is connected to the on chip instruction cache. The 32-bit-16-bit bus converter is connected to the F-bus to provide the interface between the CPU and peripheral resources. The Harvard-Princeton bus converter is connected to both of the I-bus and D-bus to provide the interface between the CPU and the bus controller.

FR71 CPU

D bus I bus

DataRAM

32bit

16bitbus converter

Instructioncache

Harvard

Princetonbus

converter

32

32

32

I data

I addressD address

D data

DataAddress

bus controllerPeripherals resource

R-bus 16

32 3232

3232

Fbus


35

4.1.3 Memory SpaceThe FR71 family has 4 gigabytes of logical addresses (232 address) which can be linearly accessed by the CPU.

Direct addressing area: The following areas in the address space is used for input/output.This area is called the direct addressing area, which allows an instruction to directly specify the address of the operand.The direct addressing area varies as shown below depending on the size of access data:

=> Byte data access:0-0FF H=> Halfword data access:0-1FF H=> Word data access:0-3FF H

4.1.3.1 Memory MapThe memory space of the macro consists of the following areas.

The capacity of D-bus RAM and address range is different according to individual core. Refer to “FR71E Core Series Line-up Manual”.

0000 0000H

0000 0400H

0001 0000H

0002 0000H

0004 2000H or 0004 1800H

0004 0000H

FFFF FFFFH

I/O

I/O

I-bus RAM 4KB (and its mirror)

Access prohibited

D-bus RAM 8kByte

or

D-bus RAM 2kByte

External area

Direct addressing area

See the I/O Map.

Access prohibited

0005 0000H


36

4.1.4 CPUThe CPU is a compact implementation of a 32-bit RISC based FR71 architecture.

The CPU uses a five-stage instruction pipeline to execute one instruction in one cycle. The pipeline consists of the following stages:

- Instruction fetch (IF): Outputs the instruction address to fetch the instruction.- Instruction decode (ID): Decodes the fetched instruction while reading a register.- Execution (EX): Executes the operation.- Memory access (MA): Access memory for loading or storing.- Write back (WB): Writes the operation result (or loaded memory data) to the register.

Figure 4.1.3 Instruction Pipeline

Instructions are not executed out of order. That is, if instruction A enters the pipeline ahead of instruction B, instruction A always reaches the writeback stage before instruction B.In principle, instructions are executed at a rate of one instruction per cycle. Note, however, a load/store instruction involving a memory wait state, a branch instruction without delay slot, or a multi-cycle instruction requires more than one cycle for execution. Also, a delay in supplying an instruction slows down the execution speed of the instruction.

4.1.5 Instruction CacheThe on chip instruction cache can construct a high performance system without generating the costs of external high-speed memory and a related control logic circuit. Instructions can be supplied to the CPU at high speed even if the external bus speed is slow. See section 4.2 for the details of instruction cache.

4.1.6 32-Bit-16-Bit Bus ConverterThis bus converter provides the interface between the 32-bit F-bus for fast access and the 16-bit R-bus, enabling data access from the CPU to built-in peripheral resources.When the CPU performs a 32-bit access, this bus converter converts it to two 16-bit accesses to the R-bus. Some of the built-in peripheral resources have an access width restriction.

CLK

Instruction 1 WB

Instruction 2 MA WB

Instruction 3 EX MA WB

Instruction 4 ID EX MA WB

Instruction 5 IF ID EX MA WB

Instruction 6 IF ID EX MA WB


37

4.1.7 Harvard-Princeton Bus ConverterThis bus converter delivers consistency between CPU instruction access and data access to provide a smooth interface to the external bus.The CPU has the Harvard architecture that the instruction and data buses are separated. In contrast, the bus controller for controlling the external bus has the Princeton architecture with a single bus. This bus converter assigns priorities to CPU instruction and data accesses to control access to the bus controller. This optimizes the order of accesses to the external bus.

4.1.8 Instruction OverviewThe FR71 supports a set of general RISC instructions and the logical operation, bit manipulation, and direct addressing instructions optimized for embedded applications. The entire instruction set is listed in APPENDIX. Individual instructions are 16 bits length (some instructions are 32 or 48 bits length), allowing memory to be used efficiently.

The instruction set is divided into the following function groups:- Arithmetic operation- Load and store- Branch- Logical operation and bit manipulation- Direct addressing- Miscellaneous

4.1.8.1 Arithmetic OperationThis group of instructions includes typical arithmetic operation instructions (add, subtract, compare) and shift instructions (logical shift, arithmetic operation shift). The add and subtract instructions can also serve for the carry producing operation used for a multiword operation and the operation with fixed flag value used for address calculation.

This group also includes 32x32-bit and 16x16-bit multiply instructions and a 32÷32-bit step divide instruction.Immediate-value transfer instruction which sets an immediate value to a register and the register-to-register transfer instruction are also included.All of the arithmetic operation instructions perform operations using the general-purpose and multiplication/division registers in the CPU.

4.1.8.2 Load and StoreThe load and store instructions read from and write to external memory. They are also used to read from and write to on-chip peripheral (I/O) resources.The load and store instructions support three different access lengths: byte, halfword, and word. Also, they support general register-indirect memory addressing and some of them support register-indirect memory addressing with displacement and register-indirect memory addressing with register increment/decrement.

4.1.8.3 BranchThis group of instructions serves for branching, calling, interrupting, and returning, Some of the branch instructions have a delay slot and the others do not, allowing optimization for specific applications. The branch instructions are detailed later in Section 4.6 "Branch Instructions".


38

4.1.8.4 Logical Operation and Bit ManipulationThe logical operation instructions can perform a logical operation of AND, OR, or EOR between general-purpose registers or between a general-purpose register and memory (and I/O resource). The bit manipulation instructions can directly manipulate the values of memory (and I/O resource). This group of instructions support general register-indirect memory addressing.

4.1.8.5 Direct AddressingThe direct addressing instructions are used for access between an I/O resource and a general-purpose register or I/O between memory. This group of instructions enables fast and efficient access by directly specifing the I/O address in the instruction instead of indirect a register. Some of these instructions supports register-indirect memory addressing with register increment/decrement.

4.1.8.6 MiscellaneousThis group of instructions includes flag setting, stack manipulation, sign/zero extension in PS register. It also includes the function entrance/exit and register multi-load/store instructions applicable to high-level languages.


39

4.2 Instruction Cache

4.2.1 OverviewThe instruction cache is a fast local memory for temporary storage. Once an instruction code is accessed from external low speed memory, the instruction cache holds the instruction code inside to increase the speed of accessing the same code from the second time.Setting the RAM mode, the instruction cache data RAM and tag RAM are directly read/write-accessible by software.

4.2.1.1 Configuration

- FR basic instruction length: Two bytes- Block layout: Two-way set associative- Blocks 128 blocks per way

16 bytes per block (= 4 sub-blocks)4 bytes per sub-block (= 1 bus access unit)

Figure I-CACHE-1 Instruction Cache Configuration

4bytes 4bytes 4bytes 4bytes 4bytes

Way 1 I3 I2 I1 I0

Cache tag Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 0

128 blocks .

.

.

.

.

.


Way 2


128 blocks .

.

.

.

.

.



40

Figure I-CACHE-2 Instruction Cache Tags

Bits 31-9: Address tagThis area stores the upper 23 bits of the memory address of the instruction that is cached in the corresponding block.For example, memory address IA of the instruction data that is stored in sub-block k in block i is obtained from the following equation:

IA = address tag x 2 11 + i x 2 4 + k x 2 2

The address tag is used to check for a match with the instruction address requested for access by the CPU. The CPU operates as follows depending on the result of the tag check:1) When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU

within the cycle.2) When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the

data loaded by external access at the same time.

bits 7-4: Sub-block validationWhen SBV* = "1", the corresponding sub-block holds the current instruction data at the address located by the tag. Each sub-block usually holds two instructions (except immediate-value transfer instructions).

Bit 3: Tag validation bitThis bit indicates whether the address tag value is valid. When the bit = "0", the corresponding block is invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.)

Way 131 09 08

Address tag

07 06 05 04 03 02 01 00

< -------------------------------- ---------- >

LRU

31 09 08

07 06 05 04 03 02 01 00

< -------------------------------- ---------- >

Empty

ETLKLRUEmptyTAGVSBV0SBV1SBV3 SBV2

--

---

Tag validation

Tag validation

Sub-block validation

Entry lock

Sub-block validation

Entry lock

Way2

Empty

Empty

Empty ETLK

Address tag

TAGVSBV0SBV1SBV2SBV3


41

Bit 1: LRU (only in way 1)

This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1 is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.

Bit 0: Entry lockThis bit is used to lock all the entries in the block corresponding to the tag in the cache. When ETLK = "1", the entries are locked and are not updated when a cache miss occurs. However, invalid sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, external memory is accessed after losing one cycle used for evaluating the cache miss.


42

4.2.1.2 Control Registers

Register list

[Bits 1, 0] SIZE1, SIZE0These bits set the cache capacity. The combination of the settings determines the cache size, IRAM size, and the address map in RAM mode as shown in Figure I-CACHE-3. When the cache size is changed, be sure to flush the cache and release the entry lock before turning on the cache.

Cache Size Register

The ICHCR (I-Cache Control Register) controls the operation of the instruction cache.Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three following cycles.

[Bit 7] RAM: RAM mode

Setting this bit to "1" causes the cache to operate as RAM mode. By placing the cache in RAM mode, the cache RAM is mapped as shown in Figure I-CACHE-3, when the cache is enabled with setting the ENAB bit to "1".

[Bit 5] GBLK: Global lock

This bit locks all of the current entries in the cache. Setting the GBLK bit to "1" prevents the valid entries in the cache from being updated when a cache miss occurs. However, invalid sub-blocks are updated. Instruction data fetch operation in the global lock state is performed as not being locked.

[Bit 4] ALFL: Auto-lock fail

Locking an already locked entry, the ALFL bit is set to "1". This prevents a new entry from being locked in the cache against the user's intention when the update of an entry in the entry auto-lock state is performed to an already locked entry. This bit is referenced for program debugging purposes. Writing "0" clears this bit.

[Bit 3] EOLK: Entry auto-lock

This bit enables or disables auto-locking for each entry in the instruction cache. An entry accessed (but resulting in a miss) at the EOLK bit = "1", is locked when the entry lock bit in the cache tag is set to "1" by hardware. Once locked, the entry is not updated at any cache miss. However, invalid sub-blocks are updated. To ensure the entry lock, set this bit after flushing.

ISIZE (8bit) 7 6 5 4 3 2 1 0 Initial value

00000307 H - - - - - - SIZE1 SIZE0 ------10 B

- - - - - - R/W R/W

SIZE1 SIZE0 Capacity

0 0 1KB

0 1 2KB

1 0 4 KB (Initial value)

1 1 Setting prohibited

ICHCR (8bit) 7 6 5 4 3 2 1 0 Initial value

000003E7 H RAM - GBLK ALFL EOLK ELKR FLSH ENAB 0-000000 B

R/W - R/W R/W R/W R/W R/W R/W


43

[Bit 2] ELKR: Entry lock release

This bit specifies the clearing of the entry lock bits in all cache tags. When the ELKR bit is set to "1", the entry lock bits in all cache tags are cleared to "0" in the next cycle. Note that the content of this bit is retained for only one clock cycle; it is cleared to "0" in the following clock cycle.

[Bit 1] FLSH: Flush

This bit specifies the flushing of the instruction cache. Setting the FLSH bit to "1" flushes the cache. Note that the value of this bit is stored for only one clock cycle; it is cleared to "0" in the following clock cycle.

[Bit 0] ENAB: Enable

This bit enables or disables the instruction cache. Setting the ENAB bit to "0" disables the cache, the instruction accesses from CPU are directly performed to external memory without cache intervention. When this bit is disabled, the cache retains its values.


44

Figure I-CACHE-3 RAM Address Map

Cache off Cache off

Address RAM off RAM on RAM off RAM on RAM off RAM on RAM off RAM on

00010000 TAG TAG TAG TAG(way1)

00010200 (way1) (way1) (way1) [TAG way1]

00010400 [TAG way1] [TAG way1]

00010600 [TAG way1]

00010800 [TAG way1] [TAG way1] [TAG way1] [TAG way1]

... ... ... ... ...

[TAG way1]

00014000 TAG TAG TAG TAG(way2)

00014200 (way2) (way2) (way2) [TAG way2]

00014400 [TAG way2] [TAG way2]

00014600 [TAG way2]

00014800 [TAG way2] [TAG way2] [TAG way2] [TAG way2]

... ... ... ...

[TAG way2]

00018000 IRAM $RAM(IRAM) $RAM $RAM $RAM(way1)

00018200 (way1) (way1) (way1) (way1) IRAM IRAM

00018400 IRAM IRAM (way1) (way1)

00018600 (way1) (way1)

00018800 [IRAM way1] [$RAM way1] [$RAM way1] [IRAM way1] [ $/I way1 ] [IRAM way] [ $/I way1 ]

... ... ... ... ... ... ... ...

0001C000 IRAM $RAM(IRAM) $RAM $RAM - $RAM(way2)

0001C200 (way2) (way2) (way2) (way2) IRAM IRAM

0001C400 IRAM IRAM (way2) (way2)

0001C600 (way2) (way2)

0001C800 [IRAM way2] [$RAM way2] [$RAM way2] [IRAM way2] [ $/I way2 ] [IRAM way2] [ $/I way2 ]

... ... ... ... ... ... ... ...

00020000

TAGRAM $RAM

00010000 <- Entry at address 00x 00018000 Instruction at address 000 (SBV0)

00010004 <- Mirror of 00x 00018004 Instruction at address 004 (SBV1)

00010008 00018008 Instruction at address 008 (SBV2)

0001000C 0001800C Instruction at address 00C ( SBV3)

00010010 <- Entry at address 01x 00018010 Instruction at address 000 (SBV0)

00010014 <- Mirror of 01x 00018014 Instruction at address 004 (SBV1)

00010018 00018018 Instruction at address 008 (SBV2)

0001001C 0001801C Instruction at address 00C (SBV3)

00010020 00018020

Cache on 4K Cache on 4K Cache on 2K Cache on 2K Cache on 1K Cache on 1K

*1

*1

*2

Square brackets [ ]: enclose an area for mirroring *1: Map as Cache on according to the value of ISIZE register.*2: Mirror area is generated in the upper 2KB of each 4KB.

*2


45

Figure I-CACHE-4 Memory Allocation by Cache Capacity

Address Cache 4K Cache 2K Cache 1K Cache of f

000 $RAM $RAM $RAM IRAM

200 (WAY1) IRAM

400 IRAM

600

... ... ...

000 $RAM $RAM $RAM IRAM

200 (WAY2) IRAM

400 IRAM

600


46

4.2.2 States in Each Operation Mode

4.2.2.1 Cache States by Operation ModeThe "Disabled" and "Flushed" columns in the following table list the states of the individual bits (areas) changed, for example, by bit manipulation instructions.

Immediately after a reset

Disabled (ENAB=0) Flushed

Cache memory Values undefined

Retains the preceding state.

Cannot be updated while disabled.


Address tag Values undefined




Sub-block validation bits

Values undefined




LRU bit Valuesundefined




Entry lock bit Values undefined



Retains the preceding state (The entry lock must be released).

Tag validation bit Values undefined


Can be flushed while disabled.

All entries are made invalid.

RAM Normal mode Retains the preceding state.

Can be flushed while disabled.


Global lock Unlock Retains the preceding state.

Can be updated while disabled.


Auto-lock fail No fail Retains the preceding state.



Entry auto-lock Unlock Retains the preceding state.



Entry lock release

No release Retains the preceding state.



Enable Disable Disable Retains the preceding state.

Flush Do not flush Retains the preceding state.


Flush in the cycle immediately after memory access.

Returns to "0" after that.

Tag

sC

ontr

ol r

egis

ters


47

4.2.2.2 Updating Entries in the CacheEntries in the cache are updated as summarized below.

4.2.3 Cacheable Areas in the Instruction Cache- The instruction cache can cache data only in external bus space.- Even when the values of external memory are updated by DMA transfer, the instruction cache does not

refresh its values to be coherent with the new values of the memory. In this case, flush the cache to give it coherence.

- Each chip select area can be set as a non-cacheable area. The penalty is one cycle compared to the cache off state. (See Section 5.5 "Setting Chip Select Areas" in Chapter 5 "EXTERNAL INTERFACE".)

4.2.4 Settings for Handling the I-Cache (1) Initializing the cache

To use the I-Cache, the values must be cleared first.Set the FLSH and ELKR bits in the ICHCR register to "1" to erase old data.

ldi #0x000003e7,r0 // Address of I-Cache control register ldi #0B00000110,r1 // FLSH bit (Bit 1) // ELKR bit (Bit 2) stb r1,@r0 // Write to register

Then, the cache is initialized.

(2) Enabling (Turning on) the cacheSet the ENAB bit to "1" to enable the I-Cache.

ldi #0x000003e7,r0 // Address of I-Cache control register ldi #0B00000001,r1 // ENAB bit (Bit 0) stb r1,@r0 // Write to register

Then, the following instructions to be accessed are stored into the cache.The cache can be enabled and initialized at the same time.

ldi #0x000003e7,r0 // Address of I-Cache control register ldi #0B00000111,r1 // ENAB bit (Bit 0)

// FLSH bit (Bit 1)// ELKR bit (Bit 2)

stb r1,@r0 // Write to register

Unlock Lock

Hit Do not update Do not update

Miss Update the values of entries in the cache by loading data from memory.

Do not update at a tag miss.

Update when sub-blocks are invalid.


48

(3) Disabling (Turning off) the cache

Set the ENAB bit to "0" to disable the I-Cache.

ldi #0x000003e7,r0 // Address of I-Cache control register ldi #0B00000000,r1 // ENAB bit (Bit 0) stb r1,@r0 // Write to register

The cache in this state (same as the state immediately after a reset) does nothing as if it was nonexistent.If a process involves significant overhead introduced by the cache, disabling the cache may improve process performance.

(4) Locking all of the values in the cacheLocks the I-Cache to prevent any cached instructions from being pushed out.Set the GBLK bit to "1". If the ENAB bit is not set to "1", or the cache is disabled, the instructions locked in the cache become unavailable.


// GBLK bit (Bit 5) stb r1,@r0 // Write to register

(5) Locking specific instructions in the cacheTo lock a group of specific instructions (such as a subroutine), set the EOLK bit to "1" before executing the instructions.The locked instructions are accessed as if they reside in high-speed internal ROM.


// EOLK bit (Bit 3) stb r1,@r0 // Write to register

This locks a group of specific instructions, starting at the instruction that follows the stb instruction, although it depends on the number of memory wait states involved.Set the EOLK bit to "0" immediately after the end of the group of instructions you want to lock.


// EOLK bit (Bit 3) stb r1,@r0 // Write to register

(6) Releasing the lock on the cacheClear the lock information of the instructions locked in step (5) above.

ldi #0x000003e7,r0 // Address of I-Cache control register ldi #0B00000000,r1 // Disable cache stb r1,@r0 // Write to register ldi #0B00000100,r1 // ELKR bit (Bit 2) stb r1,@r0 // Write to register

Only the lock information is cleared, so the unlocked instructions are replaced with new instructions sequentially according to the setting of the LRU bit.


49

4.3 Programming Model

4.3.1 Basic Programming Model

< ----------------------------------------- > (Initial value)

R0 XXXX XXXX H

R1 ...

... ... ...General-purpose registers ... ... ...

R12 ...

R13 A C ...

R14 F P XXXX XXXX H

R15 S P 0000 0000 H

Program counter PC

Program status PS - ILM - SCR CCR

Table base register TBR

Return RP

SSP

User stack pointer USP

MDHMDL

32 bits

System stack pointer

pointer

Multiply & Divide registers


50

4.3.2 Registers

General-purpose registers32 bits

< ----------------------------------------- > (Initial value)

Registers R0 to R15 are general-purpose registers, and used as accumulators and memory access pointers for various operations.

For these 16 registers, the registers listed below are intended for special applications and some instructions are enhanced.

R13: Virtual accumulatorR14: Frame pointerR15: Stack pointer

The initial values of R0 to R14 after a reset are undefined. The initial value of R15 is 00000000H (SSP value).

R0 XXXX XXXX H

R1 ...

... ... ...

... ... ...

R12 ...

R13 A C ...

R14 F P XXXX XXXX H

R15 S P 0000 0000 H


51

PS (Program Status) register

This register holds the program status. It is divided into three parts (registers): ILM, SCR, and CCR.The undefined bits in the following illustration are all reserved bits. Reading any of these bits always returns "0".

[Bit 5] Stack flag

This flag specifies the stack pointer to be used as R15.

This bit is cleared to "0" at a reset.Set the bit to "0" for execution of the RETI instruction.

[Bit 4] Interrupt enable flag

This flag controls enable/disable user interrupt requests.

This bit is cleared to "0" at a reset.

Value Description

0 SSP is used as R15.The bit is set to "0" automatically when an EIT occurs.(Note that the value saved to the stack is the existing one before the bit is cleared.)

1 USP is used as R15.

Value Description

0 Disables user interrupts.

The bit is cleared to "0" upon execution of the INT instruction.

(Note that the value saved to the stack is the existing one before the bit is cleared.)

1 Enables user interrupts.

Masking user interrupt requests is controlled by the value stored in the ILM register.

Bit position-> 31 20 16 10 8 7 0

< ---------- > < ----- >< ------------------- >ILM SCR CCR

CCR (Condition Code Register)

- - S I N Z V C --00XXXXB

7 6 5 4 3 2 1 0 [Initial value]


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[Bit 3] Negative flag

This flag indicates the sign of the operation result regarded as an integer represented in two's complement.

The initial state after a reset is undefined.

[Bit 2] Zero flag

This flag indicates whether the operation result is 0.


[Bit 1] Overflow flag

This flag indicates whether the operation using an operand regarded as an integer represented in two's complement has resulted in an overflow.


[Bit 0] Carry flag

This flag indicates whether an operation has generated a carry or borrow from the MSB.


Value Description

0 Indicates the operation result as a positive value.

1 Indicates the operation result as a negative value.

Value Description

0 Indicates that the operation result is a value other than 0.

1 Indicates that the operation result is 0.

Value Description

0 Indicates that the operation has resulted in no overflow.

1 Indicates that the operation has resulted in an overflow.

Value Description

0 Indicates that the operation has generated neither a carry nor borrow.

1 Indicates that the operation has generated a carry or borrow.


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SCR (System Condition code Register)

10 9 8 [Initial value]

[Bits 10, 9] Step division flag

This flag stores intermediate data during execution of step division.Do not update the value of this flag during the division process.To execute another process during step division process, save and return the values in the PS register so that the step division can be resumed correctly.


The flag is set by executing the DIVOS instruction to reference the dividend and divisor.The flag is forced to be cleared by executing the DIVOU instruction.

[Bit 8] Step trace trap flag

This flag enables or disables step trace traps.

This bit is cleared to "0" at a reset.The step trace trap function is used by the emulator. When it is used by the emulator, it cannot be used in the user program.

ILM (Interrupt Level Mask) register

20 19 18 17 16 [Initial value]

The ILM register stores the interrupt level mask value to be used for level masking.

An interrupt request input to the CPU is accepted only when its interrupt level is higher than the level indicated by the ILM register.The level value ranges from 0 (00000 B) for the highest level to 31 (11111 B) for the lowest.

The level value which can be set in the program is limited. When the original value is 16 to 31, the new value which can be set is 16 to 31. If an instruction which sets a value of 0 to 15 is executed, a value of the specified value + 16 is transferred.When the original value is 0 to 15, any value from 0 to 31 can be set.This register is initialized to 15 (01111 B) at a reset.

D1 D0 T XX0 B

Value Description

0 Disables step trace traps.

1 Enables step trace traps.

This disables all user NMIs and user interrupts.

ILM4 ILM3 ILM2 ILM1 ILM0 01111 B


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* Notes of PS register

• The following operation may be performed by the instruction immediately before DIV0U/DIV0S instruction: (a) when user interrupt and NMI are accepted (b)when the step is executed (c) when the data event or the emulator menu is stopped.

(1) D0, DI flags are preceded to update. (2) ELT process routine (user interrupt, NMI, or emulator) is performed.(3) DIV0U/DIV0S instruction is executed after returning from EIT, and D0/D1 flag is updated to the

value which is same as (1).

• If each instruction of ORCCR, STILM, MOV Ri, and PS is executed to enable interrupt when user interrupt and NMI factor are generated, the following operations are perfromed.

(1) PS register is preceded to update. (2) ELT process routine (user interrupt, NMI) is performed.(3) After returned from EIT, PS register is updated to the value which is same as (1).

• Since the PS register is preceded to process by a part of instruction, the break may be performed by interrupt process routine when the debugger is in use, or the display of PS flag may be updated in the following exceptional operations. The process must be correctly performed again after returning from EIT, the operation before and after ELT is performed as the specification described.

1. The following operation may be performed by the instruction immediately before DIV0U/DIV0S instruction: (a) when user interrupt and NMI are accepted (b)when the step is executed (c) when the data event or the emulator menu is stopped.

(1) D0, DI flags are preceded to update. (2) ELT process routine (user interrupt, NMI, or emulator) is performed.(3) DIV0U/DIV0S instruction is executed after returning from EIT, and D0/D1 flag is updated to the

value which is same as (1).

2. If each instruction of ORCCR, STILM, MOV Ri, and PS is executed to enable interrupt when user interrupt and NMI factor are generated, the following operations are performed.

(1) PS register is preceded to update. (2) ELT process routine (user interrupt, NMI) is performed.(3) After returned from EIT, PS register is updated to the value which is same as (1).


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PC (Program Counter)

31 0 [Initial value]

[Bits 31-0]The program counter indicates the address of the instruction being executed in the program sequence.The PC is updated as an instruction is executed, bit 0 is set to "0". Bit 0 may be set to "1" when an odd-numbered address is specified as the branch address.Even in that case, bit 0 is invalid and the instruction must be placed at an address that is a multiple of the number 2.

The initial value after a reset is undefined.

TBR (Table Base Register)


The table base register stores the start address of the vector table which is used for EIT events.

The initial value after a reset is 000FFC00H

RP (Return Pointer)


The return pointer stores the return address of a subroutine.When the CALL instruction is executed, the value in the PC is transferred to the RP.When the RET instruction is executed, the value in the RP is transferred to the PC.The initial value after a reset is undefined.

SSP (System Stack Pointer)


The SSP is a system stack pointer.It is used as R15 when the S-flag = "0".The SSP can be explicitly specified.The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event occurs.The initial value after a reset is 00000000H.

PC XXXXXXXX H

TBR 000FFC00 H

RP XXXXXXXX H

SSP 00000000 H


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USP (User Stack Pointer)


The USP is a user stack pointer.It is used as R15 when the S-flag = "1".The USP can be explicitly specified.The initial value after a reset is undefined.This pointer cannot be used by the RETI instruction.

Multiply & Divide registers

31 0

Multiply & divide result storage registers

These registers are used for multiplication or division. Both of them are 32 bits.The initial value after a reset is undefined.When a multiplication is performed:For a multiplication of 32 bits x 32 bits, the 64 bits result are stored in the multiply & divide result storage registers as follows:

MDH: Upper 32 bitsMDL: Lower 32 bits

The result of a 16x16-bit multiplication is stored as follows: MDH: UndefinedMDL: 32 bits result

When a division is performed:The dividend is stored in the MDL when the calculation is started.When the division is performed by the DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction, the results are stored in the MDL and MDH as follows:

MDH: RemainderMDL: Quotient

USP XXXXXXXX H

MDH

MDL


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4.4 Data Structure

4.4.1 Bit OrderingThe FR71 family uses the little endian method for bit ordering.

4.4.2 Byte OrderingThe FR71 family uses the big endian method for byte ordering.

bit31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0

MSB LSB

10101010 11001100 11111111 00010001

MSB LSBbit31 23 15 7 0

10101010

11001100

11111111

00010001

7 0

Memory

bit

Address n

Address (n + 1)

Address (n + 2)

Address (n + 3)


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4.4.3 Word Alignment

4.4.3.1 Program AccessPrograms for the FR71 family must be located at an address that is a multiple of the number 2. Bit 0 in the PC (program counter) is set to "0" when the PC is updated as an instruction is executed. Bit 0 may be set to "1" when an odd-numbered address is specified as the branch address.Even in that case, bit 0 is invalid and the instruction must be placed at an address that is a multiple of the number 2.

There is no odd-numbered address exception.

4.4.3.2 Data AccessWhen accessing data, the FR71 family forces alignment of the address depending on the access width as follows.

Word access:The address is a multiple of the number 4 (with the two LSBs forced to be 00).Halfword access:The address is a multiple of the number 2 (with the LSB forced to be 0).Byte access:----

When word or halfword data access is performed, some of the bits in the effective address obtained by calculation are forced to be 0. In the addressing mode with @(R13, Ri), for example, the register before addition (e.g., even if the LSB is "1") is used for calculation as it is and the lower bits in the result of addition are masked. The register before calculation is not masked.

Example: LD @(R13,R2),R0

Result of addition 00002225 H

↓ Lower two bits are forced to be masked.Address pin 00002224 H

R13 00002222 H

R2 00000003 H

+)


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4.5 Memory Map

The address space is a 32-bit, linear space.

4.5.1 Direct Addressing AreaEach of the following areas in the address space is used for input/output. By using direct addressing, the area can directly specify the operand address in a instruction.The size of the directly addressable area varies as shown below depending on each data length:

- Byte data (8 bits): 0-0FFH- Halfword data (16 bits): 0-1FFH- Word data (32 bits): 0-3FFH

4.5.2 Vector Table Initial AreaThe area from 000FFC00H to 000FFFFFH is an EIT vector table initial area.The vector table used to process EIT events can be located in an arbitrary area by rewriting the TBR. When the device is initialized by a reset, the vector table is relocated to this initial area.

Byte data

Halfword dataDirect addressing area

Word data

Vector table

0000 0000 H

0000 0100 H

0000 0200 H

0000 0400 H

000F FC00 H

000F FFFF H

FFFF FFFF H

Memory Map

~ ~

~ ~


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4.6 Branch Instructions

4.6.1 OverviewThe FR71 family supports both of branch operations with/without delay slot.

4.6.2 Branch Operation with Delay Slot

4.6.2.1 InstructionsThe instructions listed below perform a branch operation with delay slot:

JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9BC:D label9 BNC:D label9 BN:D label9 BP:D label9BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9

4.6.2.2 Principles of OperationBranching with a delay slot means that the branch operation occurs immediately after executing the instruction placed after the branch instruction (in what is called the delay slot).

As the instruction in the delay slot is executed before the branch operation, the apparent execution speed is one cycle. However, if no useful instruction can be placed in the delay slot, a NOP instruction must be placed instead.

Example:; Instruction listing

ADD R1, R2 ; BRA:D LABEL ; Branch instruction MOV R2, R3 @; Delay slot: Executed before branching ...

LABEL : ST R3, @R4 ; Branch destination

For conditional branch instructions, the instruction in the delay slot is executed no matter the branch condition is satisfied or not.

Although delayed branch instructions appear to reverse the execution order of some instructions, this only applies to the updating of the program counter (PC). Other operations (such as updating or referencing registers) are executed in the order they appear in the program.

How the delay slot works:

(1) The Ri referenced by the JMP:D @Ri or CALL:D @Ri instruction is not affected even when the instruction in the delay slot updates the Ri.

Example: LDI:32 #Label, R0 JMP:D @R0 ; Branch to Label LDI:8 #0, R0 ; No effect on branch address ...


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(2) The RP referenced by the RET:D instruction is not affected even when the instruction in the delay slot updates the RP.

Example: RET:D ; Branch to address indicating by RP that is previously set MOV R8, RP ; No effect on return operation ...

(3) The flag referenced by the Bcc:D rel instruction is not affected by the instruction in the delay slot.

Example ADD #1, R0 ; Update flag BC:D Overflow ; Branch depending on execution result of above instruction ANDCCR #0 ; This flag update is not referenced by above branch instruction ...

(4) When the instruction in the delay slot of the CALL:D instruction references the RP, the content updated by the CALL:D instruction is read.

Example: CALL:D Label ; Update RP and branch MOV RP, R0 ; Transfer RP value resulting from execution of above CALL:D ...

4.6.2.3 Restrictions

(1) Instructions acceptable to a delay slotThe instructions satisfying the following conditions can be executed in the delay slot:- One-cycle instruction- Non-branch instruction- Instruction not affecting the operation even when the execution order is changed

The "one-cycle instruction" means an instruction with "1", "a", "b", "c", or "d" listed in the number of cycles column of the instruction list.

(2) Step trace trapA step trace trap does not occur between the execution of a branch instruction with delay slot and the delay slot.

(3) Interrupt or NMINo interrupt or NMI is accepted between the execution of a branch instruction with delay slot and the delay slot.

(4) Undefined instruction exceptionIf an undefined instruction is put in a delay slot, an undefined instruction exception does not occur. In this case, the undefined instruction operates as the NOP instruction.


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4.6.3 Branch Operation without Delay Slot

4.6.3.1 InstructionsThe instructions listed below perform a branch operation without delay slot:

JMP @Ri CALL label12 CALL @Ri RET BRA label9 BNO label9 BEQ label9 BNE label9BC label9 BNC label9 BN label9 BP label9BV label9 BNV label9 BLT label9 BGE label9BLE label9 BGT label9 BLS label9 BHI label9

4.6.3.2 Principles of OperationBranching without a delay slot means that instructions are always executed in the order they appear in the program. The instruction following the branch instruction is never executed before branching.

Example:; Instruction listing ADD R1, R2 ; BRA LABEL ; Branch instruction (without delay slot) MOV R2, R3 ; Not executed ...LABEL ST R3, @R4 ; Branch destination

The branch instruction without delay slot requires two execution cycles for branch, and one execution cycle for no branch.

Compared to the branch instruction with delay slot with NOP specified, the branch instruction without delay slot can improve instruction coding efficiency because there is no effective instruction acceptable to the delay slot.

Select a branch operation with delay slot when an effective instruction can be put in the delay slot. Otherwise, select an operation without delay slot. This improves both of execution speed and coding efficiency.


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4.7 EIT (Exception/Interrupt/Trap)

4.7.1 OverviewEIT is a generic term for exceptions, interrupts, and traps. When an EIT event occurs during execution of a program, the CPU suspends execution of the program and executes another program.

An exception is an event that occurs in relation to the current context. The CPU resumes the execution of the suspended program from the instruction that caused the exception.An interrupt is an event that occurs independently of the current context. The event is generated by hardware.A trap is also an event that occurs in relation to the current context. Some traps are programmed as system calls. The CPU resumes the execution of the suspended program from the instruction next to the instruction that caused the trap.

4.7.1.1 Features- Multiple-interrupt support- Interrupt level masking function (15 levels available to the user)- Trap instruction (INT)- Emulator trigger EIT (hardware or software)

4.7.2 EIT SourcesEIT sources are as follows:

- Reset- User interrupt (internal resource or external interrupt)- NMI - Delayed interrupt- Undefined instruction exception- Trap instruction (INT)- Trap instruction (INTE)- Step trace trap- Coprocessor absence trap- Coprocessor error trap

4.7.3 Return from EIT- RETI instruction


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4.7.4 Interrupt LevelsInterrupt levels are 0 to 31; they are managed by five bits.

Each interrupt level is assigned as follows.

Table CPU-1 Interrupt Levels

Interrupt levels 16 to 31 can be operated.

Interrupt levels have no effect on the undefined instruction exception, coprocessor absence trap, coprocessor error trap, or INT instruction. Neither they change the ILM value.

4.7.5 I-flagThis flag enables or disables interrupts. It is provided as CCR bit 4 in the PS register.

Level

Binary Decimal

00000 0 (Reserved by the system)

When the original ILM value is 16 to 31, value in this range cannot be set to ILM register by a program.

... ... ...

... ... ...


INTE instruction

00100 4

Step trace trap


... ... ...

... ... ...


01111 15 NMI (for user)

10000 16 Interrupt No user interrupt is allowed during the ILM register setting.

10001 17 Interrupt

... ... ...

... ... ...

11110 30 Interrupt

11111 31 - No interrupt is allowed during the ICR setting.

Value Description

0 Disables interrupts.The flag is cleared to "0" when the INT instruction is executed.(Note that the value saved to the stack is the existing one before the bit is cleared.)

1 Enables interrupts.Masking interrupt request is controlled by the level value stored in the ILM register.


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4.7.6 ILM RegisterThe interrupt level mask (ILM) register is the PS register (bits 20 to 16) that stores an interrupt level mask value.

An interrupt request input to the CPU is accepted only when its interrupt level is higher than the level indicated in the ILM register.The highest level value is 0 (00000 B); the lowest is 31 (11111 B).

The level value which can be set in the program is limited. When the original value is 16 to 31, the new value which can be set is 16 to 31. If an instruction which sets a value of 0 to 15 is executed, a value of the specified value + 16 is transferred.When the original value is 0 to 15, any value from 0 to 31 can be set.

* The STILM instruction is used to set this register.

4.7.7 Interrupt/NMI Level MaskingIf an NMI or interrupt request occurs, the interrupt level of the interrupt source (see Table CPU-1) is compared with the level mask value stored in the ILM register. The request is masked and rejected when the following condition is satisfied:

Interrupt level of the source Level mask value

4.7.8 ICR (Interrupt Control Register)The interrupt control register (ICR) is provided in the interrupt controller to set a level for each interrupt request. This register is prepared for each interrupt request input. The register is mapped in the I/O space and accessed from the CPU through a bus.

4.7.8.1 ICR Bit Configuration

7 6 5 4 3 2 1 0

R R/W R/W R/W R/W [Bit 4] ICR4This bit always = "1".

[Bits 3 to 0] ICR3 to ICR0These are the lower four bits indicating the interrupt level of the corresponding interrupt source. These bits can be read and written.The ICR, consisting of bit 4, can set a value from 16 to 31.

- - - ICR4 ICR3 ICR2 ICR1 ICR0 Initial value---11111

≥


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4.7.8.2 ICR MappingTable CPU-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors

Note: See Section 6.1 "Interrupt Controller" for details.

4.7.9 SSP (System Stack Pointer)bit31 . . . . 0 [Initial value]

The SSP is used as the pointer to the stack used to save and restore data on receiving or returning from an EIT.

The value of the SSP is decremented by 8 by EIT processing and incremented by 8 on returning from the EIT by the RETI instruction.

The initial value after a reset is 00000000H.The SSP serves as the general-purpose register R15 when the S-flag in the CCR (condition code register) is "0".

4.7.10 Interrupt StackThe interrupt stack is the area pointed by the SSP, which the PC and PS values are saved/restored. When an interrupt occurs, the PC value is stored at the address indicated by the SSP and PS value is stored at the address of (SSP + 4).

Example:

Interrupt stack

Interrupt source Interrupt control register Corresponding interrupt vector

Register name

Address Number Address

Hex Dec

IRQ00 ICR00 00000440 H 10 H 16 TBR + 3BC H

IRQ01 ICR01 00000441 H 11 H 17 TBR + 3B8 H

IRQ02 ICR02 00000442 H 12 H 18 TBR + 3B4 H

... ... ... ... ... ...

... ... ... ... ... ...

IRQ45 ICR45 0000046D H 3D H 61 TBR + 308 H

IRQ46 ICR46 0000046E H 3E H 62 TBR + 304 H

IRQ47 ICR47 0000046F H 3F H 63 TBR + 300 H

SSP 00000000 H

[Before interrupt] [After interrupt]

SSP 80000000 H SSP 7FFFFFF8 H

Memory

80000000 H 80000000 H

7FFFFFFC H 7FFFFFFC H PS

7FFFFFF8 H 7FFFFFF8 H PC


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4.7.11 TBR (Table Base Register)

bit31 . . . . 0 [Initial value]

The table base register (TBR) indicates the top address of the EIT vector table.The vector address for each EIT is obtained by adding the offset value determined for the TBR and EIT source.The initial value after a reset is 000FFC00H.

4.7.12 EIT Vector TableThe EIT vector area is one kilobytes long, starting from the address indicated by the TBR.The area size per vector is four bytes and the relationship between vector number and vector address is expressed as follows:

vctadr = TBR + vctofs = TBR + (3FC H - 4 x vct)Where: vctadr: Vector address

vctofs: Vector offsetvct: Vector number

The lower two bits of the addition result are always "00".The area from 000FFC00H to 000FFFFFH is the initial area for the vector table, which is relocated by a reset.Special functions are assigned to some of the vectors. Table CPU-3 shows the vector table on the architecture.

TBR 000FFC00 H


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4.7.13 Multi-EIT ProcessIf two or more EIT sources occur simultaneously, the CPU selects and receives one EIT source, executes the EIT sequence, then detects another EIT source, repeatedly. If there is no more EIT source left to be received, the CPU executes the handler instruction for the EIT source received last.

When two or more EIT sources occur simultaneously, therefore, the execution order of their respective handlers is determined by the following two elements:

1) Reception priority of EIT source2) Masking of other sources

The reception priority of EIT source determines the order of executing the EIT sequence where the PS and PC values are saved, the PC is updated, and other sources are masked (as required). The handlers of EIT sources received earlier are not always executed earlier on a first-in first-out basis.

Table CPU-4 lists the reception priorities of EIT sources.

Table CPU-4 Reception Priorities of EIT Sources and the Masking of Other Sources

Reception priority of EIT source Source Masking level of other sources

1 Reset Discard other sources

2 INTE instruction ILM=4

3 Undefined instruction exception Cancel

4 INT instruction I-flag = 0

5 Coprocessor absence trap

Coprocessor error trap

-

6 User interrupt ILM = Level of received source

7 NMI (for user) ILM=15

8 NMI (for emulator) ILM=4

9 Step trace trap ILM=4


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Considering the mask of other sources after an EIT source is received, the handlers for the simultaneously generated EIT sources are executed in the order shown in Table CPU-5.

Table CPU-5 EIT Handler Execution Order

*1: Other sources are discarded.*2: If an INTE instruction is executed in single-step mode, only a step trace trap of ELT is generated. The

source by INTE is ignored.

Example:

Multi-EIT process

Handler execution order EIT source

1 Reset (*1)

2 Undefined instruction exception

3 Step trace trap (*2)

4 INTE instruction (*2)

5 NMI (for user)

6 INT instruction

7 User interrupt

8 Coprocessor absence trap, Coprocessor error trap

NMI handler

Main routine

INT instruction handler

1) Executed first

2) Executed next

Priority

(High) NMI

(Low) INT instruction

generation

execution


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4.7.14 OperationThe "PC" (program counter) as the source of transfer indicates the address of an instruction where each EIT source has been detected. The "next instruction's address" indicates as follows depending on the EIT-detected instruction: (EIT-detected instruction: Next instruction's address)

- LDI:32: PC value + 6- LDI:20, COPOP, COPLD, COPST, or COPSV: PC value + 4 - Other instructions: PC value + 2

4.7.14.1 User Interrupt/NMI OperationWhen an user interrupt or user NMI request is issued, the acceptance of the request is determined in the following order:

[Determining the acceptance of interrupt request]1) The interrupt levels of requests issued simultaneously are compared and the request of the highest level

(smallest value) is selected.The level of a maskable interrupt is compared with the value stored in the corresponding ICR and the NMI is compared with a predetermined constant.

2) If two or more interrupt requests of the same level are issued, the interrupt request of the smallest interrupt number is selected.

3) The selected interrupt request is masked and rejected if its interrupt level is equal to or greater than the level mask value.When the interrupt level is smaller than the level mask value, proceed to 4).

4) If the selected interrupt request is maskable, the interrupt request is masked and rejected when the I-flag is "0". When the I-flag is "1", proceed to 5).If the selected interrupt request is an NMI, proceed to 5) regardless of the value in the I-flag.

5) When the above conditions are satisfied, the interrupt request is accepted at a break of instruction processing.

If a user interrupt/NMI request is received upon detection of an EIT request, the CPU performs the following steps using the interrupt number corresponding to the accepted interrupt request.

*: ( ) in [Process] below represents the address to be pointed by the register.

[Process]1) SSP-4 --> SSP2) PS --> (SSP)3) SSP-4 --> SSP4) Next instructions address --> (SSP)5) Interrupt level of accepted request --> ILM6) "0" --> S-flag7) (TBR + vector offset of accepted interrupt request) --> PC

The CPU tries to detect a new EIT before executing the first instruction in the handler after the interrupt sequence. If an acceptable EIT has occurred, the CPU enters the EIT processing sequence.


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4.7.14.2 Process of INT InstructionINT #u8This instruction causes a branch to the interrupt handler of the vector indicated by u8.

[Process]1) SSP-4 --> SSP2) PS --> (SSP)3) SSP-4 --> SSP4) PC + 2 --> (SSP)5) "O" --> I-flag6) "O" --> S-flag7) (TBR + 3FCH - 4 x u8) --> PC

4.7.14.3 Process of INTE InstructionINTEThis instruction causes a branch to the interrupt handler of the vector with vector No. #9.

[Process]1) SSP-4 --> SSP2) PS --> (SSP)3) SSP-4 --> SSP4) PC + 2 --> (SSP)5) "00100" --> ILM6) "O" --> S-flag7) (TBR + 3D8H) --> PC

Do not use an INTE instruction in the INTE instruction or step trace trap process routine.The INTE instruction does not generate an EIT during single stepping.

4.7.14.4 Process of Step Trace TrapIf the T-flag in the SCR of the PS register is set to enable the step trace function, a trap occurs at the execution of every instruction, causing a break.

[Step trace trap detection conditions]1) T-flag = 12) The instruction is not a delayed branch instruction.3) During execution of other than an INTE instruction or step trace trap process routine4) If the above conditions are satisfied, a break is inserted between the executions of instructions.

[Process]1) SSP-4 --> SSP2) PS --> (SSP)3) SSP-4 --> SSP4) Next instruction's address --> (SSP)5) "00100" --> ILM6) "O" --> S-flag7) (TBR + 3CCH) --> PC

If the T-flag is set to enable the step trace trap function, user NMIs and user interrupts are disabled.The INTE instruction no longer generates an EIT.The FR71 family generates a trap at the execution of the instruction immediately after setting the T-flag.


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4.7.14.5 Process of Undefined Instruction ExceptionIf an instruction is found undefined during instruction decoding, an undefined instruction exception occurs.

[Undefined instruction exception detection conditions]1) Instruction found undefined during instruction decoding2) Placed outside the delay slot (not immediately after the delayed branch instruction)3) If the above conditions are satisfied, an undefined instruction exception occurs, causing a breaks.

[Process]1) SSP-4 --> SSP2) PS --> (SSP)3) SSP-4 --> SSP4) PC --> (SSP)5) "O" --> S-flag6) (TBR + 3C4H) --> PC

The PC saves the address of the instruction where the undefined instruction exception was detected.

4.7.14.6 Coprocessor Absence TrapA coprocessor absence trap occurs if a coprocessor instruction which attempts to use an absent coprocessor is executed.

[Process]1) SSP-4 --> SSP2) PS --> (SSP)3) SSP-4 --> SSP4) Next instruction's address --> (SSP)5) "O" --> S-flag6) (TBR + 3E0H) --> PC

4.7.14.7 Coprocessor Error TrapA coprocessor error trap occurs if an error occurs when a coprocessor is being used and if a coprocessor instruction which attempts to operate the coprocessor is executed.

[Process]1) SSP-4 --> SSP2) PS --> (SSP)3) SSP-4 --> SSP4) Next instruction's address --> (SSP)5) "O" --> S-flag6) (TBR + 3DCH) --> PC


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4.7.14.8 Process of RETI InstructionThe RETI instruction returns from an EIT process routine.

[Process]1) (R15) --> PC2) R15 + 4 --> R153) (R15) --> PS4) R15 + 4 --> R15

The RETI instruction must be executed when the S-flag is "0".

4.7.15 Notes

4.7.15.1 Delay SlotThe delay slot following a branch instruction has a restriction on EITs.See Section 4.6 "Branch Instructions".


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4.8 Operation Modes

4.8.1 Operation ModesThe operation modes for memory access are bus modes and access modes.

Bus modes Access modes

Single chipInternal ROM/external bus 32-bit bus width

16-bit bus widthExternal ROM/external bus 8-bit bus width

4.8.1.1 Bus ModeIn bus mode, the operations of internal ROM and the external access functions are controlled according to the mode setting pins (MD2 to MD0) and the values of mode data.Although the FR71 architecture supports this bus mode, this macro cannot use the single-chip or internal ROM/external bus mode but can use the external ROM/external bus mode only.

4.8.1.2 Access ModeIn access mode, the external data bus width is controlled according to the WTH1 and WTH0 bits in the mode register and the DBW1 and DBW0 bits in area configuration registers ACR0 to ACR7.

4.8.2 Bus ModesThe FR71 family has three bus modes described below. See Chapter 3 "MEMORY SPACE" for further details.

4.8.2.1 Single-Chip ModeThis mode enables access to peripheral resources, 4K I-bus RAM, and 8K (or 2K) D-bus RAM, while disabling access to any other area.For all external pins, only the peripheral resource pins can function.Therefore, this macro does not operate in the single-chip mode.

4.8.2.2 Internal ROM/External Bus ModeThis mode enables access to peripheral resources, I-bus RAM, and D-bus RAM. In this mode, any access to an externally accessible area becomes access to the external space. Some of the external pins serve as bus pins.

This macro does not operate in the internal ROM/external bus mode.

4.8.2.3 External ROM/External Bus ModeThis mode enables access to peripheral resources, I-bus RAM, and D-bus RAM. In this mode, any access becomes access to the external space. Some of the external pins serve as bus pins.


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4.8.3 Mode SettingThe FR71 family uses the mode pins (MDI[2:0]) and the mode register (MODR) to set the operation mode.

4.8.3.1 Mode PinsThree mode pins MDI[2], MDI[1], and MDI[0] are used to specify a mode vector fetch or test mode.

Setting MDI[2:0] to "010", USRTEST is set to "1" and the device operates in the user circuit test mode. The FR71 core is suspended in the user circuit test mode while SYSCLK and MCLKO are operating. The reserved modes include the FR71 core test mode. In this case, the signal at the FRTEST pin becomes "1" and enters the FR71 core test mode. If the FRTEST pin = "1", that circuit configuration is required which allows the separately defined pins of the FR71 core to be controlled and monitored from the outside of the chip.

4.8.3.2 Mode Register (MODR)The data written to the mode register (MODR) by hardware using a mode vector fetch is called mode data.When this register is set by hardware, the CPU operates in the operation mode corresponding to the register setting.The mode register is set only by an INIT-level reset cause. The user program cannot access this register.However, as an exception, when the macro shifts to emulation mode by INTE instruction, or shifts to emulation mode by a break at a debug using ICE, this register is mapped at 0000_07FDH. Select this function when using ICE, perform the mode data setting before the program loading by writing a appropriate value to this register.

*: No data is existed in the address (0000_07FFH) in the mode register of the FR family..<Register configuration>

[Bits 7-2] Reserved bitsAlways set these bits to "000000". Setting them to any other value may result in an unpredictable operation.

Mode pins Mode name Reset vector access area

Remarks

MDI[2:0]

0 0 0 Reserved -

0 0 1 External ROM mode vector

External Bus width is set by mode data

0 1 0 User circuit test - FR71 stops (with clock signal supplied)

0 1 1 Reserved -

1 0 0 Reserved -

1 0 1 Reserved -

1 1 0 Reserved -

1 1 1 Reserved - :Reserved

0

7

00000 WTH1 WTH0

6 5 4 3 2 1 0

MODR

Initial

XXXXXXXX

Operation mode setting bits


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[Bits 1, 0] WTH1, WTH0 (Bus width setting bits)

These bits specify the bus width. The value of the bits is set in the DBW1 and DBW0 bits in ACR0 (CSO area). Set these bits to a value other than "11".

WTH1 WTH0 Function Remarks

0 0 8-bit bus width External bus mode





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4.9 Reset (Macro Initialization)

4.9.1 OverviewThis section describes the reset operation, the initialization of the FR71 family core macro.When a reset cause occurs, the macro stops all of the program and hardware operations and initializes the device status. This initialized state is called the reset state.When the reset cause is eliminated, the macro restarts program and hardware operations from the initial state. A series of operations from the reset state to the beginning of the restart is called the reset sequence.

4.9.2 Reset IevelsThe FR71 family core macro resets are classified into two levels, and the cause of reset and the effect of initialization are different. Each reset level is described below.

4.9.2.1 Setting Initialization Reset (INIT)The setting initialization reset (INIT) is the highest level of reset that initializes all settings.The major settings initialized by the setting initialization reset (INIT) are listed below.

[Settings initialized by the setting initialization reset (INIT)]- All of the settings concerning the internal clock (clock source selection and divide ratio settings)- All of external bus interface settings- All of the settings concerning other pin states- All of the settings initialized by the operation initialization reset (RST)

For details on each setting item, see the description of the relevant function.Note that the setting initialization reset (INIT) must always be performed via the INITXI immediately after the power is turned on.

4.9.2.2 Operation Initialization Reset (RST)The operation initialization reset (RST) is the normal reset level to initialize program operation.The setting initialization reset (INIT) involves the operation initialization reset (RST).

The major settings initialized by the operation initialization reset (RST) are listed below.

[Settings initialized by the operation initialization reset (RST)]- Operation mode of core macro (bus mode and external bus width setting)- Program operation- CPU and internal bus- Setting values of peripheral resource register - All of the settings for the external bus CSX[0] area

For details on each setting item, see the description of the relevant function.


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4.9.3 Reset SourcesThis section describes each source of a reset and the generated reset level.Reset sources which occurred in the past can be identified by reading the RSRR (reset source register). (For information about registers and flags mentioned below, see Section 4.10.9 "Block diagram of the clock generation control unit" and Section 4.10.10 "Registers in the clock generation control unit".

4.9.3.1 Input to the INITXI Pin (Setting Initialization Reset Pin)The INITXI pin is used as the setting initialization reset pin.The setting initialization reset (INIT) request occurs while the INITXI pin maintains low-level input.High-level input to the INITXI pin cancels the INIT request.When a setting initialization reset (INIT) occurs at the request of this pin, the INIT bit (bit 15) in the RSRR (reset source register) is set.The setting initialization reset (INIT) request via the INITXI pin is the highest level of reset source, overriding any other input, operation, or state.Note that the setting initialization reset (INIT) must always be performed via the INITXI immediately after the power is turned on. Immediately after turning it on, also, keep the low-level input to the INITXI pin for the settling time required for the oscillator so that the oscillator stabilizes its oscillation within that time. (For INIT via the INITXI pin, the oscillation settling time setting is initialized to the minimum value.)

• Reset source: Low-level input to the external INITXI pin• Cancel source: High-level input to the external INITXI pin• Reset level: Setting initialization reset (INIT)• Indication flag: Bit 15 (INIT bit)

4.9.3.2 Input to the RSTXI Pin (Setting Initialization Reset Pin)The RSTXI pin is used as the operation initialization reset pin.The operation initialization reset (RST) request occurs while the RSTXI pin maintains low-level input.High-level input to the RSTXI pin cancels the RST request.When an operation initialization reset (RST) occurs at the request of this pin, the ERST bit (bit 12) in the RSRR (reset source register) is set.When the SYNCR bit (bit 7) in the TBCR (time-base counter control register) has been set (synchronous reset mode), the operation initialization reset (RST) requested via this pin occurs only after every bus access is terminated. Depending on the usage states of the buses, therefore, it may take time before the operation initialization reset (RST) can be generated.

• Reset source: Low-level input to the external RSTXI pin• Cancel source: High-level input to the external RSTXI pin• Reset level: Operation initialization reset (RST)• Indication flag: Bit 12 (ERST bit)


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4.9.3.3 Writing to the STCR: SRST Bit (Software Reset)Writing "0" to the SRST bit (bit 4) in the STCR (standby control register) generates a software reset request.The software reset request is an operation initialization reset (RST) request.When the request is accepted and an operation initialization reset (RST) is generated, the software reset request is canceled.When an operation initialization reset (RST) is generated by a software reset request, the SRST bit (bit 11) in the RSRR (reset source register) is set.When the SYNCR bit (bit 7) in the TBCR (time-base counter control register) has been set (synchronous reset mode), the operation initialization reset (RST) according to a software reset request occurs only after every bus access is terminated. Depending on the usage states of the buses, therefore, it may take time before the operation initialization reset (RST) can be generated.

• Reset source: Writing "0" to the SRST bit (bit 4) in the STCR (standby control register)• Cancel source: Occurrence of an operation initialization reset (RST)• Reset level: Operation initialization reset (RST)• Indication flag: Bit 11 (SRST bit)

4.9.3.4 Watchdog ResetWhen data is written to the RSRR (watchdog timer control register), the watchdog timer is activated. A watchdog reset request occurs unless A5h/5Ah writing to the WPR (watchdog reset defer register) is performed within the period set by the WT1 and WT0 bits (bits 9 and 8) in the RSRR.The watchdog reset request is a setting initialization reset (INIT) request. When the request is accepted and a setting initialization reset (INIT) or operation initialization reset (RST) is generated, the watchdog reset request is canceled.When a setting initialization reset (INIT) is generated by a watchdog reset request, the WDOG bit (bit 13) in the RSRR (reset source register) is set.Note that the oscillation settling time setting is not initialized when a setting initialization reset (INIT) is generated by a watchdog reset request.

• Reset source: Watchdog timer time-out• Cancel source: Occurrence of a setting initialization reset (INIT) or operation initialization reset (RST)• Reset level: Setting initialization reset (INIT)• Indication flag: Bit 13 (WDOG bit)


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4.9.3.5 Input to the HSTXI Pin (Hardware Standby Pin)The HSTXI pin is used as the hardware standby pin. A hardware standby request occurs while the HSTXI pin maintains low-level input.When the hardware standby request is accepted and the core macro enters the hardware standby state, a setting initialization reset (INIT) is generated at the same time.High-level input to the HSTXI pin cancels the hardware standby request and the setting initialization reset (INIT) as well.If a setting initialization reset (INIT) request is generated by the INITXI pin in the hardware standby state, the hardware standby request is canceled but the setting initialization reset (INIT) remains generated.When a setting initialization reset (INIT) according to the transition to the hardware standby state occurs, the HSTB bit (bit 14) in the RSRR (reset source register) is set.Note that, when a hardware standby request occurs immediately after the power is turned on, the setting initialization reset (INIT) via the INITXI pin has a higher priority. If the setting initialization reset (INIT) via the INITXI pin is then canceled and the core macro enters the hardware standby state, the oscillation settling time setting is initialized to the maximum value. The oscillation settling time is set to the maximum value after the hardware standby request is canceled.

• Reset source: Low-level input to the HSTXI pin• Cancel source: High-level input to the HSTXI pin or a setting initialization reset (INIT) via the INITXI pin• Reset level: Setting initialization reset (INIT)• Indication flag: Bit 14 (HSTB bit)

4.9.3.6 Input to the LINITXI Pin (Undervoltage Detection Standby Pin)

The LINITXI pin is used as the undervoltage detection standby pin. Undervoltage detection standby is operatred same as hardware standby.A undervoltage detection standby request occurs while the LINITXI pin maintains low-level input.When the undervoltage detection standby request is accepted and the core macro enters the hardware standby state, a setting initialization reset (INIT) is generated at the same time.High-level input to the LINITXI pin cancels the undervoltage detection standby request and the setting initialization reset (INIT).If a setting initialization reset (INIT) request is generated by the INITXI pin in the hardware standby state, the undervoltage detection standby request is canceled but the setting initialization reset (INIT) remains generated.When a setting initialization reset (INIT) according to the transition to the hardware standby state occurs, the LINIT bit (bit 10) in the RSRR (reset source register) is set.Note that, when a undervoltage detection standby request occurs immediately after the power is turned on, the setting initialization reset (INIT) via the INITXI pin has a higher priority. If the setting initialization reset (INIT) via the INITXI pin is then canceled and the core macro enters the hardware standby state, the oscillation settling time setting is initialized to the maximum value. The oscillation settling time is set to the maximum value after the undervoltage detection standby request is canceled.

• Reset source: Low-level input to the LINITXI pin• Cancel source: High-level input to the LINITXI pin or a setting initialization reset (INIT) via the INITXI

pin• Reset level: Setting initialization reset (INIT)• Indication flag: Bit 10 (LINIT bit)


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4.9.4 Reset SequenceWhen a reset source is eliminated, the core macro starts executing the reset sequence.The operations in the reset sequence vary with the reset level.This section describes the operations in the reset sequence for each reset level.

4.9.4.1 Reset Sequence for Setting Initialization Reset (INIT)When the setting initialization reset (INIT) request is cleared, the core macro performs the following operations sequentially.

(1) Cancels the setting initialization reset (INIT) and enters the oscillation stabilization wait state.(2) Maintains the operation initialization reset (RST) state and the internal clock suspended for the

oscillation settling time (set by the OS1 and OS0 bits, or bits 3 and 2 in the STCR).(3) Enters the operation initialization reset (RST) state and starts internal clock operation.(4) Cancels the operation initialization reset (RST) and returns to the normal operating state.(5) Operates as 8 bit bus width and reads a mode vector from address 000FFFF8h.(6) Writes the mode vector to the MODR (mode register)(7) Reads a reset vector from address 000FFFFCh.(8) Writes the reset vector to the PC (program counter).(9) Starts program operation from the address indicated by the PC (program counter).

4.9.4.2 Reset Sequence for Operation Initialization Reset (RST)When the operation initialization reset (RST) request is cleared, the core macro performs the following operations sequentially.

(1) Cancels the operation initialization reset (RST) and shifts to the normal operating state.(2) Operates as 8 bit bus width and reads a mode vector from address 000FFFF8h.(3) Writes the mode vector to the MODR (mode register).(4) Reads a reset vector from address 000FFFFCh.(5) Writes the reset vector to the PC (program counter).(6) Starts program operation from the address indicated by the PC (program counter).


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4.9.5 Oscillation Settling TimeThe device automatically switches to the oscillation stabilization waiting state when it returns from a state in which the original oscillation stopped, or may have stopped.

This feature prevents the macro from using unstable clock input immediately after the start of oscillation.During the oscillation settling time, the supply of clock signals to the internal and external resources is stopped when only the internal time-base timer operates, until the oscillation settling time set in the STCR (standby control register) has passed.

The transition to the oscillation stabilization wait state is detailed below.

4.9.5.1 Causes of Transition to Oscillation Stabilization Wait StateThe transition to the oscillation stabilization wait state is caused as follows.

(1) Upon cancellation of a setting initialization reset (INIT)Immediately after a setting initialization reset (INIT) is canceled, the core macro enters the oscillation stabilization wait state. When the oscillation settling time has passed, the macro then enters the operation initialization reset (RST) state.

(2) Upon returning from the stop modeImmediately after being released from the stop mode, the core macro enters the oscillation stabilization wait state.If the macro is released by a setting initialization reset (INIT) request, the macro enters the setting initialization reset (INIT) state. The macro then enters the oscillation stabilization wait state after the setting initialization reset (INIT) is canceled.When the oscillation settling time has passed, the macro then enters the state corresponding to the source that canceled the stop mode:

- Effective external interrupt request input (including an NMI)=> The macro shifts to the normal operation state.

- Setting initialization reset (INIT) request=> The macro enters the setting initialization reset (INIT) state.

- Operation initialization reset (RST)=> The macro enters the operation initialization reset (RST) state.


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4.9.5.2 Selecting the Oscillation Settling TimeThe oscillation settling time is counted by the internal time-base counter.When an oscillation stabilization wait cause occurs and the core macro enters the oscillation stabilization wait state, the internal time-base counter is initialized and starts measurement of the oscillation settling time.The oscillation settling time setting can be selected from four options using the OS1 and OS0 bits (bits 3 and 2) in the STCR (standby control register).Once selected, the oscillation settling time setting is not initialized unless the setting initialization reset (INIT) via the INITXI pin occurs. Even when an operation initialization reset (RST) or a setting initialization reset (INIT) by a watchdog reset, hardware standby state, or undervoltage detection standby state occurs, the oscillation settling time set before the occurrence of a reset.

The following four options are available as the oscillation settling time settings for their specific cases:

- OS1, OS0 = "00": No oscillation settling time(Oscillator is not stopped in the stop mode.)

- OS1, OS0 = "01": Oscillation settling time (Short)(Oscillator is not stopped in the stop mode.)

- OS1, OS0 = "10": Oscillation settling time (Intermediate)(A quickly stabilizing type of oscillator is being used, such as a ceramic resonator.)

- OS1, OS0 = "11": Oscillation settling time (Long)(A general crystal oscillator is being used.)

Note that the setting initialization reset (INIT) via the INITXI must always be performed immediately after the power is turned on. Immediately after turning it on, also, keep the low-level input to the INITXI pin for the settling time required for the oscillator so that the oscillator stabilizes its oscillation within that time. (For INIT via the INITXI pin, the oscillation settling time setting is initialized to the minimum value.)Note that, when a hardware standby request occurs immediately after the power is turned on, the setting initialization reset (INIT) via the INITXI pin has a higher priority. If the setting initialization reset (INIT) via the INITXI pin is then canceled and the core macro enters the hardware standby state, the oscillation settling time setting is initialized to the maximum value. The oscillation settling time is set to the maximum value after the hardware standby request is canceled.


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4.9.6 Reset Operation ModesThe operation initialization reset (RST) has two modes: asynchronous reset and synchronous reset modes. Either can be selected using the SYNCR bit (bit 7) in the TBCR (time-base counter control register).The reset mode setting is initialized only at a setting initialization reset (INIT).The setting initialization reset (INIT) is performed always as an asynchronous reset.The operation in each reset mode are detailed below.

4.9.6.1 Asynchronous Reset OperationThe asynchronous reset operation means 1) the operation of prompt transition to the operation initialization reset (RST) state, OR 2) hardware standby state as soon as an operation initialization reset (RST) request, OR3) hardware standby request is occurred.When a reset (RST) request or hardware standby request is accepted in the asynchronous reset mode, the core macro enters the reset (RST) state or hardware standby state promptly regardless of the operation status of internal bus access.This mode does not guarantee the result of the bus access being performed at the transition to each state. However, the mode can accept such requests without fail.The asynchronous reset mode is selected when the SYNCR bit (bit 7) in the TBCR (time-base counter control register) is "0".When the initial value immediately after a setting initialization reset (INIT) occurs, the asynchronous reset mode is selected.

4.9.6.2 Synchronous Reset OperationThe synchronous reset operation means1) the operation of transition to the operation initialization reset (RST) state, OR2) hardware standby state after all bus accesses terminate when as an operation initialization reset (RST)

request, OR3) hardware standby request is occurred.In the synchronous mode, even though a reset (RST) request or hardware standby request is accepted, the core macro does not enter the reset (RST) state or hardware standby state while any internal bus access is being performed.When such a request is accepted, a sleep request is issued to the internal buses. When each internal bus terminates operation to enter the sleep state, the core macro enters the operation initialization reset (RST) state or hardware standby state.Since all bus accesses terminate before the macro enters each state in this mode, their results are guaranteed.If any bus access does not terminate for some reason, however, the macro cannot accept such requests in that period of time. (Even in this case, the setting initialization reset (INIT) has a higher effect immediately.) Bus access does not terminate in the following cases.1) when the internal bus is generating a new bus access request when BGRNTX (bus release acknowledge) is

enabled and BRQ (bus release request) has been input to the external bus interface.2) when RDY (ready request) has been input to the external bus interface, the bus wait state is enabled. Also,

although the following case results in transition to each state, it takes a long time.

The DMA controller does not delay the transition to each state while it stops transfer to acept each request.The synchronous reset mode is selected when the SYNCR bit (bit 7) in the TBCR (time-base counter control register) is "1".The initial value immediately after a setting initialization reset (INIT) occurs, the asynchronous reset mode is selected.


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4.10 Clock Generation Control

4.10.1 OverviewThe internal operation clock signals for the FR family core macro are generated as follows:

- ソースクロックの選択：クロックの供給源を選択します。- ベースクロックの生成：ソースクロックを 2分周または PLL発振させ , 基本クロックを生成します。- Internal clock signals: Three types of operation clock signals to be supplied to different parts are

generated by frequency-dividing the base clock.

The generation and control of each type of clock signal are described below.(For details of registers and flags mentioned below, see Section 4.10.8 "Block diagram of the clock generation control unit" and Section 4.10.9 "Registers in the clock generation control unit".)

4.10.2 External ClockThe External clock signal is input always via the X0 pin.外部ソースクロックに関しましては「1.7.1. クロック」を参照してください。

4.10.3 発振器発振子は , X0, X1端子に接続します。

4.10.4 PLL制御メインのソースクロックに対応した PLL発振回路について , 動作（発振）許可／禁止と逓倍率設定を独立に制御することが可能です。各制御は , クロックソース制御レジスタ（ＣＬＫＲ）の設定によって行います。

4.10.4.1 PLL動作許可メイン PLL発振動作の許可 /停止は , クロックソース制御レジスタ (CLKR)のビット 10(PLL1ENビット )の設定によって行います。

PLL動作許可

どちらのビットも設定初期化リセット (INIT)後は "0"に初期化され ,PLLの発振動作は停止しています。停止中は ,ソースクロックとして ,PLL出力を選択することはできません。

プログラム動作を開始したら ,まずクロックソースとして使用する PLLの逓倍率を設定し ,かつ動作許可した後 ,PLLのロック待ち時間経過後にソースクロックを切り替えてください。この際の PLLロック待ち時間は ,タイムベースタイマ割込みを使用することができます。

ソースクロックとして PLL出力を選択している間は ,その PLLは動作停止させることはできません (レジスタへの書込みは無効となります )。ストップモードに移行する際などでPLLを停止させたい場合は ,一度ソースクロックをメインクロックの 2分周したものに選択し直した後 ,PLLを停止させてください。

なお ,スタンバイ制御レジスタ (STCR)のビット 0(OSCD1ビット )やビット 1(OSCD2ビット )により ,ストップモード中の発振が停止するように設定してある場合 ,対応するPLLはストップモード遷移時に自動的に停止しますので ,動作停止を改めて設定する必要はありません。その後 ,ストップモードから復帰する際 ,PLLは自動的に発振動作を開始します。ストップモード中の発振が停止しないように設定してある場合は , PLLは自動では停止


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しません。この場合は ,必要であればストップモード移行前にあらかじめ動作停止を設定してください。

4.10.4.2 PLL逓倍率メイン PLLの逓倍率は ,クロックソース制御レジスタ (CLKR)のビット 14-12(PLL1S2,PLL1S1,PLL1S0ビット )によって設定します。設定初期化リセット (INIT)後は ,全ビットが "0"に初期化されています。

PLL逓倍率設定

PLL逓倍率設定を初期値より変更する場合 ,プログラム動作開始後 ,PLLを動作許可する前または同時に設定してください。逓倍率変更後は ,ロック待ち時間経過後にソースクロックを切り替えてください。この際の PLLロック待ち時間は ,タイムベースタイマ割込みを使用することができます。

動作中に PLL逓倍率設定を変更する場合 ,一度ソースクロックを該当 PLL以外に切り替えてから変更してください。逓倍率変更後は ,上記同様にロック待ち時間経過後にソースクロックを切り替えてください。

PLL逓倍率設定の変更を ,PLL使用中に変更することも可能ですが ,この際は逓倍率設定書き換え後から自動的に発振安定待ち状態に遷移し ,設定された発振安定待ち時間が経過するまでの間はプログラム動作が停止します。

PLL以外にクロックソースを切り替えた場合は ,プログラム動作は停止しません。

4.10.5 Oscillation Settling Time The oscillation settling time is required when the unstable clock selected as the source clock.INITXで外部で発振安定待ちを制御する必要があります。(See section 4.9.5 "Oscillation settling time".)

[Wait times after the power is turned on]After the power is turned on, the oscillation stabilization wait time for the input clock is required.The oscillation stabilization wait time is kept by the time for inputting low-level to the INITXI pin.

4.10.6 Clock DistributionThe operation clock signals for various functions are produced based on the base clock signal generated from the source clock.The FR family has a total of three types of internal operation clock signals, can independently set the frequency divide ratio.The three types of internal operation clock signals are summarized below.

(1) CPU clock signal (CLKB)

This clock signal is used for the CPU, internal memory (in FR core), and internal buses.The circuits using this clock signal include:

- CPU- Instruction cache- Data RAM- Bit search module


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- I-bus, D-bus, X-bus, F-bus- DMA controller- DSU

The maximum operating frequency is 33 MHz. Do not set a combination of the multiply-by rate and divide ratio which is higher than maximum frequency.

(2) Peripheral clock signal (CLKP)

This clock signal is used for core resources and peripheral buses.The circuits using this clock signal include:

- Peripheral buses in the core- Clock control unit (only the bus interface unit)- Interrupt controller- External interrupt inputs- UART- 16-bit timer

The maximum operating frequency is 16.5 MHz. Do not set a combination of the multiply-by rate and divide ratio which is higher than maximum frequency.

(3) External interface clock signal (MCLKO)

This clock signal is used for the peripheral resources.- LAN controller, GPIO IF, I2C IF, external memory IF, internal ROM/RAM

This clock signal is used for the external interface.The circuits using this clock signal include:

- Memory interface- CLK outputs (MCLK)

The maximum operating frequency is 33 MHz. Do not set a combination of the multiply-by rate and divide ratio which is higher than maximum frequency.

4.10.7 Clock Frequency DivisionFor each type of internal operation clock signal, the divide ratio relative to the base clock frequency can be set. This feature allows the optimum operating frequency to be set for each circuit.The divide ratio is set by the combination of the DIVR0 (base clock frequency division setting register 0) and DIVR1 (base clock frequency division setting register 1). Each register has four setting bits for each type of clock signal. The divide ratio of a clock signal relative to the base clock frequency is expressed as "the register setting value + 1". Even though ratio setting is an odd number, the duty is always 50.When the divide ratio setting is changed, the new setting takes effect at the next rising edge of the clock signal.Even when an operation initialization reset (RST) occurs, the divide ratio setting is not initialized but remains unchanged. It is initialized only at a setting initialization reset (INIT). The initial divide ratio is "1" for all clock signals except the peripheral clock signal (CLKP). Before changing the source clock with a faster one, be sure to set the divide ratio.Each type of clock signal has the specified maximum operating frequency. Setting a combination of the source clock and divide ratio, which is higher than maximum frequency, the operation of the device is not guaranteed. Take care not to use the wrong sequence to change the source clock selection setting.


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4.10.8 Block Diagram of the Clock Generation Control UnitThis section provides a block diagram of the clock generation control unit. For information on registers in the diagram, see Section 4.10.10 "Registers in the clock generation control unit".

Oscillation circuitX1

X0

Reset generationF/F

Counter clock

Interrupt enable

INITXI pin

State transfer control ciruit

CTBR register

WPR register

Timebase counter

Watchdog F/F

Overflow detection F/FTBCR register

RSRR register

STCR register

Internal reset

Internal interrupt

[Clock generating block]

1/2

PLL

CLKR register

Each peripheral clockPeripheral clock division

External bus clockExternal bus clock division

CPU clockCPU clock division

DIVR0,1 register

[Stop/sleep control block]

SLEEP state

Timebase timer interrupt request

Internal reset (INIT)

STOP state

Reset generationF/F Internal reset (RST)

[Reset factor circuit]

[Watchdog control block]

Selector

Sel

ecto

r

Sel

ecto

rS

elec

tor

Sel

ecto

r

Sto

p co

ntro

l

R-b

us


89

4.10.9 Registers in the Clock Generation Control Unit

4.10.9.1 RSRR: Reset Source Register and Watchdog Timer Control Register

*: Variable with the causex: Not initialized

This register stores the cause of the most recently generated reset, sets the time interval for the watchdog timer, and controls its activation.Reading from this register clears the stored reset cause after it is read. If two or more resets occur before it is read, multiple reset cause flags are accumulated and set.Writing to this register activates the watchdog timer. After that the watchdog timer keeps on operating until a reset (RST) occurs.

[Bit 15]: INIT (INITialize reset occurred)This bit indicates whether a reset (INIT) by INITXI pin input has occurred.

- The bit is initialized to "0" immediately after a reading.- Readable; writing has no effect to the bit value.

[Bit 13]: WDOG (WatchDOG reset occurred)This bit indicates whether a reset (INIT) by the watchdog timer has occurred.

- The bit is initialized to "0" immediately after a reset by INITXI pin input or a reading.- Readable; writing has no effect to the bit value.

[Bit 11]: SRST (Software ReSeT occurred)This bit indicates whether a reset (RST) by writing to the SRST bit (software reset) in the STCR register has occurred.

- The bit is initialized to "0" immediately after a reset by INITXI pin input or a reading.

Bit 15 14 13 12 11 10 9 8

address : 00000480h INIT - WDOG - SRST LINIT WT1 WT0

R R R R R R R/W R/W

Initial value (INITX pin) 1 0 0 0 0 0 0 0

Initial value (INIT) * * * x x * 0 0

Initial value (RST) x x x * * x 0 0

0 INIT by INITXI pin input has not occurred.

1 INIT by INITXI pin input has occurred.

0 INIT by watchdog timer has not occurred.

1 INIT by watchdog timer has occurred.

0 RST by software reset has not occurred.

1 RST by software reset has occurred.


90

- Readable; writing has no effect to the bit value.

[Bit 10]: LINIT (Lowvoltage detect INITialize reset occurred)This bit indicates whether a reset (INIT) by LINITXI pin input has occurred.

- The bit is initialized to "0" immediately after a reset by INITXI pin input or a reading.- Readable; writing has no effect to the bit value.

[Bits 9, 8]: WT1, WT0 (Watchdog interval Time select)These bits are used to specify the time interval required for the watchdog timer.The combination of values written to these bits selects the time interval for the watchdog timer from the four options listed below.

( : the system base clock period.)

- These bits are initialized to "00" at a reset (RST)- Readable; writing is valid only once after a reset (RST). Any further writing is invalid.

0 INIT by LINITXI pin input has not occurred.

1 INIT by LINITXI pin input has occurred.

WT1 WT0 Minimum write-to-WPR interval required for suppressing watchdog reset

Time from final 5AH write to WPR until watch-dog reset is generated

0 0 x 2 16 (Initial value) x 2 16 to x 2 17

0 1 x2 18 x 2 18 to x 2 19

1 0 x 2 20 x 2 20 to x 2 21

1 1 x 2 22 x 2 22 to x 2 23

φ φ φ

φ φ φ

φ φ φ

φ φ φ

φ


91

4.10.9.2 STCR: Standby Control Register

*: Only at the same time as initialization via the INITXI pin. Otherwise, same as after an INIT reset.

This register controls the operation mode of the core macro.The register controls the transition to each of the two standby modes (stop and sleep modes), controls the pin status and oscillation disable mode during the stop mode, sets the oscillation settling time, and issues a software reset.

Note: In standby mode, the following sequences must be used after using the synchronous standby mode (set by bit8 SYNCS bit of TBCR: time base counter control register).

(LDI #value_of_standby,R0) ; Value_of_standby is the data which is written to STCR. (LDI #_STCR,R12) ; _STCR is the address of STCR (481H)STB R0,@R12 ; Writing to standby control register (STCR) LDUB @R12,R0 ; STCR read for synchronous standby LDUB @R12,R0 ; Dummy read STCR againNOPNOPNOPNOPNOP

After the standby is returned, set I flag, ILM, and ICR in order to branch to the interrupt handler (return cause).

[Bit 7]: STOP (STOP mode)This bit selects whether to cause a transition to the stop mode. If "1" is written to both of this bit and the SLEEP bit (bit 6), this bit has a higher priority, causing a transition to the stop mode.

- The bit is initialized to "0" at a reset (RST) or when a stop-mode return cause is generated.- Readable and writable.

bit 7 6 5 4 3 2 1 0

address : 00000481h STOP SLEEP HIZ SRST OS1 OS0 - -

R/W R/W R/W R/W R/W R/W - R/W

Initial value (INITXI pin) 0 0 1 1 0 0 1 1

Initial value (HSTXI pin) * 0 0 1 1 1 1 1 1

Initial value (INIT) 0 0 1 1 x x 1 1

Initial value (RST) 0 0 x 1 x x x x

0 Do not enter stop mode. (Initial value)

1 Enter stop mode.


92

[Bit 6]: SLEEP (SLEEP mode)

This bit selects whether to cause a transition to the sleep mode. If "1" is written to both of this bit and the STOP bit (bit 7), the STOP bit (bit 7) has a higher priority, causing a transition to the stop mode.

- The bit is initialized to "0" at a reset (RST) or when a sleep-mode return cause is generated.- Readable and writable.

[Bit 5]: HIZ (HIZ mode)This bit controls the pin status during the stop mode.

- The bit is initialized to "0" at a reset (INIT).- Readable and writable.

[Bit 4]: SRST (Software ReSeT)

This bit issues a software reset (RST)

- The bit is initialized to "0" at a reset (RST).- Readable and writable. "1" is always read.

[Bits 3, 2]: OS1, OS0 (Oscillation Stabilization time select)These bits are used to specify the oscillation settling time to be waited immediately after a reset (INIT) or upon a return from the stop mode.The combination of values written to these bits selects the oscillation settling time from the four options listed below.

( : the system base clock period. It is the cycle of the oscillator input in this case.)

- These bits are initialized to "00" at a reset (INIT) by INITXI pin input.If the reset (INIT) by INITXI pin input and HSTXI pin input are enabled at the same time, the bits are initialized to "11".

- Readable and writable.

[Bit 1]: Reserved- This bit is initialized to "1" at a reset (INIT).- Set the bit to "1" at writing.

0 Do not enter sleep mode. (Initial value)

1 Enter sleep mode.

0 Maintain the pin status before a transition to stop mode.

1 Keep pin output in high impedance state during stop mode. (Initial value)

0 Issue software reset.

1 Do not issue software reset. (Initial value)

OS1 OS0 Oscillation settling time Oscillation at 108 MHz and XINBY = 1

0 0 x 2 1 (Initial value) 18.5 [nsec]

0 1 x 2 11 18.9 [usec]

1 0 x 2 16 606.8 [usec]

1 1 x 2 22 38.8 [msec]

φ

φ

φ

φ

φ


93

4.10.9.3 TBCR: Time-Base Counter Control Register

This register controls time-base timer interrupts.The register enables time-base timer interrupts, selects the interrupt time interval, and sets optional functions for reset operation.

[Bit 15]: TBIF (TimeBase timer Interrupt Flag)This bit is used as the time-base timer interrupt flag.The flag indicates that the time-base counter has expired the time interval (set the TBC2 to TBC0 bits, bits 13 to 11).With an interrupt enabled by bit 14: TBIE bit (TBIE = "1"), when this bit is set to “1”, a time-base timer interrupt request is generated.

- The bit is initialized to "0" at a reset (RST).- Readable and writable. Note that only "0" can be written. Writing "1" has no effect to the bit value.

Reading the bit using a read modify write instruction always returns "1".

[Bit 14]: TBIE (TimeBase timer Interrupt Enable)This bit is used as the time-base timer interrupt request output enable bit.The bit controls interrupt request output when the time-base counter has expired the time interval. When this bit is set to "1", a time-base timer interrupt request occurs when the bit 15 (TBIF bit) is set to "1" .

- The bit is initialized to "1" at a reset (RST).- Readable and writable.

[Bits 13-11]: TBC2, TBC1, TBC0 (TimeBase timer Counting time select)These bits are used to set the time interval required for the time-base counter used for the time-base timer.The combination of values written to these bits selects the time interval for the time-base counter from the eight options listed below.

Bit 15 14 13 12 11 10 9 8

address : 00000482h TBIF TBIE TBC2 TBC1 TBC0 - SYNCR SYNCS

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value (INIT) 0 0 x x x x 0 0

Initial value (RST) 0 0 x x x x x x

Clear cause "0" is written by instruction

Set cause Specified time interval has passed (falling edge of time-base counter output is detected).

0 Disable time-base timer interrupt request output. (Initial value)

1 Enable time-base timer interrupt request output.


94


- The initial value is undefined. Be sure to set a value before enabling interrupts.- Readable and writable.

[Bit 10]: (Reserved bit)This bit is a reserved bit. The value read is undefined. Writing to this bit has no effect to any function of the register.

[Bit 09]: SYNCR (SYNChronous Reset enable)This bit is used as the synchronous reset operation enable bit.The bit selects one of the two types of reset operation to be performed:1) when a operation initialization reset (RST) request occurred, OR 2) when hardware standby request occurred. One is the asynchronous reset operation for prompt transition to the reset (RST) or hardware standby state as soon as the request is issued. The other is the synchronous reset operation for transition to the reset (RST) or hardware standby state after all bus accesses are terminated.


[Bit 08]: SYNCS (SYNChronous Standby enable)This bit is used as the synchronous standby operation enable bit.To use standby mode (sleep mode or stop mode), this bit must be set to “1”.


TBC2 TBC1 TBC0 Time-base counter time interval Oscillation at 108 MHz and XINBY = 1

0 0 0 x 2 11 18.9 [usec]

0 0 1 x 2 12 37.9 [usec]

0 1 0 x 2 13 75.9 [usec]

0 1 1 x 2 22 38.8 [msec]

1 0 0 x 2 23 77.7 [msec]

1 0 1 x 2 24 155.3 [msec]

1 1 0 x 2 25 310.7 [msec]

1 1 1 x 2 26 621.4 [msec]

0 Normal reset operation (Initial value)

1 Synchronous reset operation

0 Normal standby operation (Initial value)

1 Synchronous standby operation

φ

φ

φ

φ

φ

φ

φ

φ

φ


95

4.10.9.4 CTBR: Time-Base Counter Clear Register

This register initializes the time-base counter.When A5h and 5Ah are continuously written to this register, all the bits in the time-base counter are cleared to "0" immediately after the 5Ah write. There is no restriction on the interval between A5h writing and 5Ah writing. If any data other than 5Ah is written following the A5h writing, however, A5h must be written again before 5Ah is written in order to clear the time-base counter.

The value read from this register is undefined.Note: Clearing the time-base counter using this register temporarily changes the oscillation settling time,

watchdog timer interval, and time-base timer interval.

Bit 7 6 5 4 3 2 1 0

address : 00000483h D7 D6 D5 D4 D3 D2 D1 D0

W W W W W W W W

Initial value (INIT) x x x x x x x x

Initial value (RST) x x x x x x x x


96

4.10.9.5 CLKR: Clock Source Control Register

クロックソース制御レジスタ (CLKR)は ,システムのベースクロックとするクロックソースの選択や PLLの制御を行うレジスタです。このレジスタでクロックソースを 2 種類のうちから選択します。また ,PLL の動作許可および逓倍率の選択を制御します。

The following explains the each bit function of clock source control register (CLKR).

[Bit 15]: (reserved bit)

This bit is a reserved bit.

[Bit 14 to 12]: PLL1S2,PLL1S1,PLL1S0 (PLL1 ratio Select 2 to 0)

これらのビットは ,PLLの逓倍率選択ビットです。下記表に示す PLLの逓倍率を 8種類のうちから選択します。

These bits prohibit to rewrite while selecting the main PLL as a clock source.

*1: φ is a cycle of system base clock.- The bit is initialized to “000” at a reset (INIT). - Readable and writable.

Note:

The oscillation guaranteed frequency range of PLL is 32.5 to 62.5 MHz. It is necessary to set withinthis range.

[Bit 11]: (reserved bit)

This bit is a reserved bit.

表 10.9-1 メイン PLL逓倍率の設定

PLL1S2 PLL1S1 PLL1S0 メイン PLL逓倍率原発振 16.5MHzの場合

0 0 0 × 1　 (等倍 ) Setting disabled

0 0 1 × 2　(2逓倍 ) φ*1=30.0 [ns](33.0 [MHz])

0 1 0 × 3　(3逓倍 ) φ*1=20.2 [ns](49.5 [MHz])

0 1 1 × 4　(4逓倍 ) Setting disabled





Bit 15 14 13 12 11 10 9 8

Address: 0000 0484H - PLL1S2 PLL1S1 PLL1S0 - PLL1EN CLKS1 CLKS0

Initial value (INIT) 0 0 0 0 0 0 0 0




97

[Bit 10]: PLL1EN(PLL1 ENable)

This bit is operation enable bit of main PLL.These bits prohibit to rewrite while selecting the main PLL as a clock source.Also, it is prohibited to select the main PLL as a clock source while this bit is “0” (depending on setting of CLKS1 and CLKS0 bits of bit 9 and 8).

STCRのビット 1(OSCD2ビット )が "1"であると ,ストップモード中はこのビットが "1"であっても PLLは停止します。ストップモードからの復帰後は動作許可に戻ります。

The following shows the function of operation enable bit (PLL1EN) of main PLL.Å@Å@Å@Å@

- The bit is initialized to “0” at a reset (INIT). - Readable and writable.

[Bit 9, 8]: CLKS1,CLKS0(CLocK source Select)

These bits specify the using clock source at a FR core.

これらのビットに書き込む値により ,クロックソースを以下の表に示す 2種類のうちから選択します。

The following shows the setting of clock source.

以下に ,CLKS1,CLKS0ビットの変更不可能な組み合せおよび変更可能な組み合せを示します。

- The bit is initialized to “00” at a reset (INIT). - Readable and writable.

表 10.9-2 Function of operation enable bit (PLL1EN) of main PLL

PLL1EN Function

0 Main PLL stop (initial value)

1 Main PLL operation enable

表 10.9-3 Setting of clock source

CLKS1 CLKS0 Setting of clock source

0 0 X0/X1よりの原発振入力の 2分周 (初期値 )

0 1 X0/X1よりの原発振入力の 2分周

1 0 Main PLL

1 1 Setting disabled

表 10.9-4 CLKS1,CLKS0ビットの変更不可能 /変更可能な組み合せ

変更不可能な組み合せ変更可能な組み合せ

"00"→"11" "00"→"01" or "10"

"01"→"10" "01"→"11" or "00"

"10"→"01" or "11" "10"→"00"

"11"→"00" or "10" "11"→"01"


98

4.10.9.6 WPR: Watchdog Reset Defer Register

This register defers the generation of a watchdog reset.When A5h and 5Ah are written to this register in succession, the FF (flip-flop) for detecting the watchdog timer is cleared immediately after the 5Ah is written, deferring the generation of a watchdog reset. There is no restriction on the interval between A5h write and 5Ah write. If any data other than 5Ah is written following the A5h write, however, A5h must be written again before 5Ah is written in order to clear the FF. Note also that a watchdog reset is generated unless both writing of A5h and 5Ah are finished within the period specified in the table below.The period varies with the combination of the settings of the WT1 and WT0 bits (bits 9 and 8) in the RSRR register as follows.

( : the system base clock period. WT1 and WT0 are bits 9 and 8 in the RSRR, used to set the watchdog timer

interval.)Note, however, that the FF is cleared automatically when the CPU is not operating such as in the stop or sleep mode or during DMA transfer. Under such a condition, a watchdog reset is deferred automatically. If an external bus hold request (BRQ) has been accepted, however, the watchdog reset is not deferred. Before holding an external bus for an extended period of time, establish the sleep mode and then input the hold request (BRQ).The value read from this register is undefined.

Bit 7 6 5 4 3 2 1 0

Address : 00000485h D7 D6 D5 D4 D3 D2 D1 D0

W W W W W W W W

Initial value (INIT) x x x x x x x x


WT1 WT0 Minimum write-to-WPR interval required for suppressing watchdog reset

Time from final 5AH write to WPR until watchdog reset is generated

0 0 x 2 ^16 (Initial value) x 2 ^16 to x 2^ 17

0 1 x 2^ 18 x 2^ 18 to x 2 ^19

1 0 x 2 ^20 x 2 ^20 to x 2 ^21

1 1 x 2 ^22 x 2 ^22 to x 2 ^23

φ φ φ

φ φ φ

φ φ φ

φ φ φ

φ


99

4.10.9.7 DIVR0: Base Clock Divide Ratio Setting Register 0

This register controls the frequency divide ratio for each type of internal clock signal relative to the base clock signal.The register sets the divide ratios for the CPU/internal bus clock signal (CLKB) and for the peripheral circuit/peripheral bus clock signal (CLKP).Each type of clock signal has the specified maximum operating frequency. If a combination of the source clock and divide ratio is set, which is higher than maximum frequency, the operation of the device is not guaranteed. Take care not to use the wrong sequence to change the source clock selection setting.The limited value of the maximum base clock frequency is different for each core. For the details, refer to “FR71E Core Series Lin-up Manual”.When the divide ratio setting in this register is changed, the new setting becomes effective at the next clock rate.

[Bits 15-12]: B3, B2, B1, B0 (clkB divide select 3-0)These bits are used to set the CPU clock (CLKB) frequency divide ratio.The clock frequency divide ratio set by these bits applies to the clock signal for the CPU, internal memory, and internal buses.The combination of values written to these bits selects the divide ratio (clock frequency) for the CPU/internal bus clock signal relative to the base clock signal, from the 16 types listed below.The maximum operating frequency is different according to individual cores. Do not set the bits to a divide ratio which is higher than maximum frequency. For the maximum operating frequency of each core, refer to “FR71E Core Series Lin-up Manual”.


- These bits are initialized to "0000" at a reset (INIT). Readable and writable.

Bit 7 6 5 4 3 2 1 0

address : 00000486h B3 B2 B1 B0 P3 P2 P1 P0




B3 B2 B1 B0 Clock divide ratio Clock frequency: Oscillation at 108 [MHz] and XINBY = 1

0 0 0 0 33 [MHz] (Initial value)

0 0 0 1 x 2 (Divide by 2) 16.5 [MHz]

0 0 1 0 x 3 (Divide by 3) 11 [MHz]

0 0 1 1 x 4 (Divide by 4) 8.25 [MHz]

0 1 0 0 x 5 (Divide by 5) 6.6 [MHz]

0 1 0 1 x 6 (Divide by 6) 5.5 [MHz]

... ... ... ... ... ...

1 1 1 1 x 16 (Divide by 16) 2.063 [MHz]

φ

φ

φ

φ

φ

φ

φ

φ


100

[Bits 11-8]: P3, P2, P1, P0 (clkP divide select 3-0)

These bits are used to set the peripheral clock (CLKP) frequency divide ratio.The clock frequency divide ratio set by these bits applies to the clock signal for peripheral circuits and peripheral buses (CLKP).The combination of values written to these bits selects the divide ratio (clock frequency) for the peripheral circuit/peripheral bus clock signal relative to the base clock signal, from the 16 types listed below.The maximum operating frequency is different according to individual cores. Do not set the bits to a divide ratio which is higher than maximum frequency. For the maximum operating frequency of each core, refer to “FR71E Core Series Lin-up Manual”.


- These bits are initialized to "0011" at a reset (INIT).- Readable and writable.

P3 P2 P1 P0 Clock divide ratio Clock frequency: Oscillation at 108 [MHz] and XINBY = 1

0 0 0 0 33 [MHz]

0 0 0 1 x 2 (Divide by 2) 16.5 [MHz]

0 0 1 0 x 3 (Divide by 3) 11 [MHz]

0 0 1 1 x 4 (Divide by 4) 8.25 [MHz] (Initial value)

0 1 0 0 x 5 (Divide by 5) 6.6 [MHz]

0 1 0 1 x 6 (Divide by 6) 5.5 [MHz]

... ... ... ... ... ...

1 1 1 1 x 16 (Divide by 16) 2.063 [MHz]

φ

φ

φ

φ

φ

φ

φ

φ


101

4.10.9.8 DIVR1: Base Clock Divide Ratio Setting Register 1

This register controls the frequency divide ratio for each type of internal clock signal relative to the base clock signal.The register sets the divide ratio for the external extended bus interface clock signal (CLKT).Each type of clock signal has the specified maximum operating frequency. If a combination of the source clock and divide ratio is set, which is higher than maximum frequency, the operation of the device is not guaranteed. (Take care not to use the wrong procedure to change the source clock selection setting).When the divide ratio setting in this register is changed, the new setting becomes effective at the next clock rate.

[Bits 7-4]: T3, T2, T1, T0 (clkT divide select 3-0)These bits are used to set the external bus interface clock (CLKT) frequency divide ratio.The clock frequency divide ratio set by these bits applies to the clock signal for the external bus interface.The combination of values written to these bits selects the divide ratio (clock frequency) for the external bus interface relative to the base clock signal, from the 16 types listed below.The maximum operating frequency is different according to individual cores. Do not set the bits to a divide ratio which is higher than maximum frequency. For the maximum operating frequency of each core, refer to “FR71E Core Series Lin-up Manual”.


- These bits are initialized to "0001" at a reset (INIT).- Readable and writable.

[Bits 3-0]: Reserved

- These bits are initialized to "0000" at a reset (INIT).- Be sure to set these bits to "0000" at writing.

Bit 7 6 5 4 3 2 1 0

address : 00000487h T3 T2 T1 T0 - - - -




T3 T2 T1 T0 Clock divide ratio Clock frequency: Oscillation at 108 [MHz] and XINBY = 1

0 0 0 0 33 [MHz]

0 0 0 1 x 2 (Divide by 2) 16.5 [MHz] (Initial value)

0 0 1 0 x 3 (Divide by 3) 11 [MHz]

0 0 1 1 x 4 (Divide by 4) 8.25 [MHz]

0 1 0 0 x 5 (Divide by 5) 6.6 [MHz]

0 1 0 1 x 6 (Divide by 6) 5.5 [MHz]

... ... ... ... ... ...

1 1 1 1 x 16 (Divide by 16) 2.063 [MHz]

φ

φ

φ

φ

φ

φ

φ

φ


102

4.10.10 Peripheral Circuits in the Clock Control UnitThis section describes peripheral circuits in the clock control unit.

4.10.10.1 Time-Base CounterThe clock control unit incorporates a 26-bit time-base counter operating with the system base clock signal.The time-base counter is used for measurement of the oscillation settling time (detailed in Section 4.9.5 "Oscillation settling time") and the following applications.

- Watchdog timerThe watchdog timer for detecting system runaway performs measurement using the bit output of the time-base counter.

- Time-base timerThe time-base timer generates an interval interrupt using the time-base counter output.

These functions are described below.

4.10.10.1.1 Watchdog TimerThe watchdog timer is a runaway detection timer using the time-base counter output. If a program runs out of controls, the watch dog reset defer function cannot be executed within the set interval, so the watchdog timer generates a setting initialization reset (INIT) request as a watchdog reset.

[Activating the watchdog timer and setting its time interval]The watchdog timer is activated upon the first writing to the RSRR (reset cause register and watchdog timer control register) after a reset (RST). At this time, the WT1 and WT0 bits (bits 09 and 08) are used to set the time interval for the watchdog timer. Only the time interval set at the first writing to the RSRR is effective; any further writing is ignored.

[Deferring the generation of a watchdog reset]Once the watchdog timer is activated, A5h and 5Ah must be written in this order, periodically to the WPR (watchdog reset defer register) by a program. This operation initializes the watchdog reset generation flag.

[Generating a watchdog reset]The watchdog reset generation flag is set at the falling edge of the time-base counter output during the set interval. If the flag has been set when the second falling edge is detected, a setting initialization reset (INIT) request is generated for a watchdog reset.

[Stopping the watchdog timer]Once the watchdog timer is activated, it cannot be stopped until an operation initialization reset (RST) occurs.In the following states in which an operation initialization reset (RST) occurs, the watchdog timer stops and will not function until it is programmed to be reactivated.

- Operation initialization reset (RST) state- Setting initialization reset (INIT) state- Oscillation stabilization wait reset (RST) state- Hardware standby state

[Suspending the watchdog timer (deferring automatic generation)]The watchdog timer initializes the watchdog reset generation flag to defer the generation of a watchdog reset when the CPU is suspending program operation. Put briefly, the CPU suspends program operation


103

in the following states:- Sleep state- Stop state- Oscillation stabilization wait RUN state- During DMA transfer to the I-bus (instruction bus) or D-bus (data bus)- During the break when emulator debugger and monitor debugger are used- The period to perform INTE instruction to RETI instruction- During data access to cache memory in RAM mode of instruction cache control register (ISIZE,

ICHR).Note that, when the time-base counter is cleared, the watchdog reset generation flag is also initialized at the same time, deferring the generation of a watchdog reset.If the situation stated as above is occurred by the system runaway, watchdog reset may not be generated. In this case, apply resert (INIT) by using external INITX pin.


104

4.10.10.1.2 Time-Base TimerThe time-base timer generates an interval interrupt using the time-base counter output. This timer is suitable for applications which involves time measurement for relatively long time up to the base clock signal x 2^27 cycle, such as the lock wait time of PLL which is connected with the macro externally, or subclock oscillation settling time.The time-base timer generates a time-base timer interrupt request upon detection of the falling edge of the time-base counter output which corresponds to the set interval.

[Activating the time-base timer and setting its time interval]The time interval for the time-base timer is set by the TBC2, TBC1, and TBC0 bits (bits 13-11) in the TBCR (time-base counter control register)Since the falling edge of the time-base counter output which corresponds to the set interval is always detected, clear the TBIF bit (bit 15) first after setting the time interval, and then set the TBIE bit (bit 14) to "1" to enable the interrupt request output.Before changing the time interval, set the TBIE bit (bit 14) to "0" to disable the interrupt request output.The time-base counter keeps counting without being affected by these settings. To obtain the accurate interval interrupt time, therefore, clear the time-base counter before enabling interrupts. Otherwise, an interrupt request may occur immediately after interrupts are enabled.

[Clearing the time-base counter using a program]When A5h and 5Ah are written in this order, to the CTBR (time-base counter clear register) continuously, all the bits in the time-base counter are cleared to "0" immediately after the 5Ah write. There is no restriction on the interval between A5h writing and 5Ah writing. If any data other than 5Ah is written following the A5h writing, however, A5h must be written again before 5Ah is written in order to clear the time-base counter.When the time-base counter is cleared in this way, the watchdog reset generation flag is initialized at the same time, temporarily deferring the generation of a watchdog reset.

[Clearing the time-base counter by core macro state]All the bits in the time-base counter are cleared to "0" when the core macro causes a transition to the following states:

- Stop state- Setting initialization reset (INIT) state- Hardware standby state

When the core macro enters the stop state, in particular, the time-base timer may cause an unintentional interval interrupt as the time-base counter is used for measurement of oscillation setting time. Before setting to the stop mode, therefore, disable time-base timer interrupts and stop using the time-base timer.When the core macro enters any other state, an operation initialization reset (RST) occurs and thus time-base timer interrupts are disabled automatically.


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4.10.11 クロックの滑らかな起動と停止内部電圧効果または電圧サージを抑制するための方法を説明します。

4.10.11.1 クロックの滑らかな起動と停止内部電圧効果または電圧サージを抑制するために C端子に 5.0mF程度のパスコンを接続すると内部電圧変化が大幅に抑制されます。また ,すべてのクロック (CPUおよび内部バスクロック (CLKB),外部バスクロック (CLKT),周辺回路およびペリフェラルバスクロック (CLKP))を ,低周波数から目標とする周波数にいきなり切り替えるのではなく ,段階的に切り替えてください。低周波数での動作に戻す場合も段階的に行って ,以下のようなクロックの起動とシャットダウンを行ってください。高周波数での動作から低周波数での動作に切り替える場合も ,同様の方法で行います。

4.10.11.1.1 起動1)PLL動作許可 (クロックソース制御レジスタ (CLKR)の PLL1ENビットを "1"に設定してください。)

2)発振安定待ち時間

3)CLKB,CLKT,CLKPを 16分周します。(DIVR0,DIVR1レジスタを設定してください。)

4)PLLの逓倍率を設定し ,X0を PLL側に切り替えます。(クロックソース制御レジスタ (CLKR)を設定してください。)

5)CLKB,CLKT,CLKPの分周比を段階的に下げます。分周ステップの間に待機ループを挿入します。

4.10.11.1.2 シャットダウン1)CLKB,CLKT,CLKPを段階的 (ステップ数は周波数の設定による )に最大分周係数まで分周し ,分周ステップの間に待機ループを挿入します。(DIVR0,DIVR1レジスタを設定してください。)

2)PLLから X0/X1よりの原発振に切り替えます。(クロックソース制御レジスタ (CLKR)を設定してください。)

3)PLLを無効にします。(クロックソース制御レジスタ (CLKR)の PLL1ENビットを "0"に設定してください。)

4.10.11.2 クロックの滑らかな起動と停止のプログラム例

4.10.11.2.1 起動手順#macro wait_loop loop_number

#local _wait64_loop

ldi #loop_number,r0

_wait64_loop:

add #-1,r0

bne _wait64_loop

#endm

smooth_up_start3:

ldi #_DIVR0,r1// CLKBおよび CLKP用の分周レジスタ


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ldi #_DIVR1,r2// CLKT用の分周レジスタ

ldi #_CLKR,r3// CLKR レジスタ

ldi #0xff,r4

ldi #0x11,r5

ldi #0x33,r6

ldi #0x77,r7

ldi #0x01,r8

ldi #0x34,r12

ldi #0x36,r13

nop

nop

nop

stb r12,@r3// PLL → X0 PLL動作許可

//CLKB,CLKT,CLKPを 16分周します

stb r4,@r1// CLKB , CLKP 16分周

stb r4,@r2// CLKT 16分周

wait_loop 4

stb r13,@r3//X0を PLL側に切り替えます °

wait_loop 4

//CLKB,CLKPの分周比を段階的に下げます。

stb r7,@r1// CLKB , CLKP 16分周→ 8分周

wait_loop 8


wait_loop 8


wait_loop 16

stb r8,@r1// CLKB 2分周→分周なし ,CLKP2分周→ 2分周

wait_loop 16

//CLKTの分周比を段階的に下げます。

stb r7,@r2// CLKT 16分周→ 8分周

wait_loop 8


wait_loop 8


wait_loop 16

stb r8,@r2// CLKT 分周なし

wait_loop 16


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4.10.11.2.2 シャットダウン手順#macro wait_loop loop_number

#local _wait64_loop

ldi #loop_number,r0

_wait64_loop:

add #-1,r0

bne _wait64_loop

#endm

smooth_down_start3:

ldi #_DIVR0,r1// CLKBおよび CLKP用の分周レジスタ

ldi #_DIVR1,r2// CLKT用の分周レジスタ

ldi #_CLKR,r3// CLKR レジスタ

ldi #0x11,r5

ldi #0x3f,r6

ldi #0xff,r8

ldi #0x04,r9

ldi #0x33,r10

ldi #0xff,r12

ldi #0x00,r13

ldi #0x1f,r14

nop

nop

nop

//CLKTの分周比を段階的に上げます。

stb r14,@r2// CLKT　分周なし→ 2分周

wait_loop 16

stb r6,@r2// CLKT 　2分周→ 4分周

wait_loop 8

stb r8,@r2// CLKT 　4分周→ 16分周

wait_loop 4

//CLKB,CLKPの分周比を段階的に上げます。

stb r5,@r1// CLKB 分周なし→ 2分周 , CLKP 2分周→ 2分周

wait_loop 16

stb r10,@r1// CLKB ,CLKP　2分周→ 4分周

wait_loop 8

stb r12,@r1// CLKB ,CLKP　4分周→ 16分周

wait_loop 4


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//PLLの逓倍率を段階的に下げます。

stb r9,@r3// PLL から X0/X1よりの原発振に切り替えます。

stb r13,@r3// PLL off

nop

nop

nop

ret


109

4.11 Core Macro Status ControlThis section describes each status of the FR71 family core macro and its control.

4.11.1 Core Macro States and Transition Trigger EventsThe FR71 family core macro has the following operating states.

4.11.1.1 RUN State (Normal Operation State)This state is the program execution state.All internal clock signals are supplied and all circuits can operate.However, note that the peripheral resource bus will stop the bus clock when no access is being performed.Although each state transition request is acceptable, the state transition to the normal reset mode or in response to a certain request is different when the synchronous reset mode has been selected. For details, see Section 4.9.6.2 Synchronous reset operation.

4.11.1.2 Sleep StateThis state is the program idle state. The core macro enters the state by program operation.Only the CPU stops program execution while peripheral circuits can operate. The instruction cache is off and various built-in memory modules and internal/external busses remain idle until requested by the DMA controller.When a valid interrupt request occurs, the core macro is released from this state and enters the RUN state (normal operation state )When a setting initialization reset (INIT) request occurs, the core macro enters the setting initialization reset (INIT) state.When an operation initialization reset (RST) request occurs, the core macro enters the operation initialization reset (RST) state.When a hardware standby request occurs, the core macro enters the hardware standby state.

4.11.1.3 Stop StateThis state is a core macro idle state. The core macro enters the state by program operation.All internal circuit operations and all internal clock signals are stopped. The oscillator stop instruction can be enabled by using the settings.Output-enabled external pins (excluding some pins) can be disabled by the settings. When a specific (clock-free) effective interrupt request occurs, the core macro enters the oscillation stabilization wait RUN state.When a setting initialization reset (INIT) request occurs, the core macro enters the setting initialization reset (INIT) state.When an operation initialization reset (RST) request occurs, the core macro enters the oscillation stabilization wait reset (RST) state.When a hardware standby request occurs, the core macro enters the hardware standby state

4.11.1.4 Hardware Standby StateThis state is a core macro idle state. The core macro enters the state in response to low-level input to the HSTXI or LINITXI pin (hardware standby request).All internal circuit operations and all internal clock signals are stopped. And the oscillator stop instruction is enabled.The setting initialization reset (INIT) is supplied to the internal circuits.Output-enabled external pins are output-disabled (excluding some pins).Either high-level input to the HSTXI or LINITXI pin or low-level input to the INITXI pin causes the core macro to enter the setting initialization reset (INIT) state.


110

4.11.1.5 Oscillation Stabilization Wait RUN StateThis state is a core macro idle state. The core macro enters the state when returning from the stop state.All internal circuit operations are stopped, excluding the clock generation control unit (time-base counter and core macro status control unit). Although all internal clock signals are stopped, the oscillator stop instruction cannot be enabled.This state cancels high-impedance control applied to external pins in the stop state.The core macro enters the RUN state (normal operation state) as the set oscillation settling time has passed.When a setting initialization reset (INIT) request occurs, the core macro enters the setting initialization reset (INIT) state.When an operation initialization reset (RST) request occurs, the core macro enters the oscillation stabilization wait reset (RST) state.When a hardware standby request occurs, the core macro enters the hardware standby state.

4.11.1.6 Oscillation Stabilization Wait Reset (RST) StateThis state is a core macro idle state. The core macro enters the state when returning from the setting initialization reset (INIT) state.All internal circuit operations are stopped, excluding the clock generation control unit (time-base counter and core macro status control unit). Although all internal clock signals are stopped, the oscillator is enabled for operation.This state cancels high-impedance control applied to external pins in the stop state.An operation initialization reset (RST) is output to internal circuits.The core macro enters the oscillation stabilization wait reset (RST) state as the set oscillation settling time has passed.When a setting initialization reset (INIT) request occurs, the core macro enters the setting initialization reset (INIT) state.When a hardware standby request occurs, the core macro enters the hardware standby state.

4.11.1.7 Operation Initialization Reset (RST) StateThis state is the program initialized state. The core macro enters the state either on receipt of an operation initialization reset (RST) request or upon termination of the oscillation stabilization wait reset (RST) state.The CPU stops program execution and the program counter is initialized. Most of the peripheral circuits are initialized. All internal clocks and oscillator are enabled for operation.An operation initialization reset (RST) is output to internal circuits.When the operation initialization reset (RST) request is eliminated, the core macro enters the RUN state (normal operation state) and executes the operation initialization reset sequence. When returning from the setting initialization reset (INIT) state, the core macro executes the setting initialization reset sequence.When a setting initialization reset (INIT) request occurs, the core macro enters the setting initialization reset (INIT) state.When a hardware standby request occurs, the core macro enters the hardware standby state.


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4.11.1.8 Setting Initialization Reset (INIT) StateIn this state, all settings are initialized. The core macro enters the state either on receipt of a setting initialization reset (INIT) request or upon termination of the hardware standby state.The CPU stops program execution and the program counter is initialized. All peripheral circuits are initialized and the oscillator is operated. While INITXI pin maintains low-level input, all internal clocks are stopped. Otherwise, all internal clocks are operated.A setting initialization reset (INIT) and an operation initialization reset (RST) are output to internal circuits.When the initialization reset (INIT) request is eliminated, the core macro is released from this state and enters the oscillation stabilization wait reset (RST) state. The core macro then enters the operation initialization reset (RST) state and executes the setting initialization reset sequence.

4.11.1.9 Priorities of State Transition RequestsState transition requests follow their priorities given as follows irrespective of the current state. Note that some requests are generated only under specific conditions; they are effective only under such conditions.

[Highest] Setting initialization reset (INIT) requestHardware standby requestEnd of stabilization settling time (Occurs only in the oscillation stabilization wait reset or oscillation stabilization wait Run state.)Operation initialization reset (RST) requestEffective interrupt request (Occurs only in the RUN, sleep, or stop state.)Stop mode request (register write) (Occurs only in the RUN state.)

[Lowest] Sleep mode request (register write) (Occurs only in the RUN state.)


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4.11.2 Low Power Consumption ModesThis section describes the individual low power consumption modes in FR71 family core macro states and explains how to use such modes.The low power consumption modes for the FR71 family are as follows:

- Sleep modeThe core macro enters the sleep state in response to a register writing.

- Stop modeThe core macro enters the stop state in response to a register writing.

- Hardware standby modeThe core macro enters the hardware standby state in response to low-level input to the external HSTX pin.

- Undervoltage detection standby modeThe core macro enters the hardware standby state in response to low-level input to the external LINITX pin.

Each of these modes is detailed below.

4.11.2.1 Sleep ModeWriting "1" to the SLEEP bit (bit 6) in the STCR (standby control register) establishes the sleep mode and causes the core macro to enter the sleep state. The core macro remains in the sleep state until a sleep-state return cause (an event that triggers the macro to return from the sleep state) is generated.If "1" is written to both of this bit and the STOP bit (bit 7) in the STCR (standby control register), the STOP bit (bit 7) overrides the other, causing the transition to the stop state.For details on the sleep state, see Section 4.11.1.2 "Sleep state".

[Transition to the sleep mode]In sleep mode, the following sequences must be used after using the synchronous standby mode (set by bit8 SYNCS bit of TBCR: time base counter control register).

(LDI #value_of_sleep,R0) ; Value_of_sleep is the data which is written to STCR. (LDI #_STCR,R12) ; _STCR is the address of STCR (481H)STB R0,@R12 ; Writing to standby control register (STCR) LDUB @R12,R0 ; STCR read for synchronous standby LDUB @R12,R0 ; Dummy read STCR againNOPNOPNOPNOPNOP

After the standby is returned, set I flag, ILM, and ICR in order to branch to the interrupt handler (return factor).

[Circuits which stop in the sleep state]- CPU program execution- Instruction cache- Bit search module (Operates when DMA transfer occurs.)- Built-in memory modules (Operate when DMA transfer occurs.)- Internal/external buses (Operate when DMA transfer occurs.)


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[Circuits which do not stop in the sleep state]

- Clock generation control unit- Interrupt controller- Peripheral resources- DMA controller- DSU

[Sleep-state return sources]- Occurrence of a effective interrupt request

When a request for an interrupt whose level is higher than the interrupt level set by the ILM register in the CPU occurs, the sleep mode is canceled and the core macro enters the RUN state (normal operation state). In this case, set the I flag of the processor status register (PS) in CPU to “1” and enable the interrupt acceptance, then perform the interrupt handler after the sleep state is returned.The sleep mode is not canceled even when an interrupt request occurs, which interrupt level is lower than the setting in the ILM in the CPU.

- Occurrence of a setting initialization reset (INIT) requestWhen a setting initialization reset (INIT) request occurs, the core macro enters the setting initialization reset (INIT) state unconditionally.

- Occurrence of a hardware standby request

When a hardware standby request occurs, the core macro enters the hardware standby state unconditionally.

- Occurrence of an operation initialization reset (RST) requestWhen an operation initialization reset (RST) request occurs, the core macro enters the operation initialization reset (RST) state unconditionally.

*: For the priority of each type of request, see Section 4.11.1.9 "Priorities of state transition requests".

[Synchronous standby operations]

When the SYNCS bit (bit 8) in the TBCR (time-base counter control register) is set to "1", the synchronous standby operation is enabled. In this case, the core macro does not enter the sleep state only by writing to the SLEEP bit. After that it enters the sleep state by reading the STCR register.To use sleep mode, the sequence in [Transition to the sleep mode] must be used.


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4.11.2.2 Stop ModeWriting "1" to the STOP bit (bit 7) in the STCR (standby control register) establishes the stop mode, causing the transition to the stop state. The core macro remains in the stop state until a stop-state return cause (an event that triggers the macro to return from the stop state) is generated.If "1" is written to both of the STOP bit (bit 7) and SLEEP bit (bit 6) in the STCR (standby control register), the STOP bit (bit 7) overrides the other, causing the transition to the stop state.For details on the stop state, see Section 4.11.1.3 "Stop state".

[Transition to the stop mode]In stop mode, the following sequences must be used after using the synchronous standby mode (set by bit8 SYNCS bit of TBCR: time base counter control register).

(LDI #value_of_stop,R0) ; Value_of_stop is the data which is written to STCR. (LDI #_STCR,R12) ; _STCR is the address of STCR (481H)STB R0,@R12 ; Writing to standby control register (STCR) LDUB @R12,R0 ; STCR read for synchronous standby LDUB @R12,R0 ; Dummy read STCR againNOPNOPNOPNOPNOP

After the standby is returned, set I flag, ILM, and ICR in order to branch to the interrupt handler (return factor).

[Circuits which stop in the stop state]- All internal circuits.

[Circuit which does not stop in the stop state]- None.

[High-impedance control of pins in the stop state]Setting the HIZ bit (bit 5) in the STCR (standby control register) to "1" output-disables some pin outputs in the stop state. For the target pins for this control, see Section 7.3 "Pin Status in Each CPU State".Setting the HIZ bit (bit 5) in the STCR (standby control register) to "0", the pin outputs in the stop state stores the value as before the transition to this state. For the target pins for this control, see Section 7.3 "Pin Status in Each CPU State".


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[Stop-state return causes]

- Occurrence of a specific (clock-free) effective interrupt requestOnly the external interrupt input pin is effective.When a request for an interrupt whose level is higher than the interrupt level set by the ILM register in the CPU occurs, the stop mode is canceled and the core macro enters the RUN state (normal operation state). In this case, set the I flag of the processor status register (PS) in CPU to “1” and enable the interrupt acceptance, then perform the interrupt handler after the sleep state is returned.The stop mode is not canceled even when an interrupt request occurs, whose interrupt level is lower than the setting in the ILM in the CPU.

- Occurrence of a setting initialization reset (INIT) requestWhen a setting initialization reset (INIT) request occurs, the core macro enters the setting initialization reset (INIT) state unconditionally.

- Occurrence of a hardware standby requestWhen a hardware standby request occurs, the core macro enters the hardware standby state unconditionally.

- Occurrence of an operation initialization reset (RST) requestWhen an operation initialization reset (RST) request occurs, the core macro enters the operation initialization reset (RST) state unconditionally.


[Synchronous standby operations]

When the SYNCS bit (bit 8) in the TBCR (time-base counter control register) is set to "1", the synchronous standby operation is enabled. In this case, the core macro does not enter the stop state only by writing to the STOP bit. It enters the stop state by reading the STCR register after writing to the STOP bit.To use stop mode, the sequence in [Transition to the stop mode] must be used.


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4.11.2.3 Hardware Standby ModeLow-level input to the external HSTX pin generates a hardware standby request, causing the transition to the hardware standby state. The core macro remains in the hardware standby state as long as the low-level input lasts.For details on the hardware standby state, see Section 4.11.1.4 "Hardware standby state".

[Circuits which stop in the hardware standby state]- All internal circuits

[Circuits which do not stop in the hardware standby state]- None

[High-impedance control of pins in the hardware standby state]In the hardware standby, pin outputs are put in the high impedance state. For the target pins for this control, see Section 7.3 "Pin Status in Each CPU State".

[Hardware-standby-state return causes]- High-level input to the HSTXI or LINITXI pin

When the hardware standby request is eliminated, the core macro enters the setting initialization reset (INIT) state.

- Low-level input to the INITXI pin, causing a setting initialization reset (INIT)When a setting initialization reset (INIT) via the INITXI pin occurs, the core macro enters the setting initialization reset (INIT) state unconditionally. A setting initialization reset (INIT) owing to any other cause does not occur in the hardware standby state.


[Asynchronous reset and synchronous reset operations]When the SYNCR bit (bit 9) in the TBCR (time-base counter control register) is set to "1", the synchronous reset operation is enabled. In this case, the core macro does not enter the hardware standby state as long as internal bus access is being processed even when a hardware standby request has been received.For details, see Section 4.9.6.2 Synchronous reset operation.When the SYNCR bit is set to "0", the core macro performs asynchronous reset operation. It enters the hardware standby state upon receipt of a hardware standby request, regardless of the service status of internal bus access.For details, see Section 4.9.6.1 "Asynchronous reset operation".

4.11.2.4 Undervoltage Detection Standby ModeLow-level input to the LINITXI pin generates an undervoltage detection standby request, causing the transition to the hardware standby state. The core macro remains in the hardware standby state as long as the low-level input lasts.For details on the hardware standby state, see Section 4.11.1.4 "Hardware standby state".The operations in the undervoltage detection standby mode are same as the hardware standby mode. See Section 4.11.2.3 "Hardware standby mode".


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CHAPTER 5 MEMORY INTERFACE

5.1 Bus InterfaceThe external bus interface controller controls the interface between the internal bus in the core and external memory plus external I/O devices.This chapter describes the functions of the external bus interface.

5.1.1 Features- Up to 32-bit (4-gigabyte space) address output

- Directly connecting to various types of external memory modules (8-bit/16-bit/32-bit products) and controlling a mixture of different access timings

Asynchronous SRAM or asynchronous ROM/flash memory (Multiple write strobe type or byte enable type)Page mode ROM/flash memory (Page sizes of 2/4/8 acceptable)Burst mode ROM/flash memory (MBM29BL160D/161D/162D, etc.)SDRAM (FCRAM type is also supported, CAS-Latency 1~8, 2 banks and 4 banks products)Address/data multiplex bus (8-bit/16-bit width only)Synchronous memory (ASIC integrated memory, etc.)

*: Synchronous SRAM cannot be connected directly.

- Allowing eight independent banks (chip select areas) to be set with their respective chip select outputs

Capable of setting the size of each chip select area in 64 kilobytes (from 64 KB to 2 GB per chip select area)Capable of allocating each area at an arbitrary location in the logical address space (with boundary restrictions by area size)

- Capable of setting the following functions for each chip select area

Enabling/disabling the chip select area (Disabled areas are not accessed.)Access timing type setting by memory typeDetailed access timing setting (individual access type setting such as the wait cycle)Data bus width setting (8/16/32 bits)Byte-ordering endian setting (bit or little endian)*: The CS0X area allows big endian only.Setting for writing prohibited (read only area)Enabling/disabling fetching to the built-in cacheEnabling/disabling the prefetch functionMaximum burst length setting (1, 2, 4, 8)

- Capable of detailed timing setting for each access timing type

Allowing a mixture of different timings to be set for the same type of individual chip select areas Programmable automatic wait insertion for up to 15 cycles (Asynchronous SRAM, ROM, flash memory, I/O area)Capable of extending the bus cycle using the external RDY input (Asynchronous SRAM, ROM, flash memory, I/O area)Fast access wait and page wait setting (Burst mode/page mode ROM/flash areas)Programmable insertion of various idle/recovery cycles and setup delayCapable of setting CAS-Latency, RAS-CAS delay and other timings (SDRAM area)Capable of controlling various refresh timings such as dispersion/concentration auto fresh, self fresh (SDRAM area)


114

- Fly-by transfer by DMA

Transfer by a single memory-I/O accessCapable of synchronizing the memory wait cycle with the I/O wait cycle during fly-by transferCapable of extending only the transfer source access to keep the hold time

Capable of setting a unique idle/recovery cycle for fly-by transfer

- External bus arbitration using BRQ and BGRNTX


115

5.2 Block Diagram

ADDRESS BLOCK

DATA BLOCK

+1 or +2

switch

switch

32 32

DATA BUS

BRQ BGRNTX RDY SYSCLK MCLKO MCLKI

ASX,BAAX RDX,WEX WRX[3:0]

CSX[0]-CSX[7]

EXTERNALADDRESS BUS

EXTERNALDATA BUS

MUX

A-OUT

write bus

ADRESS BUS

resisters &

control

External pin control section

comparator

ACR

ASR

address buffer

read buffer

SRASX,SCASX, SWEX,MCLKE, DQMUU,DQMUL, DQMLU,DQMLL

refresh counter

underflow RCR

SDRAM control section

* The pin which is outputted from SDRAM control section, is shared with the pin which is outputted from external pin control section.

All-block control


116

5.3 Register List

Address 31 24 23 16 15 08 07 00

Reserved: Registers reserved and access prohibited.MODR cannot be accessed from user program.

00000640H ASR0 ACR0

00000644H ASR1 ACR1

00000648H ASR2 ASR2

0000064cH ASR3 ACR3

00000650H ASR4 ACR4

00000654H ASR5 ACR5

00000658H ASR6 ACR6

0000065cH ASR7 ACR7

00000660H AWR0 AWR1

00000664H AWR2 AWR3

00000668H AWR4 AWR5

0000066cH AWR6 AWR7

00000670H MCRA MCRB Reserved Reserved

00000674H Reserved Reserved Reserved Reserved

00000678H IOWR0 IOWR1 IOWR2 Reserved

0000067cH Reserved Reserved Reserved Reserved

00000680H CSER CHER Reserved TCR

00000684H RCR Reserved Reserved

00000688H

Reserved|

000007f8H

000007fcH Reserved (MODR) Reserved Reserved


117

5.4 Register Description

5.4.1 ASR0 to ASR7 (Area Select Registers)

Area select registers 0 to 7 (ASR0 to ASR7) specify the start addresses of chip select areas of CS0X to CS7X.The start address can set the upper 16 bits (A[31:16]). The chip select area starts at the address set in theregister and specify the range set by the ASZ[3:0] bits in the ACR0-ACR7 register.The boundary of each chip select area follows the setting of the ASZ[3:0] bits in the ACR0-ACR7 register.When the ASZ[3:0] bits specify an area size of one megabyte, the lower four bits in the ASR0-ASR7 registerare ignored, with only the A[31:20] bits are significant.The ASR0 register is initialized to 0000H at INIT or RST. The ASR1 to ASR7 registers are not initialized butbecome undefined at INIT or RST.Before enabling each chip select area using the CSER register, be sure to set the corresponding ASR register.

ASR0 Initial value

15 14 13 12 ... 2 1 0 At INIT At RST Access

0000 0640 H A31 A30 A29 … … A18 A17 A16 0000 H 0000 H W/R

ASR1

15 14 13 12 … 2 1 0

0000 0644 H A31 A30 A29 … … A18 A17 A16 xxxx H xxxx H W/R

ASR2

15 14 13 12 ... 2 1 0


ASR3

15 14 13 12 ... 2 1 0

0000 064C H A31 A30 A29 … … A18 A17 A16 xxxx H xxxx H W/R

ASR4

15 14 13 12 ... 2 1 0


ASR5

15 14 13 12 ... 2 1 0


ASR6

15 14 13 12 ... 2 1 0


ASR7

15 14 13 12 ... 2 1 0

0000 065C H A31 A30 A29 … … A18 A17 A16 xxxx H xxxx H W/R


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5.4.2 ACR0 to ACR7 (Area Configuration Registers)

ACR0HInitial value Access

15 14 13 12 11 10 9 8 At INIT At RST

0000 0642 H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 1111**00 b 1111**00 b W/R

ACR0L

7 6 5 4 3 2 1 0

0000 0643 H SREN PFEN WREN 0 TYP3 TYP2 TYP1 TYP0 00000000 b 00000000 b W/R

ACR1H

15 14 13 12 11 10 9 8

0000 0646 H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx b xxxxxxxx b W/R

ACR1L

7 6 5 4 3 2 1 0

0000 0647 H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx b xxxxxxxx b W/R

ACR2H

15 14 13 12 11 10 9 8

0000 064A H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx b xxxxxxxx b W/R

ACR2L

7 6 5 4 3 2 1 0

0000 064B H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx b xxxxxxxx b W/R

ACR3H

15 14 13 12 11 10 9 8

0000 064E H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx b xxxxxxxx b W/R

ACR3L

7 6 5 4 3 2 1 0

0000 064F H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx b xxxxxxxx b W/R


119

Area configuration registers 0 to 7 (ACR0 to ACR7) specify the functions of their respective chip select areas.

ACR4H

15 14 13 12 11 10 9 8


ACR4L

7 6 5 4 3 2 1 0


ACR5H

15 14 13 12 11 10 9 8


ACR5L

7 6 5 4 3 2 1 0


ACR6H

15 14 13 12 11 10 9 8

0000 065A H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx b xxxxxxxx b W/R

ACR6L

7 6 5 4 3 2 1 0

0000 065B H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx b xxxxxxxx b W/R

ACR7H

15 14 13 12 11 10 9 8

0000 065E H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxx b xxxxxxxx b W/R

ACR7L

7 6 5 4 3 2 1 0

0000 065F H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxx b xxxxxxxx b W/R


120

[Bits 15-12] ASZ3-ASZ0 = Area Size Bits 3-0

These bits set the size of each chip select area as shown below.

The ASZ[3:0] bits specify the size of the corresponding chip select area by changing the number of bits address-compared with the ASR. Thus the ASR contains bits which are not compared.

The ASZ[3:0] bits in the ACR0 register are initialized to 1111B (0FH) at RST. Regardless of this setting, the CS0 area immediately after RST is specially set to the range from 00000000H to FFFFFFFFH (the entire area). This is a temporary state for fetching the reset vector and initial program. By the first writing to the ACR0 register, the entire-area setting is canceled and the CS0 area is set to the size as specified in the above table.

In the early stage of initial program, all settings of CS0 area (include ACR0) must be performed. Maintaining the initial state, the CS0 area is not disabled even if setting bit 0:CSE0 in CSER register to “0”. And the writing to CS0 area is not masked even if setting bit 5:WREN in ACR0 register to “0”.

If SDRAM/FCRAM is connected to the area that is set by ASR6, ASR7, set 128 Mbytes (1011H) or less respectively.

[Bits 11-10] DBW1-DBW0 = Data Bus Width 1-0

These bits specify the data bus width of the corresponding chip select area as shown below.

For DBW-1 bit of ACR0, a value same as WTH bit of mode vector is written in the reset sequence.In the area which SDRAM/FCRAM is connected, set all the data bus width setting in the same way by using these bits.

ASZ3 ASZ2 ASZ1 ASZ0 Chip select area size

0 0 0 0 64K bytes (00010000h bytes, ASR A[31:16] bits effective)




0 1 0 0 1M bytes (00100000h bytes, ASR A[31:20] bits effective)










1 1 1 0 1024M bytes (40000000h byte, ASR A[31:30] bits effective)

1 1 1 1 2048M bytes (80000000h byte, ASR A[31] bits effective)

DBW1 DBW0 Data bus width

0 0 8 bits (Byte access)

0 1 16 bits (Halfword access)

1 0 32 bits (Word access)

1 1 Reserved (Setting prohibited)


121

[Bits 9-8] BST1-BST0 = Burst Size 1-0

These bits specify the burst length of the corresponding chip select area as shown below.

If a burst length other than "single access" is set for a chip select area, the area allows continuous burst access within the address boundary determined by the burst length only when prefetch access or a data reading which size exceeds the bus width is performed.

- The maximum burst length for an area with a bus width of 32 bits must not exceed four bursts. It is recommended to set it to two bursts or less.

- The maximum burst length for an area with a bus width of 16 bits is recommended to be two bursts or less.

The areas which a burst length other than "single access" has been set, ignores RDY inputs.In the area which SDRAM/FCRAM is connected, set all the burst length setting in the same way by using these bits.

[Bit 7] SREN = ShaRed ENable

This bit enables or disables sharing the corresponding chip select area by BRQ and BGRNTX.

*1: CSXC[x] is not set to 1 (output disabled).*2: CSXC[x] is set to 1 (output disabled).

For the sharing-enabled area, CSXC[x] has the "H" level with the bus released (BGRNTX = Low-level output).For the sharing-disabled area, CSXC[x] does not have the "H" level even with the bus released (BGRNTX = Low-level output).The output enable pins (RDXC, WRXC) of the access strobe outputs (RDX, WRX[3:0], WEX ) have the "H" level only when all the areas enabled by the CSER register have been sharing-enabled.

BST1 BST0 Maximum burst length

0 0 1 (Single access)

0 1 2 bursts

1 0 4 bursts

1 1 8 bursts

SREN Sharing enable/disable status

0 Disable sharing by BRQ/BGRNTX (without placing CSX in Hi-Z state *1).

1 Enable sharing by BRQ/BGRNTX (while placing CSX in Hi-Z state *2 ).


122

[Bit 6] PFEN = PreFetch ENable

This bit enables or disables prefetching the corresponding chip select area as shown below.

When a prefetch-enabled area is read, the following address is prefetched and stored in the built-in prefetch buffer. When the internal bus accesses the stored address, the device returns the data read ahead to the prefetch buffer without performing external access.For details of prefetch, see Section 5.7.3 "Prefetch".

[Bit 5] WREN = WRite ENableThis bit enables or disables writing to the corresponding chip select area.

An write-access to a write-disabled area, even though generated by the internal bus, is ignored without causing any external access.For an area to be updated, such as a data area, set the WREN bit to "1".

[Bit 4] LEND = Little ENDian selectThis bit selects the type of byte ordering for the corresponding chip select area.

The LEND bit in the ACR0 register is always set to "0" to select the big endian method.

PFEN Prefetch enable/disable status

0 Disable prefetch

1 Enable prefetch

WREN Write enable/disable status

0 Enable writing

1 Disable writing

LEND Byte ordering

0 Big Endian

1 Little Endian


123

[Bits 3-0] TYP3, TYP2, TYP1, TYP0 = TYPe select

These bits specify the access type of the corresponding chip select area.

These bits are used as a combination. It is prohibited to set the TYP3 bit to "1". Always set it to "0". Setting it to "1" yields unpredictable results.

*1: Selecting this setting allows the WRX[3:0] pins to use as byte enable pins.*2: Only ACR6, ACR7 registers are valid. Settings in ACR0, ACR1, ACR2, ACR3, ACR4, ACR5 registers

are prohibited.*3: CS area mask setting function

In a CS area (hereafter called base setting area), to define a area that some operation setting has been changed, set ACR:TYPE[3:0]=1111 with setting of another CS area, then the area can be used as mask setting area.When mask setting function is not used, overlap area setting by two or more CS area is prohibited.Access to mask setting area performs the following operations:

-CSX corresponding to mask setting area is not asserted.-CSX corresponding to base setting area is asserted.-The following ACR setting is valid on mask setting area side.

bit[11:10] DBW[1:0]: bus width settingbit[9:8] BST[1:0]: burst length settingbit[7] SREN: common enable settingbit[6] PFEN: prefetch enable settingbit[5] WREN: writing enable setting (for this setting only, setting differs from base setting area is

prohibited.)bit[4] LEND: little endian setting

-The following ACR setting is valid on base setting area side.bit[3:0] TYPE[3:0]: access type setting

- AWR setting is valid on mask setting area side.- CHER setting is valid on mask setting area side.

TYP3 TYP2 TYP1 TYP0 Access type

0 0 x x Normal access (SRAM, I/O, single/page/burst-ROM/flash)

1 x x Address data multiplex access (Bus width limited to 8 or 16 bits)

x x 0 Wait insertion by RDY pin is invalid.

x 1 Wait insertion by RDY pin is valid (invalid in burst mode).

0 x WRX[3:0] pins are used as write-strobe (with WEX fixed at "H" level)

1 x WEX pin is used as write-strobe. *1

1 0 0 0 Memory type A: SDRAM/FCRAM (not used by auto precharge)*2

1 Memory type B: FCRAM (used by auto precharge)*2

0 1 0 Setting prohibited





1 1 1 Mask area setting (access type: access the overlapped area)*3


124

Mask setting area can only set the limited area in other CS areas (base setting area). Mask setting area cannot be set in the area which have no base setting area. In addition, mask setting area cannot be even addressed. Pay attention to the setting of ASR and ACR:ASZ[3:0] bit.

Note: Writing enable setting cannot be executed by mask.Set writing enable setting, base CS area and mask setting area in the same way.If mask setting area is set to be writing disabled, this area operates as base CS area without masking.If base CS area is set to be writing disabled and mask setting area is set to be writing enabled, this area becomes the area which has no base setting area, and malfunction occurs.


125

5.4.3 AWR0 to AWR7 (Area Wait Registers)

Initial value Access

AWR0H 31 30 29 28 27 26 25 24 At INIT At RST

0000 0660 H W15 W14 W13 W12 W11 W10 W09 W08 01111111 b 01111111 b W/R

AWR0L 23 22 21 20 19 18 17 16

0000 0661 H W07 W06 W05 W04 W03 W02 W01 W00 11111111 b 11111011 b W/R

AWR1H 15 14 13 12 11 10 9 8

0000 0662 H W15 W14 W13 W12 W11 W10 W09 W08 xxxxxxxx b xxxxxxxx b W/R

AWR1L 7 6 5 4 3 2 1 0


AWR2H 31 30 29 28 27 26 25 24


AWR2L 23 22 21 20 19 18 17 16


AWR3H 15 14 13 12 11 10 9 8


AWR3L 7 6 5 4 3 2 1 0


AWR4H 31 30 29 28 27 26 25 24


AWR4L 23 22 21 20 19 18 17 16


AWR5H 15 14 13 12 11 10 9 8

0000 066A H W15 W14 W13 W12 W11 W10 W09 W08 xxxxxxxx b xxxxxxxx b W/R

AWR5L 7 6 5 4 3 2 1 0

0000 066B H W07 W06 W05 W04 W03 W02 W01 W00 xxxxxxxx b xxxxxxxx b W/R


126

The AWR0 to AWR7 registers specify various wait timings for their respective chip select areas.Since the initial values in these registers, except AWR0, are undefined, set them before enabling each chipselect area using the CSER register.


AWR6H 31 30 29 28 27 26 25 24 At INIT At RST

0000 066C H W15 W14 W13 W12 W11 W10 W09 W08 xxxxxxxx b xxxxxxxx b W/R

AWR6L 23 22 21 20 19 18 17 16

0000 066D H W07 W06 W05 W04 W03 W02 W01 W00 xxxxxxxx b xxxxxxxx b W/R

AWR7H 15 14 13 12 11 10 9 8

0000 066E H W15 W14 W13 W12 W11 W10 W09 W08 xxxxxxxx b xxxxxxxx b W/R

AWR7L 7 6 5 4 3 2 1 0

0000 066F H W07 W06 W05 W04 W03 W02 W01 W00 xxxxxxxx b xxxxxxxx b W/R


127

5.4.3.1 Normal AccessThe chip select area that performed the following setting to the access type (TYP[3:0]bit) of ACR0~7 registers,becomes the area that performs the normal access operation.

The function of each bit in AWR0~7 registers for normal access or address/data multiplex access area areshown below.Since the initial values in these registers, except AWR0, are undefined, set them before enabling each chipselect area using the CSER register.

[Bits 15-12] W15-W12 = First Access Wait CyclesThese bits set the number of automatic wait cycles for the first data fetch in each cycle. Only this waitsetting is used except for burst access cycles.The initial value for the CS0 area is 7 (seven wait cycles). The initial values for the other chip select areasare undefined.

[Bits 11-8] W11 to W08 = Inpage Access Wait CyclesThese bits set the number of automatic wait cycles for in-page access in burst mode. This setting ismeaningless when the burst mode is not used.

Note that, even though the number of first access wait cycles and in-page access wait cycles are set to the same value, the access times from addresses in their respective access cycles are not the same. (This is because in-page access cycles involve an address output delay.)

[Bits 7-6] W07-W06 = Read -> Write Idle CyclesA read-to-write idle cycle is inserted between a read cycle and the write cycle to prevent read data and write data from causing a collision on the data bus. During the idle cycle, all chip select signals are negated and the data pins remain in the high impedance state. When a reading is followed by a writing, the specified number of idle cycles are inserted if access to another chip select area occurs after the reading.


0 0 X X Normal access (asynchronous SRAM, I/O, single/page/burst-ROM/FLASH)

W15 W14 W13 W12 First access wait cycles

0 0 0 0 0 automatic wait cycle


... ...

1 1 1 1 15 automatic wait cycles

W11 W10 W09 W08 In-page access wait cycles



... ...

1 1 1 1 15 automatic wait cycles


128

[Bits 5-4] W05-W04: Write Recovery CyclesA write recovery cycle is set to control access to a device restricted on the interval between writing access to the device and succeeding access. During the write recovery cycle, all chip select signals are negated and the data write enable pin maintains the "H" level.When the write recovery cycle count has been set to one cycle or more, every write access is followed by a write recovery cycle.

[Bit 3] W03 = WRX[3:0]/WEX output timing selectionThis bit is used to select whether to use the write strobe output as asynchronous strobe output or synchronous write enable output. Setting them as asynchronous strobe output supports normal memory-I/O access; setting them as synchronous write enable output supports clock-synchronous access between memory and I/O device (such as ASIC integrated memory).

Selecting the write strobe output as synchronous write enable output (with the AWR W03 bit = "0") has the following effects on operations.- The synchronous write enable output timing assumes the execution of fetch at the rising edge of the

MCLK output of the external memory access clock. The timing is different from the asynchronous strobe output.

- The WRXO[3:0]/WEX pin output asserts the synchronous write enable output when the ASX pin output is asserted. The synchronous write enable output has the "L" level at a writing to the external bus. At a reading from the external bus, the synchronous write enable output has the "H" level.

- The external data output pin output write data in the clock cycle next to the clock cycle, which is asserted the synchronous write enable output.

- The read strobe output (RDXO) is used as an asynchronous read strobe regardless of the WRX[3:0]/WEX output timing setting. Use it as it is intended for controlling the I/O direction of data.

- The synchronous write enable output has the following restrictions on usage.- Do not make either of the following additional wait settings:- CSX->RDX/WRX setup setting (Always write "0" to the AWR: W01 bit.)

W07 W06 Read-write idle cycles

0 0 0 cycle

0 1 1 cycle

1 0 2 cycles

1 1 3 cycles

W05 W04 Write recovery cycles

0 0 0 cycle

0 1 1 cycle

1 0 2 cycles

1 1 3 cycles

W03 WRX[3:0]/WEX output timing selection

0 MCLK-synchronous write enable output (valid with ASX = "L")

1 Asynchronous write strobe output (normal operation)


129

- First access wait cycle setting (Always write "0000B" to the AWR: W15-W12 bits.)

- Do not make either of the following access type settings (TYPE[3:0] bits (bits 3-0) in the ACR register):- Setting for using WRXO[3:0] as write strobe output (Always write "0" to the ACR: TYPE[1] bit.)- Address/data multiplex bus setting (Always write "0" to the ACR: TYPE[2] bit.)- RDY input enable setting (Always write "0" to the ACR: TYPE[0] bit.)- For the synchronous write enable output, always set the burst length to 1 (set the ACR: BST[1:0] bits to

"00B").

[Bit 2] W02 = Address → CSX Delay

This bit sets an address→CSX delay when addresses require certain setup at the falling edge of CSX or when the edge of CSX is also required for successive accesses to the same chip select area.The bit sets a delay from the address or ASX output to CSXO[7:0].

When this bit is set to "0" to select setting no delay, the CSXO[7:0] signals start being asserted at the same timing as ASX assertion. If successive accesses to the same chip select area are executed at this time, the CSXO[7:0] signals may stay asserted and remain unchanged between the accesses.When this bit is set to "1" to select setting a delay, the CSXO[7:0] signals start being asserted at the rising edge of the external memory clock MCLK output. Even though successive accesses to the same chip select area are executed at this time, the CSXO[7:0] negate timing is generated between the accesses.When setting a CSX delay is selected, insert one setup cycle after the delayed CSXO[7:0] assertion before asserting the read/write strobes. (This has the same effect as CSX→RDX/WRX setup setting of the W01 bit.)The address→CSX delay setting also applies the DACKX[2:0] signals output to the same area in the same way. The DACKX[2:0] outputs have the same waveform as the CSXO[7:0] outputs to that area.

[Bit 1] W01 = CSX→RDX/WRX setup cycle

This bit is used to set a CSX→RDX/WRX setup cycle to extend the interval from CSX0[7:0] assertion to read/write strobe assertion. At least one setup cycle is inserted after asserting the CSX signals before asserting the read/write strobes.

When this bit is set to "0" to select 0 cycle, the RDXO/WRXO[3:0]/WEX signals are outputted at highest speed, from the rising edge of the external memory clock MCLKO output immediately after the assertion of CSXO[7:0].

When this bit is set to "1" to select one cycle, all of the RDXO/WRXO[3:0]/WEX outputs are always delayed at least one cycle.When successive accesses in the same chip select area are performed without negating CSXO[7:0], no setup cycle is inserted. When an address-asserted setup cycle is required, inserting an address→CSX delay by enabling the W02 bit, the CSX signals are negated temporarily at each access and thus this setup cycle becomes effective.When a CSX delay setting of W02 bit is inserted, this setup cycle remains valid regardless of the W01 bit setting.

W02 Address-CSX delay

0 Set delay

1 Set no delay

W01 CSX-RDX/WRX setup cycle

0 0 cycle

1 1 cycle


130

[Bit 0] W00 = RDX/WRX->CSX Hold Cycle

This bit sets an RDX/WRX-to-CSX hold cycle to extend the interval from read/write strobe negation to CSXO[7:0] negation. One hold cycle is inserted after negating the read/write strobes before negating the CSXO[7:0] signals.

When this bit is set to "0" to select 0 cycle, after the hold delay time passed, the CSXO[7:0] signals are negated at the rising edge of the external memory clock MCLKO output after the negation of RDXO/WRXO[3:0]/WEX.When this bit is set to "1" to select one cycle, the CSXO[7:0] are negated after a delay of one cycle. When bit4 (EDOE bit) of TCR (Terminal and timing Control Register) is also set to "1", write data output is also extended for one cycle.When successive accesses in the same chip select area are performed without negating CSXO[7:0], no hold cycle is inserted. When an address-asserted hold cycle is required, inserting an address-to-CSX delay by enabling the W02 bit, the CSXO[7:0] signals are negated temporarily at each access and thus this hold cycle becomes effective.

W00 RDX/WRX-CSX hold cycle

0 0 cycle

1 1 cycle


131

5.4.3.2 Memory Type A (SDRAM/FCRAM) and Memory Type B (FCRAM)

The chip select area that performed the following setting to the access type (TYP[3:0]bit) of ACR0~7 registers, becomes the area that performs SDRAM/FCRAM.

The function of each bit in AWR6~7 registers for SDRAM access area are shown below.Since the initial values are undefined, set them before enabling each chip select area using the CSER register.In area which SDRAM/FCRAM is connected, all settings of this register should be the same.

[Bits 15] W15 = Reserved bitReserved bit. Always set “0” to this bit.

[Bits 14-12] W14-W12 = RAS-CAS Delay CyclesSet the number of cycles from RAS output to CAS output.

In the area which SDRAM/FCRAM is connected, set all the RAS-CAS delay cycles settings in the same way by using these bits.

[Bits 11] W11 = Reserved bitReserved bit. Always set “0” to this bit.

[Bits 10-8] W10-W08 = CAS latency Cycle Set the CAS latency.

In the area which SDRAM/FCRAM is connected, set all the CAS latency settings in the same way by using these bits .


1 0 0 0 Memory type A: SDRAM/FCRAM (auto precharge is not used).

1 0 0 1 Memory type B: FCRAM (auto precharge is used).

W14 W13 W12 RAS-CAS delay cycles

0 0 0 1 cycle

0 0 1 2 cycles

... ...

1 1 1 8 cycles

W10 W09 W08 CAS latency

0 0 0 1 cycle

0 0 1 2 cycles

... ...

1 1 1 8 cycles


132

[Bits 7-6] W07-W06 = Read→Write Idle Cycle

Set the minimum cycle from the read data input cycle till the last write command is issued.

In the area which SDRAM/FCRAM is connected, set all the read→write idle cycle settings in the same way by using these bits.

[Bits 5-4] W05-W04 = Write Recovery Cycle

Set the minimum cycle from the last data output till the next read command is issued.

In the area which SDRAM/FCRAM is connected, set all the write recovery settings in the same way by using these bits.

[Bits 3-2] W03-W02 = RAS Active Time

Set the minimum cycle of the RAS active time.

In the area which SDRAM/FCRAM is connected, set all the RAS active time settings in the same way by using these bits .

[Bits 1-0] W01-W00 = RAS Precharge Cycle

Set the RAS precharge cycle.

In the area which SDRAM/FCRAM is connected, set all the RAS precharge settings in the same way by using these bits.

W07 W06 Read→Write Idle Cycle

0 0 1 cycle

0 1 2 cycles

1 0 3 cycles

1 1 4 cycles

W05 W04 Write Recovery Cycle

0 0 1 cycle

0 1 2 cycles

1 0 3 cycles

1 1 4 cycles

W01 W00 RAS Active Time

0 0 1 cycle

0 1 2 cycles

1 0 5 cycles

1 1 6 cycles

W01 W00 RAS Prechagre Cycle

0 0 1 cycle

0 1 2 cycles

1 0 3 cycles

1 1 4 cycles


133

5.4.4 MCRA (Memory Configuration Register for Extend Type-A: SDRAM/FCRAM without Auto Precharge)

Perform the setting of SDRAM/FCRAM which is connected to the chip select area that performed the following setting to the access type (TYP[3:0]bit) of ACR0~7 registers.

MCRA shares the register hardware with MCRB, so changing MCRA also changes MCRB at the same time.If different values are written simultaneously, the value that is written to MCRA, is set to both registers.

[Bits 31] Reserved = Reserved bitReserved bit. Always set “0” to this bit.

[Bits 30-28] PSZ2, PSZ1, PSZ0 = Page SiZeSet the page size of SDRAM to be connected.

[Bits 27] WBST = Write BurST enableSet whether perform burst writing at writing.

Always set this bit to “1” when FCRAM is connected. FCRAM does not support “Burst-reading, Single-writing” mode.


MCRA 31 30 29 28 27 26 25 24 At INIT At RST

0000 0670 H RESV PSZ2 PSZ1 PSZ0 WBST BANK ABS1 ABS0 XXXXXXXXb XXXXXXXXb W/R


1 0 0 0 Memory type A: SDRAM/FCRAM (auto precharge is not used).

PSZ2 PSZ1 PSZ0 SDRAM Page SiZe

0 0 0 8 bit column address = A0-A7 (256 memory word)




1 X X Setting prohibited

WBST Write burst setting

0 Single writing

1 Burst writing


134

[Bits 26] BANK = BANK type select

Set the bank number of SDRAM to be connected.

[Bits 25-24] ABS1, ABS0 = Active Bank SelectSet the maximum bank number that is actvie simultaneously.

BANK Bank type setting

0 2 banks

1 4 banks

ABS1 ABS0 Active bank number setting

0 0 1 bank

0 1 2 banks

1 0 3 banks

1 1 4 banks


135

5.4.5 MCRB (Memory Configuration Register for Extend Type-B: FCRAM with Auto Precharge)

Perform the setting of FCRAM which is connected to the chip select area that performed the following setting to the access type (TYP[3:0]bit) of ACR0~7 registers.

MCRB shares the register hardware with MCRA, so changing MCRA also changes MCRB at the same time.If different values are written simultaneously, the value that is written to MCRA, is set to both registers.

MCRB functions as MCRA. However, function of WBST bit cannot be used for this TYPE setting.(FCRAM does not support “Burst-reading, Single-writing” mode.)


MCRB 23 22 21 20 19 18 17 16 At INIT At RST

0000 0671 H RESV PSZ2 PSZ1 PSZ0 WBST BANK ABS1 ABS0 XXXXXXXXb XXXXXXXXb W/R


1 0 0 1 Memory type B: FCRAM (auto precharge is not used).


136

5.4.6 IOWR0 to IOWR2 (I/O Wait Registers for DMAC)IOWR0-2 registers are used to set various wait at DMA fly-by access.

[Bits 31, 23, 15] RYE0, RYE1, RYE2 = RDY function setting (ReadY Enable 0, 1, 2)These bits are used to specify DMA fly-by access wait control using the RDYI pin for channels 0 to 2.

When the RYE bit in the IOWR register for each channel is set to "1", the RDYI pin can be used to insert await cycle for fly-by transfer using that channel. The IOWRX and IORDX outputs are deferred until theRDYI pin is enabled. The RDXO/WRXO[3:0]/WEX outputs on the memory side are also deferred insynchronization.If the chip select area as the destination of fly-by transfer has been RDY-enabled by the ACR register, theRDYI pin can be used to insert a wait cycle regardless of the RYEn bit on the IOWRX side. Even when thechip select area as the destination of fly-by transfer has been RDY-disabled by the ACR register, the RDYIpin can be used to insert a wait cycle only during fly-by access by enabling the RDY input using the RYEnbit on the IOWRX side.When RDY is enabled by fly-by writing access to SDRAM, enable HLD bit and perform hold wait setting.

[Bits 30, 22, 14] HLD0, HLD1, HLD2 = HoLD wait controlThese bits are used to control the hold cycle of the read strobe signal on the transfer-source access sideat DMA fly-by access.

When this bit is set to "0", the read strobe signal (RDXO for memory→I/O access or IORDX for I/O→memory access) and the write strobe signal (IOWRX for memory→I/O access or WRXO[3:0] andWEX for I/O→memory access) on the transfer-source access side are output at the same timing.When this bit is set to "1", the read strobe signal is output one cycle longer than the write strobe signal tokeep the time for holding data on the transfer-source access side before transfer.When RDY is enabled by fly-by writing access to SDRAM, enable HLD bit and perform hold wait setting.


IOWR0 31 30 29 28 27 26 25 24 At INIT At RST

0000 0678 H RYE0 HLD0 WR01 WR00 IW03 IW02 IW01 IW00 xxxxxxxxb xxxxxxxxb W/R

IOWR1 23 22 21 20 19 18 17 16

0000 0679 H RYE1 HLD1 WR11 WR10 IW13 IW12 IW11 IW10 xxxxxxxxb xxxxxxxxb W/R

IOWR2 15 14 13 12 11 10 9 8

0000 067A H RYE2 HLD2 WR21 WR20 IW23 IW22 IW21 IW20 xxxxxxxxb xxxxxxxxb W/R

RYEn RDY function setting

0 Disable RDY input for I/O access

1 Enable RDY input for I/O access

HLDn Hold wait setting

0 Insert no hold cycle

1 Insert hold cycle to extend read cycle by one cycle


137

[Bits 29-28, 21-20, 13-12] WR0, 1, 2 = (I/O Idle Cycles Setting) I/O Idle Cycles

These bits specify the number of idle cycles for successive I/O accesses in DMA fly-by access mode.

When one or more idle cycles are set, the specified number of idle cycles are inserted after I/O access inDMA fly-by access mode. In the idle cycle, all CSX and strobe outputs are negated and the data pinsremain in the high impedance state.

[Bits 27-24, 19-16, 11-8] IW03-00, IW13-10, IW23-20 = I/O Wait CyclesThese bits specify the number of automatic wait cycles for I/O access in DMA fly-by access mode.

As the number of wait cycles to be inserted, the greater one between the I/O side setting by the IWnn bitsand the wait setting of the fly-by transfer destination (such as memory) is used. The number of actuallyinserted wait cycles may therefore be greater than the number of cycles set by the IWnn bits.

WRn1 WRn0 I/O idle cycles

0 0 0 cycle

0 1 1 cycle

1 0 2 cycles

1 1 3 cycles

IWn3 IWn2 IWn1 IWn0 I/O wait cycles

0 0 0 0 0 cycle

0 0 0 1 1 cycle

... ...

1 1 1 1 15 cycles


138

5.4.7 CSER (Chip Select Enable Register)

[Bits 31-24] CSE7-CSE0 = Chip select area enable 0-7These bits enable their respective chip select areas from CS0X to CS7X.The initial value of the register is 00000001B, enabling only the CS0 area.Writing "1" to these bits enable the respective chip select areas according to the settings of the ASR0-ASR7, ACR0~7 and AWR0-AWR7 registers. Be sure to perform all the settings of the corresponding chipselect area before enabling. However, before executing power sequence by PON bit in refresh controlregister RCR, be sure to enable the chip select area by CSER. To the SDRAM/FCRAM connected to thearea that has not been enabled by CSER, the power sequence becomes invalid.

Initial value

31 30 29 28 27 26 25 24 At INIT At RST Access

0000 0680 H CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001 B 00000001 B R/W

CSE0 to CSE7 Area control

0 Disable

1 Enable

CSE bit Corresponding CSX0 pin

bit[24]:CSE0 CSXO[0]









139

5.4.8 CHER (CacHe Enable Register)This register controls storing data read from each chip select area to the built-in cache.

[Bits 24-17] CHE7-CHE0 = Cache area setting (Cache Enable 7-0)These bits enable or disable their respective chip select areas for being cached.

Initial value

Access

23 22 21 20 19 18 17 16 At INIT At RST

0000 0681 H CHE7 CHE6 CHE5 CHE4 CHE3 CHE2 CHE1 CHE0 xxxxxxx1B xxxxxxx1B R/W

CHnE Cacheable area setting

0 Non-cacheable area (Do not cache data read from the area)

1 Cacheable area (Cache data read from the area)


140

5.4.9 TCR (Terminal and Timing Control Register)This register controls functions applicable to the entire external bus interface controller, such as common pin function setting and timing control.

[Bit 7] BREN = BRQ input enableThis bit enables the BRQ pin input, allowing an external bus to be shared.

The BRQ input is ignored in the initial state (when this pin = "0").When this pin is set to "1", the BRQ input goes high. When the bus has become releasable, the bus is released (under high-impedance control) and the BGRNTX goes active ("L" output).The address-bus and data-bus output enable pins (AC[3:0] and DC[3:0]) are placed in the disable state ("H" output). CSX[7:0] puts CSC[7:0] in the disable state ("H" output) only for the chip select areas with the corresponding ACR SREN bit = "1". The strobe output enable pins (RDXC, WRXC) enter the disable state ("H" output) when all the SREN bits in the ACR registers for the chip select areas enabled by the SCER register = "1".

[Bit 6] PSUS = Prefetch SUSpendThis bit controls suspending the prefetch for all areas.

When this bit is set to "1", prefetch is suppressed until "0" is written to the bit. When prefetch is being suppressed, the prefetch buffer maintains its contents without erasing them unless a prefetch buffer miss occurs. Before restarting prefetching, therefore, clear the prefetch buffer by setting the PCLR bit (bit 5).

[Bit 5] PCLR = Prefetch buffer CleaRThis bit is used to clear all the contents of the prefetch buffer.

Writing "1" to this bit clears the entire prefetch buffer only once. When clearing the buffer is finished, the bit returns to "0" automatically. Before clearing the buffer, set the PSUS bit to "1" to suspend prefetching ( "10B" can be written to both of the PSUS and PCLR bits at the same time).

Initial value

7 6 5 4 3 2 1 0 At INIT At RST Access

0000 0683 H BREN PSUS PCLR EDOE RESV RESV RDW1 RDW0 00000000 B 0000xxxx B W

BREN BRQ input enable/disable status

0 Disable BRQ input, not allowed bus sharing by BRQ/BGRNTX

1 Enable BRQ input, allowing bus sharing by BRQ/BGRNTX

PSUS Prefetch control

0 Enable prefetch

1 Suppress prefetch

PCLR Prefetch buffer control

0 Normal state

1 Clear prefetch buffer


141

[Bit 4] EDOE = Enable Data Output Extension

Write data is also extended for one cycle during RDX/WRX→CSX hold delay.

If the access type (TYP 3:0) of the ACR0-7 register is normal access of 00xx or 01xx or address/data multiplex operation, and both W00 bit (RDX/WRX→CSX hold extension cycle) of AWR0-7 register and this bit are set to “1”, write data output is extended for one cycle. As a result, it is possible to increase one cycle of data hold for the rising edge of WRX.However, due to the negation of CSX is not generated during the access to the successive area, and the hold extension cycle of CSX is not inserted, write data output is not extended.

In this case, hold extension cycle of CSX and extension cycle of write data are inserted by setting W02 bit (address→CSX delay) of AWR0-7 register and generating negation timing of CSX. The operation is not effected during reading.

[Bits 3-2] Reserved = Reserved bits

These bits are reserved bits. Always set "0" to these bits.

[Bits 1-0] RDW1-RDW0 = ReDuce Wait cycleThese bits are used to reduce only the number of automatic wait cycles for all chip select areas and fly-by I/O channels without changing the setting in the AWR register. This function has no effect on the idle cycle, recovery cycle, setup cycle, or hold cycle setting. SDRAM control area is also not functioned.

This function prevents an excessive access cycle wait state during operation at a low clock speed, for example, when the base clock speed is low or when the external bus clock divide ratio is high.To change the number of wait cycles, usually, all of the AWR registers must be updated one by one. Using the function of the RDW1-RDW0 bits can reduce only the access cycle wait state without changing the fast-clock settings in all AWR registers.To return to the original high-speed clock settings, be sure to reset the RDW1-RDW0 bits to "00B".

EDOE Delay output extension

0 Without write data extension

1 With write data extension

RDW1 RDW0 Wait cycle reduction

0 0 Normal wait state (Original settings in AWR0-AWR7)

0 1 Reduce the setting values in AWR0-AWR7 to 1/2 (by shifting right 1 bit)

1 0 Reduce the setting values in AWR0-AWR7 to 1/4 (by shifting right 2 bits)

1 1 Reduce the setting values in AWR0-AWR7 to 1/8 (by shifting right 3 bits)


142

5.4.10 RCR (Refresh Control Register)

This register is used to set various refresh control setting to SDRAM. The setting of this register has no significance in any area which has not been set SDRAM control. In this case, do not rewrite the register value from the initialization state.At reading of read-modify-write, SELF, RRLD and PON bits always return to “0”.

[Bit 31] SELF = Self refresh control (SELF refresh assert)This bit controls the self refresh mode for the memory which is corresponding to self refresh mode.

When this bit is set to “1”, self refresh is performed after the issue of SELF command. When this bit is set to “0”, self refresh mode ends.To set the core macro to stop mode as maintaining the values of SDRAM, self refresh mode should be set by this bit before setting stop mode. Under this circumstance, concentration refresh executes before a transition to self refresh, so a generated external access request is kept waiting until the execution of concentration refresh is completed. The transition to stop mode is also kept waiting. To release from self refresh mode, write “0” to this bit or generate an access to SDRAM. Under this circumstance, since concentration refresh executes immediately after the release, if external accesses including SDRAM access is executed, the external access request is kept waiting for a period of time and the operation of CPU is stopped.Setting LSI to stop mode without entering self refresh mode, LSI is caused to power down, and the content of SDRAM will be destroyed.At reading of read-modify-write, this bit always return to “0”.

[Bit 30] RRLD = Refresh counter activate control (Refresh counter ReLoaD))This bit specifies the start up of refresh counter operation and reloading.

In initialization state, refresh counter stops. Under this circumstance, if this bit is set to “1”, to all the SDRAM areas which is enabled by CSER, auto refresh is executed once in dispersion mode or is executed as the times specified by RFC in concentration mode. Then, the value of RFINT[5:0] bit is


RCRH 31 30 29 28 27 26 25 24 At INIT At RST

0000 0684 H SELF RRLD RFINT5 RFINT4 RFINT3 RFINT2 RFINT1 RFINT0 00xxxxxx b 00xxxxxx b W/R

RCRL 23 22 21 20 19 18 17 16

0000 0685 H BRST RFC2 RFC1 RFC0 PON TRC2 TRC1 TRC0 xxxx0xxx b xxxx0xxx b W/R

SELF Self refresh control

0 Auto refresh or power down

1 Shifts to self refresh mode

RRLD Refresh counter activate control

0 Disable (no execution)

1 Auto refresh is executed once, RFINT value is reloaded


143

reloaded. After that refresh counter starts countdown, whenever an underflow occurs from counter value “000000B”, the reloading of the value of RFINT[5:0] bit and the execution of auto refresh for once are performed simultaneously, repeatly. This bit returns to “0” after the reloading ends.To stop auto refresh, write “000000B” to RFINT[5:0] bit.At reading of read-modify-write, this bit always return to “0”.

[Bit 29-24] RFINT [5:0] = Auto refresh interval (ReFresh INTerval)This bit specifies the interval of auto refresh.Auto refresh interval can be obtained by (the value of REFINT[5:0]) x 32 x (external bus clock cycle) in dispersion refresh mode; and can be obtained by (the value of REFINT[5:0]) x 32 x (specified times of RFC) x (external bus clock cycle) in concentration refresh mode.To stop auto refresh, write “000000B” to RFINT[5:0] bit. In addition, refresh counter executes countdown during the issue of auto refresh command.

[Bit 23] BRST = Burst refresh control (BuRST refresh select)This bit controls the operation mode at auto refresh.

When the dispersion refresh is selected, auto refresh command is issued once at every refresh interval.When the burst refresh is selected, auto refresh command is continuously issued as the number of times specified by refresh counter at every refresh interval.

[Bit 22-20] RFC [2:0] = The times of refresh (ReFresh Count)This bit specifies the necessary times of refresh for refreshing all SDRAM.

The refresh count specifed here is the concentration refresh count executing before or after the transition to self refresh mode. In addition, when burst refresh is selected by BRST bit, the refresh command count is issued at every refresh interval.

BRST Auto refresh mode control

0 Dispersion refresh (disperse and activate auto refresh)

1 Burst refresh (continuously activate auto refresh once)

RFC2 RFC1 RFC0 The number of times of refresh

0 0 0 256

0 0 1 512

0 1 0 1024

0 1 1 2048

1 0 0 4096

1 0 1 8192


1 1 1 Refresh prohibited


144

[Bit 19] PON = Power on control (Power On)

This bit controls the power sequence of SDRAM (FCRAM).

Setting PON bit to “1”, the power sequence of SDRAM starts. To be sure set the corresponding AWR, MCRA(B) and CSER registers before starting the power sequence. As the power sequence is started, this bit returns to “0”. To enable PON bit, also enable RFINT setting and RRLD, and activate the refresh counter. Only PON bit does not execute refresh operation.Do not enable with SELF bit simultaneously.At reading of read-modify-write, this bit always return to “0”.

[Bit 18-16] TRC [2:0] = Refresh cycles (tRC) setting (Time of Refresh Cycle)This bit sets the refresh cycle (tRC).

PON Power on control

0 Disable (no execution)

1 Power sequence starts

TRC2 TRC1 TRC0 Refresh cycle (tRC)

0 0 0 4

0 0 1 5

0 1 0 6

0 1 1 7

1 0 0 8

1 0 1 9

1 1 0 10

1 1 1 11


145

5.4.11 MODR (MODe Register)This register specifies the operation mode. The register automatically reads one byte of mode data which is located at address 000FFFF8H by hardware in the reset sequence immediately after a INIT reset.This register cannot be accessed by user program. However, as an exception, when the macro shifts to emulation mode by INTE instruction, or shifts to emulation mode by a break at a debug using ICE, this register is mapped at 0000_07FDH. Select this function when using ICE, perform the mode data setting before the program loading by writing a appropriate value to this register.* Nothing is in the address (0000_07FFH) of mode register of FR family.

[Bits 23-18] Reserved = Reserved bitsThese bits are reserved bits. Always set "0" to these bits.

[Bits 17-16] WTH1-WTH0 = Initial bus WidTH 1-0These bits are used to specify the bus width for reading reset vectors and the initial value of the DBW1-DBW0 bits in the ACR0 register.

The DBW1-DBW0 bits in the ACR0 register reflect the setting in the WTH1-WTH0 bits.


23 22 21 20 19 18 17 16 At INIT At RST

RESV RESV RESV RESV RESV RESV WTH1 WTH0 ******** B xxxxxxxx B R

WTH1 WTH0 Bus width

0 0 8bit

0 1 16bit

1 0 32bit



146

5.5 Setting Chip Select AreasThe external bus interface can set a total of eight chip select areas.The ASZ3 to ASZ0 bits in ASR0 to ASR7 (Area Select Registers) and in ACR0 to ACR7 (Area Configuration Registers) are used to allocate the address spaces for individual areas 0 to 7 arbitrarily in 64 kilobytes in four gigabytes of a vast memory space. When bus access to the area allocated by such a register is performed, the corresponding chip select signal (CSXO[7:0]) has the "L"-level output in the access cycle.

[Examples of ASR and ASZ[3:0] settings]1. ASR1=0003h ACR1->ASZ[3:0]=0000B

Chip select area 1 is allocated to the 00030000H-0003FFFFH address range.2. ASR2=0FFCh ACR2->ASZ[3:0]=0010B

Chip select area 2 is allocated to the 0FFC0000H-10000000H address range.3. ASR3=0011h ACR3->ASZ[3:0]=0100B

Chip select area 3 is allocated to the 00100000H-00200000H address range.Since the ACR->ASZ[3:0] bits specify one megabyte in this example, the boundaries are given in 1-MB units and ASR3[19:16] are ignored.

After a reset, the 00000000H-FFFFFFFFH address range is allocated as chip select area 0 until the first writing to the ACR0 register is performed.

Note: Adjacent chip select areas must not overlap each other.

(Initial value) (Example)

00000000 H 00000000 H

00030000 H Area 1 64KB

00040000 H

Area 0 00100000 H Area 3 1MB

00200000 H

0FFC0000 H Area 2 256KB

0FFFFFFF H

FFFFFFFF H FFFFFFFF H


147

5.6 Bus Operations

5.6.1 Relationships between Data Bus Widths and Control Signals

The WRX[3:0] control signals correspond to the byte positions of a data bus on a one-to-one basis, regardless of the data bus width.Shown below are the byte positions of the data bus with the data bus width set for each bus mode and their respective control signals.

1) Regular bus interface

2) Time-division I/O interface

D31

D0

a) 32-bit bus width

data bus Controlsignal

WRX[0]

WRX[1]

WRX[2]

WRX[3]

data bus Controlsignal data bus Control

signal

WRX[0]

WRX[1]

WRX[0]

-

-

-

-

-

b) 16-bit bus width c) 8-bit bus width

(D15 to D0 are notused.)


-

-

-

-

data bus Controlsignal data bus Control

signal

WRX[0]

WRX[1]

WRX[0 ]

a) 16-bit bus width b) 8-bit bus width



-

-

Outputaddresses

A15 8

A7 0 -

-

-

Outputaddresses

A7 0

-

-

-

-

-

-

-

- -

-

D31

D16


148

5.6.2 Big Endian Bus AccessThe FR71 family can use the big endian or little endian method selectively for each chip select area except the CS0 area. When the LEND bit in the ACR register for a chip select area is set to "1", the area is handled as a little endian area.The FR71 family usually uses the big endian method for external bus access.

5.6.2.1 Data FormatsInternal registers and external data buses have the relationships as illustrated below.

D31

D15

D23

D7

D0

AA

BB

CC

DD

Internal register

D31

D15

D23

D7

D0

AA

BB

CC

DD

External bus

(2) Halfword access (during execution of LDUH or STH instruction)

b) Lower output address "10"

D31

D15

D23

D7

D0

AA

BB

Internal registerD31

D15

D23

D7

D0

AA

BB

External bus

a) Lower output address "00"

D31

D15

D23

D7

D0

AA

BB

Internal registerD31

D15

D23

D7

D0

AA

BB

External bus

(3) Byte access (during execution of LDUB or STB instruction)

D31

D15

D23

D7

D0AA

Internal register

D31

D15

D23

D7

D0

AA

External bus


D31

D15

D23

D7

D0AA

Internal register

D31

D15

D23

D7

D0

AA

External bus


D31

D15

D23

D7

D0AA

Internal register

D31

D15

D23

D7

D0

AA

External bus

c) Lower output address "10"

D31

D15

D23

D7

D0AA

Internal register

D31

D15

D23

D7

D0AA

External bus

d) Lower output address "11"

(1) Word access (during execution of LD or STinstruction)


149

5.6.2.2 Data Bus Widths

External busInternal register

read/write

AA

BB

CC

DDD07

D15

D23

D31 AA

BB

CC

DD D07

D15

D23

D31read/writeAA

BB

CC

DDD07

D15

D23

D31 AA

BB

CC

DD D23

D31

“00” “10”

External bus

Lower output address

Internal register

External bus

Lower output

Internal register

read/writeAA

BB

CC

DDD07

D15

D23

D31 AA

“00”

D31BB CC DD

“01” “11”“10”

(1) 32- bit bus width (2) 16- bit bus width

(3) 8- bit bus width


150

5.6.2.3 External Bus AccessThis section summarizes external bus accesses by:

- Bus width (32, 16, or 8 bits)- Access data length (word, halfword, or byte)

for the following items: - Access byte position- Program address- Output address bus access count

The FR71 family does not detect misalignment errors.Even when the lower two bits of a program-specified address are "00", "01", "10", or "11", therefore, those of the output address are always "00" for word access. For halfword access, the latter bits are "00" when the former ones are "00" or "01" and the latter ones are "10" when the former ones are "10" or "11".

(1) 32-bit bus width

PA1/PA0 : Lower two bits of program-specified address

Output A1/A0 : Lower two bits of output address

: First byte position of output address

+ : Data byte position to be accessed

1) - 4) : Bus access count

(A) word access(a) PA1/PA0=”00”

-> 1) Output A1/A0=”00”

(b) PA1/PA0=”01”

-> 1) Output A1/A0=”00”

(c) PA1/PA0=”10”

-> 1) Output A1/A0=”00”

(d) PA1/PA0=”11”

-> 1) Output A1/A0=”00”

1)

LSBMSB

32bit

1) 1) 1)

(B) half word access(a) PA1/PA0= 00”-> 1) OutputA1/A0=”00”

(b) PA1/PA0=”01”-> 1) OutputA1/A0=”00”

(c) PA1/PA0=”10”-> 1) OutputA1/A0=”10”

(d) PA1/PA0=”11”-> 1) Output A1/A0=”10”

1110

1) 1)

01

1)

00 01

1)

001110

(C) byte acce ss(a) PA1/PA0=”00”

-> 1) Output A1/A0=”00”

(b) PA1/PA0=”01”

-> 1) Output A1/A0=”01”

(c) PA1/PA0=”10”

-> 1) Output A1/A0=”10”

(d) PA1/PA0=”11”

-> 1) Output A1/A0=”11”

111001

1)

1110

1)

00 1101

1)

00 1001

1)

00

00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

00 01 00 01 10 11 10 11

00 01 10 11


151


2)

1)

LSBMSB

16bit

1110

01

2)

1) 00

2)

1)

2)

1)

1110

1)

1110

1) 01

1)

00 01

1)

00

1110

011)

1110

1) 00

11

01

1)

00

10

01

1)

00

(A) word access (a) PA1/PA0="00" ->1) Output A1/A0="00" 2) Output A1/A0="10"

(b) PA1/PA0="01" ->1) Output A1/A0="00" 2) Output A1/A0="10"

(c) PA1/PA0="10" ->1) Output A1/A0="00" 2) Output A1/A0="10"

(d) PA1/PA0="11" ->1) Output A1/A0="00" 2) Output A1/A0="10"

(B) half word access (a) PA1/PA0="00" ->1) Output A1/A0="00"

(b) PA1/PA0="01" ->1) Output A1/A0="00"

(d) PA1/PA0="11" ->1) Output A1/A0="10"

(c) PA1/PA0="10" ->1) Output A1/A0="10"

(C) byte access (a) PA1/PA0="00" ->1) Output A1/A0="00"

(b) PA1/PA0="01" ->1) Output A1/A0="01"

(d) PA1/PA0="11" ->1) Output A1/A0="11"

(c) PA1/PA0="10" ->1) Output A1/A0="10"

00

10

01

11 1110

0100

1110

0100

00 01

10 11

0000 0001 01

10 11 10 11


152

(3) 8-bit bus width

LSBMSB

11

10

01

4)

3)

2)

1)

8 bit

00

4)

3)

2)

1)

4)

3)

2)

1)

4)

3)

2)

1)

2)

1)

2)

1)

2)

1)

2)

1)

11

10

01

1) 00

1)

1)

1)

(A) word access (a) PA1/PA0="00" ->1) Output A1/A0="00" 2) Output A1/A0="01" 3) Output A1/A0="10" 4) Output A1/A0="11"

(b) PA1/PA0="01" ->1) Output A1/A0="00" 2) Output A1/A0="01" 3) Output A1/A0="10" 4) Output A1/A0="11"

(d) PA1/PA0="11" ->1) Output A1/A0="00" 2) Output A1/A0="01" 3) Output A1/A0="10" 4) Output A1/A0="11"

(c) PA1/PA0="10" ->1) Output A1/A0="00" 2) Output A1/A0="01" 3) Output A1/A0="10" 4) Output A1/A0="11"

(B) half word access (a) PA1/PA0="00" ->1) Output A1/A0="00" 2) Output A1/A0="01"

(b) PA1/PA0="01" ->1) Output A1/A0="00" 2) Output A1/A0="01"

(d) PA1/PA0="11" ->1) Output A1/A0="10" 2) Output A1/A0="11"

(c) PA1/PA0="10" ->1) Output A1/A0="10" 2) Output A1/A0="11"

(C) byte access(a) PA1/PA0="00"->1) Output A1/A0="00"

(b) PA1/PA0="01" ->1) Output A1/A0="01"

(d) PA1/PA0="11" ->1) Output A1/A0="11"

(c) PA1/PA0="10" ->1) Output A1/A0="10"

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

11

10

01

00

11

10

01

00

11

10

01

00


153

5.6.2.4 Examples of Connections to External DevicesIn this example, pins are represented by their function names. For the correspondence between pin names and function names, see Section 1.4 "Pin Description".

1 00

D31 D07 D00D00D15D00D16D15 D08D07D08D07D24D23

D07 W to RD00 X

[0]

D15 W to RD08 X

[2]

D23 W to RD16 X

[1]

D31W to RD24 X

[0]

00 01 1110

FR71Core

*: For a 16-bit/8-bit device, use the MSB-side data bus of this macro.

32-bit device 8-bit device*16-bit device*

("00" to "11": Lower two bits of address) ("0" to "1": Lower one bit of address)


154

5.6.3 Little Endian Bus AccessThe FR71 family can use the big endian or little endian method selectively for each chip select area except the CS0 area. When the LEND bit in the ACR register for a chip select area is set to "1", the area is handled as a little endian area.

5.6.3.1 OverviewThe FR71 family accomplishes little endian bus access by using bus access as in big endian mode, resulting in basically the same output address order and control signal outputs as in big endian mode, and by swapping the data bus byte positions depending on the bus width.Note that the big endian and little endian areas must be physically separated for connection.

<Differences between little endian and big endian methods>- The output address order is not different between the little endian and big endian methods.- Word access

The MSB-side byte data at address A[1:0]=00 in big endian mode corresponds to the LSB-side byte data in little endian mode.For word access, the little endian method reverses the positions of all the four bytes in a word.

- Halfword accessThe MSB-side byte data at address A[0] in big endian mode corresponds to the LSB-side byte data in little endian mode.For halfword access, the little endian method reverses the positions of two bytes in a halfword.

- Byte accessThere is no difference in byte access between the little endian and big endian methods.

<Restrictions on little endian areas>- When accessing a prefetch-enabled little endian area, be sure to use word access. When data read into the

prefetch buffer is accessed not in word length, endian conversion is not performed correctly and wrong data is read. This is traceable to a hardware restriction of the endian conversion mechanism.

- Do not place instruction code in any little endian area.


155

5.6.3.2 Data FormatsInternal registers and external data buses have the relationships as illustrated below.

(1) Word access (during execution of LD orST instruction)

(2) Halfword access (during execution of LDUH or STHinstruction)

(3) Byte access (during execution of LDUB or STBinstruction)

D31

D15

D23

D7

D0AA

Internal register D31

D15

D23

D7

D0

AA

External bus


D31

D15

D23

D7

D0AA

Internal register

D31

D15

D23

D7

D0

AA

External bus


D31

D15

D23

D7

D0AA

Internal register

D31

D15

D23

D7

D0

AA

Externalbus

c) Lower output address"10"

D31

D15

D23

D7

D0AA

Internal register D31

D15

D23

D7

D0AA

Externalbus

d) Lower output address"11"

D31

D15

D23

D7

D0

AA

BB

CC

DD

Internalregister D31

D15

D23

D7

D0AA

BB

CC

DD

External bus


D31

D15

D23

D7

D0

AA

BB


D15

D23

D7

D0

AA

BB

Externalbus


D31

D15

D23

D7

D0

AA

BB


D15

D23

D7

D0AA

BB

External bus


156

5.6.3.3 Data Bus Widths

AA

BB

CC

DDD07

D15

D23

D31 DD

CC

BB

AA D07

D15

D23

D31 AA

BB

CC

DDD07

D15

D23

D31 DD

CC

BB

AA D23

D31

“00” “10”

AA

BB

CC

DDD07

D15

D23

D31 DD

“00”

D31CC BB AA

“01” “11 ”“10”

(1) 32-bit bus widthInternal register External bus

read/write

read/write


Lower output address


Lower output

read/write


157

5.6.3.4 Examples of Connections to External DevicesIn this example, pins are represented by their function names. For the correspondence between pin names and function names, see Section 1.4 "Pin Description".

10 0011

D31 D08D07 D00D16D15D31D00D16D15 D24D23D08D07D24D23

D07W to RD00 X

[3]

D15W to RD08 X

[2]

D23W to RD16 X

[1]

D31W to RD24 X

[0]

00 01 1110 01

0

D15 D08D07 D00D15D00D08D07

D23W to RD16 X

[1 ]

D31W to RD24 X

[0]

0 1 1


FR71Core

Big endian area Little endian area


FR71Core



158

D07 D07 D00D00

D31W to RD24 X

[0]

(3) 8-bit bus widtrh

FR71Core



159

5.6.4 External Access

(1) Word access

1)D00D00

D31D31AA

CC

BB

DD

AA

CC

BB

DD

1)D00D00

D31D31AA

CC

BB

DD

DD

BB

CC

AA

Control pin

2)1)D00

D31D31AA

CC

BB

DD

AA CC

--

-

BB

-

DDD16

Control pin

2)1)D00

D31D31AA

CC

BB

DD

DD BB

--

-

CC

-

AA

-

-D16

4)3)2)1)D00

D31D31AA

CC

BB

DD

AA CCBB

----

DD

-

-

D24

----

----

-

Control pin

4)3)2)1)D00

D31D31AA

CC

BB

DD

DD BBCC

----

AA

-

-

D24

----

----

-

big endian mode little endian mode

32-bitbuswidth

16-bitbuswidth

Control pinInternal register External pin

Address (Lower 2 bits): "0"

WRX[0]

WRX[3]

WRX[2]

WRX[1]


Address: "0"

WRX[0]

WRX[3]

WRX[2]

WRX[1]

WRX[0]

-

-

WRX[1]

WRX[0]

WRX[1]

Internal register External pin

Address: "0" "2"


Address: "0" "2"

WRX[0] WRX[0]


Address: "0" "1" "2" "3"


Address: "0" "1" "2" "3"Control pin8-bit

buswidth


160

(2) Halfword access

D00D00

D31D31

AA

BB

1)

AA

-

BB

-D00D00

D31D31

AA

BB

1)

AA

-

BB

-

Control pin

D00D00

D31D31

CCCC

DDDD

1)

-

-

D00D00

D31D31

CC

CC DD

DD

1)

-

-

32-bitbuswidth


Address: "0"


Address: "0"

WRX[0]

WRX[1]

WRX[0]

WRX[1]

WRX[2]

WRX[3]

WRX[2]

WRX[3]


Address: "2"


Address: "2"



161

big endian mode litt le endian mode

16-bitbuswidth

D16

D00

D31D31

AA

BB

1)

AA

-

-

-

BB

-

D16

D00

D31D31

AA

BB

1)

AA

-

-

-

BB

-

D16

D00

D31D31

CC

DD

1)

CC

-

-

-

DD

-

D16

D00

D31D31

CC

DD

1)

CC

-

-

-

DD

-

8-bitbuswidth

D24

D00 D00

D31D31

AA

BB

2)1)

AA

-

- -

-

--

-

BB

-

-D24

D00 D00

D31D31

AA

BB

2)1)

BB

-

- -

-

--

-

AA

-

-

D24

D00 D00

D31D31

CC

DD

2)1)

CC

-

- -

-

--

-

DD

-

-D24

D00 D00

D31D31

CC

DD

2)1)

DD

-

- -

-

--

-

CC

-

-


Address: "0"


Address: "0"


Address: "2"


Address: "2


Address: "0" "1"


Address: "0" "1"


Address: "2" "3"


Address: "2" "3"

WRX[0] WRX[0]

WRX[0] WRX[0]

WRX[0]

WRX[1]

WRX[0]

WRX[1]

WRX[0]

WRX[1]

WRX[0]

WRX[1]


162

(3) Byte access

D00D00

D31D31

AA

1)

AA

-

-

-

D00D00

D31D31

AA

1)

AA

-

-

-

D00D00

D31D31

BB

1)

BB

-

-

-

D00D00

D31D31

BB

1)

BB

-

-

-

D00D00

D31D31

CC

1)

CC

-

-

-

D00D00

D31D31

CC

1)

CC

-

-

-

D00D00

D31D31

DD

1)

DD

-

-

-

D00D00

D31D31

DD

1)

DD

-

-

-

32-bitbuswidth



Address: "0"


Address: "0"

WRX[0] WRX[0]

WRX[1]WRX[1]


Address: "1"


Address: "1"


Address: "2"Control pinInternal register External pin

Address: "2"


Address: "3"


Address: "3"

WRX[2]

WRX[3]

WRX[2]

WRX[3]


163

D16

D00

D31D31

AA

1)

AA

-

-

-D16

D00

D31D31

AA

1)

AA

-

-

-

D16

D00

D31D31

BB

1)

BB

-

-

-

D16

D00

D31D31

BB

1)

BB

-

-

-

D16

D00

D31D31

CC

1)

CC

-

-

-D16

D00

D31D31

CC

1)

CC

-

-

-

D16

D00

D31D31

DD

1)

DD

-

-

-

D16

D00

D31D31

DD

1)

DD

-

-

-

WRX[0] WRX[0]


Address: "0"


Address: "0"16-bitbuswidth




Address: "1"

WRX[1] WRX[1]



Address: "2"


Address: "3"


Address: "3"

WRX[0]

WRX[1]

WRX[0]

WRX[1]


164

D24

D00

D31D31

AA

1)

AA

-

-

-D24

D00

D31D31

AA

1)

AA

-

-

-

D24

D00

D31D31

BB

1)

BB

-

-

-D24

D00

D31D31

BB

1)

BB

-

-

-

D24

D00

D31D31

CC

1)

CC

-

-

-D24

D00

D31D31

CC

1)

CC

-

-

-

D24

D00

D31D31

DD

1)

DD

-

-

-D24

D00

D31D31

DD

1)

DD

-

-

-

WRX[1] WRX[1]

WRX[1]WRX[1]

WRX[0]WRX[0]


8-bitbuswidth


Address: "0"


Address: "0"


Address: "1"


Address: "1"


Address: "2"


Address: "2"


Address: "3"


Address: "3"

WRX[0] WRX[0]


165

5.7 Bus Timing

This section details the bus access timings and operations in each mode.

5.7.1 Regular Bus Interface

The regular bus interface uses two clock cycles as a basic bus cycle for both read and write accesses.

5.7.1.1 Basic Timing (for Successive Accesses) (ACR->TYP[3:0]=0000B, AWR=0008H)

- ASX is asserted one cycle in the bus access start cycle.

- The AO[31:0] pins output the address at the first byte position for word, halfword, or byte access, from the bus access start cycle to the bus access end cycle.

- When the W02 bit in the AWR0 to AWR7 register is "0", the CSXO[7:0] signals are asserted at the same timing as ASX and are not negated if succeeding access occurs. When the W00 bit in the AWR register is "0", the CSXO[7:0] signals are negated. When the W00 bit is "1", the signals are negated one cycle after the end of the bus access.

- RDXO is asserted after a delay of MCLKI ↑ from the second bus access cycle. The signal is negated after the wait cycle specified by the W15-W12 bits in the AWR register is inserted.

#1

#1

#1

#2

#2

#2

MCLKO

MCLKI

AO[31:0]

ASX

CSXO[n]

RDXO

DI[31:0]

WRXO[3:0]

DO[31:0]

DC[3:0]

READ

WRITE


166

- WDXO[3:0] is asserted after a delay of MCLKO ↑ from the second bus access cycle. The signal is negated after the wait cycle specified by the W15-W12 bits in the AWR register is inserted.

- The timing to assert RDXO and WRXO[3:0] can be delayed one cycle by setting the W01 bit in the AWR register to "1".

- WEX is fixed at "H" level when the use of WRXO[3:0] has been set as ACR->TYP[3:0] = 0x0xB.

- For read access, the DI[31:0] signals are input at the rising edge of MCLKI in the cycle which a wait cycle is terminated after the assertion of RDXO.

- For write access, data is output to the DO[31:0] pins at the timing at which the WRXO[3:0] signals are asserted.


167

5.7.1.2 WRX+Byte-Control Type (ACR->TYP[3:0]=0010B, AWR=0008H)

- ASX, CSXO[n], RDXO, AO[31:0], DI[31:0], and DO[31:0] behave in the same way as described in Section 5.7.1.1 "Basic timing".

- WEX is asserted from the second bus access cycle. It is negated after the wait cycle specified by the W15-W12 bits in the AWR register is inserted. The timing to assert RDXO and WRXO[3:0] can be delayed one cycle by setting the W01 bit in the AWR register to "1". (This behavior is also the same as WRXO[3:0] described in Section 5.7.1.1 "Basic timing".)

- The WRXO[3:0] signals indicate, as byte enable signals, the byte position to be accessed using negative logic. The signals remains asserted from the bus access start cycle to the bus access end cycle. The status changes at the same timings as addresses. The signals indicate the byte position to be accessed for both read and write accesses.

M C L K O

A O [ 3 1 : 0 ]

A S X

C S X O [ n ] *

R D X O

D I [ 3 1 : 0 ]

W R X O [ 1 : 0 ]

W R X O [ 3 : 2 ]R E A D

W E X

D O [ 3 1 : 0 ]

W R X O[ 1 : 0 ]

W R X O [ 3 : 2 ]

W R I T E

M C L K I

D C [ 1 : 0 ]

D C [ 3 : 2 ]


168

- For write access, data is output to the DO[31:0] pins at the timing at which the WEX signal is asserted.

- To use a mixture of areas specified by ACR->TYP[3:0]=0x0xB (WRX[3:0] used) and TYP[3:0]=0x1xB (WEX+byte control), be sure to make the following settings for all of the areas to be used. (See Section 5.7.7 "Notes on use" for details.)

- Set at least one read-to-write idle cycle.- Set at least one write recovery cycle.


169

5.7.1.3 Read-to-Write Timing (ACR->TYP[3:0]=0000B, AWR=0048H)

- 0 to 3 idle cycles can be inserted depending on the setting of the W07-W06 bits in the AWR register.

- The read-side CS area setting is effective.

- Insert the read-to-write idle cycle when read access is followed by either write access or access to a different area.

MCLKO

AO[31:0]

ASX

CSXO[n]

RDXO

WRXO[3:0]

DI[31:0]

Read WriteIdle *

MCLKI

DO[31:0]

DC[3:0]


170

5.7.1.4 Write-to-Write Timing (ACR->TYP[3:0]=0000B, AWR=0018H)

- 0 to 3 write recovery cycles can be inserted depending on the setting of the W05-W04 bits in the AWR register.

- A recovery cycle is generated following every write cycle.

- The write recovery cycle is also generated when write access is divided by access with the specified bus width or greater.

MCLKO

AO [31:0]

ASX

CSXO[n]

WRXO[3:1]

DO[31:0]

Write WriteWrite recovery *

DC[3:0]


171

5.7.1.5 Automatic Wait Timing (ACR->TYP[3:0]=0000B, AWR=2008H)

- 0 to 15 automatic wait cycles can be inserted depending on the setting (first wait cycle) of the W15-W12 bits in the AWR register.

- In the above example, two automatic wait cycles are inserted, resulting in access in a total of four cycles.

- When an automatic wait cycle is inserted, at least two bus cycles are required (plus the first wait cycle). Write access may require more cycles depending on the internal state.

MCLKO

AO[31:0]

ASX

CSXO[n]

RDXO

DI[31:0]

WRXO[3:0]

DO[31:0]

Basic cycle Wait cycle *

MCLKI

DC[3:0]

READ

WRITE


172

5.7.1.6 External Wait Timing (ACR->TYP[3:0]=0001B, AWR=2008H)

- An external wait cycle can be inserted by setting the TYP0 bit in the ACR register to “1” and enabling the external RDY input pin.

MCLKO

AO[31:0]

ASX

CSXO[n]

RDXO

DI[31:0]

WRXO[n]

DO[31:0]

Basic cycle

RDYI

Wait

Release

MCLKI

DC[3:0]

READ

WRITE

Automatic wait 2 cycles Wait cycle by RDY


173

5.7.1.7 Synchronous Write Enable Output Timing (ACR->TYP[3:0]=0000B, AWR=0000H)

- Enabling synchronous write (AWR: W03 bit = "0") results in the following operations.

- The WRXO[3:0] and WEX pin outputs assert the synchronous write enable output at the timing at which the ASX pin output is asserted. When a write to the external bus is performed, the synchronous write enable output has the "L" level. When a read from the external bus is performed, the synchronous write enable output has the "H" level.

- The external data output pin outputs write data in the clock cycle next to the clock cycle which the synchronous write enable output is asserted. If write data cannot be outputted for reasons of internal bus, the assertion of synchronous write enable output may delay until write data is outputted.

- The read strobe output (RDXO) is used as as an asynchronous read strobe regardless of the WRXO[3:0]/WEX output timing setting. Use it as it is intended for controlling the I/O direction of data.

The synchronous write enable output has the following restrictions on usage.

- Do not make either of the following additional wait settings as it nullifies the synchronous write enable output timing:

- CSX->RDX/WRX setup setting (Always write "0" to the AWR: W01 bit.)

- First wait cycle setting (Always write "0000" to the AWR: W15-W12 bits.)

- Do not make either of the following access type settings (TYPE[3:0] bits (bits 3-0) in the ACR register) as it nullifies the synchronous write enable output timing:

MCLKO

AO[31:0]

ASX

CSXO[n] *

RDXO

DI[31:0]

WRXO[3:0]

DO[31:0]

READ

WRITE

#1 #2

#1 #2

#1 #2

MCLKI

DC[3:0]


174

- Multiplex bus setting (Always write "0" to the ACR->TYPE[2] bit.)

- RDY input enable setting (Always write "0" to the ACR->TYPE[0] bit.)

- For the synchronous write enable output, always set the burst length to 1 (set the BST[1:0] bits to "0").


175

5.7.1.8 CSX Delay Setting (ACR->TYP[3:0]=0000B, AWR=000CH)

- When the W02 bit is "1", the assertion is started at the cycle next to the cycle which ASX is asserted. For succeeding access, a negate period is inserted.

- One setup cycle is inserted before the read/write strobes are asserted after the delayed assertion of CSXO[7:0]. (This operation is equivalent to CSX->RDX/WRX setup setting using the W01 bit in the AWR register.)

MCLKO

AO[31:0]

ASX

CSXO[n]

RDXO

DI[31:0]

WRXO[3:0]

DO[31:0]

READ

WRITE

MCLKI

DC[3:0 ]


176

5.7.1.9 CSX->RDX/WRX Setup and RDX/WRX->CSX Hold Setting (TYP[3:0]=0000B, AWR=000BH)

- A CSX→RDX/WRX setup delay can be set by setting the W01 bit in the AWR register to "1". Set the setup delay to extend the period from chip select assertion to read/write strobe assertion.

- An RDX/WRX→CSX hold delay can be set by setting the W00 bit in the AWR register to "1". Set the hold delay to extend the period from read/write strobe negation to chip select negation. In this case, write data output is also extended for one cycle by setting EDOE bit (bit4) of TCR register to “1”.

- The CSX→RDX/WRX setup delay (using the W01 bit) and RDX/WRX→CSX hold delay (using the W00 bit) can be set separately.

- When the same chip select area is accessed continuously without chip select negation, neither the CSX→RDX/WRX setup delay nor RDX/WRX→CSX hold delay is inserted. Extension cycle of write data output which is set by EDOE bit of TCR register is also not inserted.

- When setup cycle and hold cycle after address assertion, and extension cycle of write data for address assertion are required, set the address→CSX delay setting bit (W02 bit in the AWR register) to "1".

CSX->RDX/WRX RDX/WRX->CSX

TCR[4]=0

TCR[4]=1

MCLKO

AO[31:0]

ASX

CSXO[n]

RDXO

DI[31:0]

WRXO[n]

DO[31:0]

READ

WRITE

MCLKI

DC[3:0]

DO[31:0]

DC[3:0]

Delay Delay


177

5.7.1.10 DMA Fly-By Transfer (I/O-to-Memory) (TYP[3:0]=0000B, AWR=0008H, IOWR=51H)

* No wait cycle setting on the memory side.

- An I/O read cycle can be extended one cycle by setting the HLD bit in the IOWR0-IOWR3 register to "1".

- 0 to 15 wait cycles can be inserted by setting the IW[3:0] bits in the IOWR0-IOWR3 register.

- When the memory side has a wait cycle setting (AWR[15:12] is not "0"), it is compared to the I/O wait cycle setting (IW[3:0] bits) and whichever is greater is used as the number of wait cycles to be inserted.

- The data output enable (DC[3:0]) pins always output the "H" level.

- The data output (DO[31:0]) signals are undefined; the data input (DI[31:0]) signals are not sampled.

Note: DMA fly-by transfer is External IF and Ether MAC IF only.

MCLKO

AO[31:0]

ASX

CSXO[n]

WRXO[3:0]

D[31:0]

IORDX

MCLKI

DC[3:0]=H

DACKX[n]

Basic cycleI/O wait cycle*1

I/O holdwait*2

I/O idle cycle Basic cycle

I/O wait cycle*1

I/O holdwait*2


178

5.7.1.11 Burst Access (First Access Wait Cycle: 1, Page Wait Cycle: 1) (ACR->TYP[3:0]=0000B, AWR=3208H)

- In the external bus interface, continuously transfer blocks of data in one access sequence is referred to as burst access. Regular access cycles other than burst access cycles are called single access. In this context, one access sequence starts from the assertion of ASX and CSXO[7:0] and ends up with the negation of CSXO[7:0]. Blocks of data indicate at least two bus-width units of data, which have been set for the corresponding area.

- Burst cycles can be used to improve the efficiency of access cycles for reading a substantial amount of data, for example, from asynchronous memory or burst flash memory such as page mode ROM, as well as to read data from asynchronous memory as usual.

- The access sequence for a burst cycle consists of two types of cycles;

- First access cycleThis cycle starts the burst access, which the same operations are performed as in an ordinary single access cycle.

- Page access cycleFollowing the first access cycle, this cycle is executed with CSXO[7:0] and RDXO (read strobe) asserted. Wait cycles different from a single cycle can be set. The page access cycle is executed repeatedly within the address boundary determined by the burst length setting. The burst access is completed when access within the address boundary is finished, negating CSXO[7:0].

- The first wait cycle of 0 to 15 wait cycles can be inserted depending on the setting of the W15-W12 bits in the AWR register. The first access cycle consists of, at minimum, a wait cycle plus two cycles (three cycles in the above example).

- 0 to 15 page wait cycles can be inserted depending on the setting of the W11-W8 bits in the AWR register. The page access cycle consists of a page wait cycle plus 1 cycle (two cycles in the above example).

MCLKO

AO[31:0]

ASX(LBAX)

CSXO[n]

RDXO

WRXO[3:1]

DI[31:0]

BAAX

MCLKI

First cycle wait*1

In-page access wait*2

In-page access wait

In-page access wait


179

- The burst length can be set to 1, 2, 4, or 8 depending on the setting of the BST bits in the ACR register. Setting the burst length to 1 causes single access, where only the first cycle is repeated. If you select a data bus width of 32 bits (by setting the BST bits in the ACR register to "10B"), however, set the burst length to 4 or less (setting it to 8 results in malfunction).

- When burst access has been enabled, it is performed it at prefetch access or transfer with the data size that is greater than the specified data bus width. For word access to an area which a data bus width of 8 bits and a burst length of 4 have been set, perform one 4-burst access instead of four byte accesses.

- The LBAX and BAAX signals are dedicated to burst flash memory; LBAX indicates the beginning of access and BAAX indicates an address increment.

- AO[31:0] are updated after the wait cycle set during burst access.


180

5.7.2 Prefetch

5.7.2.1 Function OverviewThe external bus interface controller incorporates a prefetch buffer consisting of "8 bits x 16 lines".When the PSUS bit in the TCR register is "0" and read access is generated to an area which the PFEN bit in the ACR register has been set ("1"), the external bus interface controller prefetches data from the following addresses into the prefetch buffer.When internal bus access occurs to such an address, the control returns the corresponding data prefetched into the prefetch buffer without performing external access. This contributes to the reduction in wait time for successive accesses to external bus areas.

(1) Fundamental conditions for starting external access for prefetchExternal bus access is performed for prefetch when the following conditions are satisfied: - The PSUS bit in the TCR register is "0".- Not in the sleep or stop mode.- External bus read access to a prefetch-enabled chip select area is requested. Note that it must not be

DMA access to area other than SDRAM area and read access by a read modify write instruction. Prefetch is performed at DMA access to SDRAM area.

- Any external bus access request (such as external bus area access to a prefetch-disabled area or DMA transfer to an external bus area) other than the prefetch access request has not been generated.

- That part of the prefetch buffer is empty, which is used to store data to be obtained by the next prefetch access.

Prefetch access lasts as long as the above conditions are satisfied. Even when external bus area access to a prefetch-disabled area is generated after prefetch access, the prefetch access to prefetch-enabled areas is performed continuously unless a prefetch buffer clear condition develops.When accesses are performed to both prefetch-enabled areas and prefetch-disabled areas, the prefetch buffer always prefetches data from the prefetch-enabled area accessed last to hold that data. Since any access to a prefetch-disabled area does not affect the state of the prefetch buffer at all, data access to prefetch-disabled areas and instruction fetch from prefetch-enabled areas can coexist without wasting data in the prefetch buffer.

(2) Suspending and clearing prefetch accessSetting the PSUS bit to “1” in the TCR register suspends prefetching. Setting the PSUS bit to "0" restarts it. The buffer retains its contents in this period unless a buffer clear event occurs, such as a buffer miss or setting the PCLR bit.Setting the PCLR bit in the TCR register to "1" clears the entire prefetch buffer. Before clearing the buffer, set the PSUS bit to suspend prefetching.Execution of prefetch is stopped temporarily for each boundary whose upper 16 bits of the address vary, or the minimum unit (64 kilobytes) of a hip select area. When the boundary is exceeded, a buffer read miss occurs temporarily. After that, the prefetch buffer restarts prefetch from a new area.In the area which SDRAM/FCRAM is connected, the execution of prefetch is stopped temporarily if the bank address is overed. When an access is performed to new bank address, the execution of prefetch is started by the following new bank addresses if a buffer read miss occurs. In addition, in the area which SDRAM/FCRAM is connected, when a page miss is occurred with writing to the area that is performing prefetch, or an address is performed to another SDRAM/FCRAM area that the prefetch is not enabled, the prefetch is stopped temporarily even if the page address is updated.


181

(3) Unit of prefetch access

The unit of data to be handled by a single prefetch access is determined by the DBW bits (bus width setting) and BST bits (burst length setting) in the ACR register.Prefetch access is performed always in the size of the full bus width set by the DBW bits. The access is executed the number of times corresponding to the burst length set by the BST bits at one time. That is, when the values other than "00B" are set to BST bits, prefetch access is performed always in page mode or burst mode. Pay attention to unsupported ROM/RAM or access time running out (set the W15 to W08 bits in the AWR register to appropriate values for wait cycle settings).In burst access mode, continuous access is performed only within the address boundary dependent on the burst length. Even when the buffer has four bytes of free space, for example, four bytes of data cannot be accessed at one time if that space lies across a boundary. (Assume that the prefetch buffer starts at xxxxxx0EH and has four bytes of free space and that the burst length is 16 bits. When two bursts are set in this case, the next prefetch access can obtain only two bytes at xxxxxx0EH and xxxxxx0FH.)Examples: - A bus width of 16 bits and a burst length of 2 have been set for the area.

-> The amount of data read into the prefetch buffer by a single prefetch is four bytes.In this case, prefetch access is not performed until the prefetch buffer is refreshed to have four bytes of free space.

- A bus width of 8 bits and a burst length of 8 have been set for the area.-> The amount of data read into the prefetch buffer by a single prefetch is eight bytes.

In this case, prefetch access is not performed until the prefetch buffer is refreshed to have eight bytes of free space.

(4) Burst length setting and prefetch efficiencyEven though either an external bus access request other than prefetch access or a prefetch buffer miss occurs when a single prefetch access is being executed as described in (3) above, the access request waits until the current prefetch buffer access is completed.Setting the burst length to a too large value lowers the efficiency and response of bus access other than prefetch. Setting the burst length to 1, in contrast, always causes single access to be performed even with burst or page access memory connected, wasting many read cycles.When the size of data to be read by a single prefetch access has been set to to a large value, prefetch access cannot be started until the prefetch buffer is refreshed to have that size of free space. When access to the prefetch buffer is performed infrequently, therefore, the external bus easily becomes idle. When a bus width of 16 bits and a burst length of 8 are set, for example, the amount of data read into the prefetch buffer by a single prefetch is 16 bytes. In this case, the entire prefetch buffer must become empty before another prefetch access can be performed.Taking into account these conditions, optimize the burst length setting depending on the actual operating environment. When asynchronous memory which cannot accept burst/page access is connected, in general, the optimum burst length setting is 1 (single access).When small memory such as SDRAM burst/page access cycle is connected, the optimum burst length setting is except “1” (single access). In this case, the optimum setting is read 8 bytes data (half of the buffer) at one time according to the bus width. However, depending on the frequency of external access and the clock division setting of external access clcok, the condition may change.

(5) Reading from the prefetch bufferWhen the internal bus accesses the prefetch buffer, data stored in the prefetch buffer is read if the requested address matches the data, eliminating the need for external access. When a buffer is read forward, a reference to the buffer can result in a hit (up to 16 bytes) even though addresses are not consecutive. The buffer is therefore structured to prevent read access to the external bus from recurring even when a short forward branch is encountered.


182

When access from the internal bus matches the address being referenced by the current prefetch, the interface controller returns a wait state to the internal bus until the corresponding data is obtained after completion of the prefetch access. This case is not regarded as a buffer miss.When read access during DMA transfer matches an address in the prefetch buffer, the interface controller reads target data from the external bus without using the data in the prefetch buffer. Although this case is regarded as a buffer miss, prefetch is not continued and prefetch access is not performed until new external access is performed to a prefetch-enabled area.

(6) Clearing and updating the prefetch bufferThe entire prefetch buffer is cleared when any of the following conditions is satisfied:

- "1" is written to the PCLR bit in the TCR register.- A buffer read miss (described later) occurs.- A buffer write hit (described later) occurs.

The prefetch buffer is partly cleared when the following condition is satisfied:- A buffer read hit occurs. In this case, only the buffers before the hit address are cleared.

Buffer read misses indicate the following cases:- Read access to a prefetch-enabled area does not match any of the addresses held in the prefetch

buffer. In this case, new access is performed to the external bus. Although the data read at this time is not stored in the buffer, prefetch access is started from the next address to store data to the buffer.

- Read access performed to a prefetch-enabled area is requested by a read modify write instruction. In this case, new access is performed to the external bus. The data read at this time is not stored in the buffer and prefetch access is not started (because a writing is executed after that).

- Read access to a prefetch-enabled area is performed during DMA access to area other than SDRAM area. In this case, new access is performed to the external bus. The data read at this time is not stored in the buffer and prefetch access is not started. Prefetch access is performed at DMA transfer to SDRAM area.

A buffer write indicates the following case:- When write access to a prefetch-enabled area matches even one byte of addresses in the buffer, in

this case, although new access is performed to the external bus in this case, prefetch access is not performed until new read access is performed.

(7) Restriction on prefetch-enabled areasWhen accessing a prefetch-enabled little endian area, be sure to use word access. When data read into the prefetch buffer is accessed not in word length, endian conversion is not performed correctly and wrong data is read. This is traceable to a hardware restriction of the endian conversion mechanism.


183

5.7.3 SDRAM/FCRAM InterfaceCS6, CS7 area can be used as SDRAM/FCRAM area by setting TYP[3:0] bit in ACT register to “100xB”.

5.7.3.1 Timing Chart

5.7.3.1.1 Burst Read/Write (Page Hit, CAS Latency=2)

• Depends on the capacity of SDRAM, AO[13:0] may not use all the pins. Refer to connection example.

• MCLK is a clock to be input to SDRAM. Address, data, and command signals are fetched to SDRAM at the rising edge of MCLK.

• Set the write recovery cycle by referring the SDRAM/FCRAM standard by W05-W04 bits in AWR register.

• Set the CAS latency by referring the SDRAM/FCRAM standard by W10-W08 bits in AWR register.

• Set the burst length by using BST bit in ACR register.

5.7.3.1.2 Single Read/Write (Page Hit, CAS Latency=3, without Auto Precharge)

• Set the read→write idle cycle by referring the SDRAM/FCRAM standard by W07-W06 bits in AWR register.

#1

#1#1

#1 #3 #4

#2 #3 #4

#2

MCLK

AO[13:0]

DO[31:0]

DI[31:0]

SRASX, SCASX,SWEX

READWRITE

Write cycle

Write recovery Cas Latency

Read cycle

#1

#1

#1#1

MCLK

AO[13:0]

DO[31:0]

DI[31:0]

SRASX, SCASX,SWEX

READ WRITE

Write cycle

Cas Latency

Read cycle

Read->Writeidle cycle


184

5.7.3.1.3 Single Read (Page Miss, CAS Latency=3, without Auto Precharge)

• When a page miss is occurred, reading is performed after the issue of PRE charge command and ACTV command.

• Set the RAS precharge cycle (tRP) by referring the SDRAM/FCRAM standard by W01-W00 bits in AWR register.

• Set the RAS to CAS delay (tRCD) by referring the SDRAM/FCRAM standard by W14-W12 bits in AWR register.

5.7.3.1.4 Single Read/Write (CAS Latency=1, TYP=1001B, with Auto Precharge)

• When TYP=1001B is set, read/write command with auto precharge is issued. However, the cycle from the issue of READA/WRITA to the issue of ACTV, is fixed at CL+BL-1, so TYP=1001B can be set only when FCRAM is connected.

• Due to there is no cycle to issue PRE command, single read/write is effective when page miss frequently occurs.

Row #1

ACT

#1

READ

RAS

PRE

BA

MCLK

AO[13:0]

DI[31:0]

SRASX, SCASX,SWEX

RAS precharge cycle(tRP)

RAS->CAS delay(tRCD) Cas Latency

MCLK

AO[13:0]

DO[31:0]

DI[31:0]

SRASX, SCASX,SWEX

Row Col Row Col Row Col

#1 #3

#2

ACTV WRITA ACTV READA ACTV WRITA

CL+BL-1CL+BL-1 Read write

idle cycle


185

5.7.3.1.5 Auto Refresh

• Refresh command is issued at every RFINT5-0 x 32 cycle of RCR register, access restarts after the refresh is completed.

• Set the TRC bit in RCR register by referring the SDRAM/FCRAM standard.

5.7.3.2 Self RefreshSDRAM/FCRAM starts the sequence after the self refresh by writing SELF bit in refresh control register (RCR) to “1”. After SDRAM/FCRAM interface executes the auto refresh that is specified by RFC[2:0], SELF command is issued for SDRAM/FCRAM, and a transition to self refresh mode is started.

To release self refresh mode, write SELF bit to “0” or perform read/write access to SDRAM/FCRAM.

Writing “0” to SELF bit or detecting access to SDRAM/FCRAM in self refersh mode, SDRAM/FCRAM interface issues SELFX command, and executes the auto refresh that is specified by RFC[2:0].

Therefore, after self refresh mode is set and the chip is entered to sleep mode, self refresh mode is released if performing access to SDRAM/FCRAM by DMA transfer.

<After self refresh mode>

(1) Set SELF bit to “1”.

(2) Issue REF command as RFC[2:0] specified.

(3) Issue SELF command.

<Release self refresh mode>

(1) Set SELF bit to “0” or perform access to SDRAM/FCRAM.

(2) Issue SELFX command.

(3) Issue REF command as RFC[2:0] specified.

(4) Shift to normal access state.

MCLK

AO[31:0]

DC[3:0]

SRASX, SCASX,SWEX

"H"

REF ACTV

tRC

Refresh cycle


186

5.7.3.3 Power SequencePower on sequence is started by setting PON bit in refresh control register (RCR) to “1”.

Set PON bit to “1” and shift to power on sequence as the following instructions.

(1) Assure the clock stable wait time as the description of SDRAM/FCRAM manual.

(2) Set ACR, AWR, MCRA(B).

(3) Set CSER and enable the area that is connected to SDRAM/FCRAM.

(4) Set the value in RCR and set PON bit to “1” at the same time.

By executing the instructions as above, SDRAM/FCRAM executes the following power sequence.

(5) Execute REF command for 8 times.

(6) Perform mode register set according to BST bit in ACR, CL (CAS Latency) in AWR, and WBST bit in MCRA.

(7) Shift to normal access state.

5.7.3.4 SDRAM/FCRAM Connection for Multiple AreaSDRAM/FCRAM setting is possible in CS6X, CS7X area, connect the same type if SDRAM/FCRAM is connected to two areas simultaneously. Concretely, connect the common address data bus to the following register settings.

(1) ACR register: DBW[1:0], BST[1:0], TYP[3:0] setting should be the same.

(2) AWR register: all the bits should be the same.

(3) MCR register: all the settings should be the same since the register is shared.

(4) RCR register: all the settings should be the same since the register is shared.

In addition, power sequence/auto refresh/self refresh are performed simultaneously if two areas are enabled at the same time.

5.7.3.5 Address Multiplex • FormatFor the access address to SDRAM/FCRAM, according to the setting of ASZ[3:0] bit, DBW[1:0] bit, PSZ[2:0] bit, BANK bit, the correspondence for row address, bank address, and column address may change. The correspondence for address is allocated from the lower bit, column address, bank address, and row address in that order.Set the bits as follow:

• ASZ[3:0] Set the total capacity of SDRAM/FCRAM that is connected to the corresponding area. Set the total capacity if two addresses are parallel used. It is affected to the number of row address.

• DBW[1:0] Set the data bus width (set to 16 bit when two 8 bit products are parallel used). Shift the column address according to the data bus width specification.

8 bit: unchanged. 16 bit: 1 bit shift. 32 bit: 2 bit shift.

• PSZ[2:0] Set the number of column address that is used by SDRAM/FCRAM.

• BANK Set the number of bank address of SDRAM/FCRAM.


187

Examples of access address between row address, bank address, column address

(1) 4Mbyte (ASZ=0110B), 8bit bus width (DBW=00B), 256 columns (PSZ=000B), 2 banks (BANK=0B)



A31 A22 A21 A9 A8 A7 A0

A31 A24 A23 A12 A11 A10 A9 A1 A0

A31 A26 A25 A13 A12 A11 A10 A1 A0A2ROW BA Column

ROW BA Column

ROW BA Column


188

5.7.3.6 Memory Connection Example

5.7.3.6.1 When 8-bit SDRAM/FCRAM is Used (Big Endian)

SDRAM/FCRAM interface pin SDRA/FCRAM pin Remarks

MCLKO CLK

MCLKE CKE

SRASX(ASX) RAS

SCASX(BAAX) CAS

SWEX(WEX) WE

CSXO[7] or CSXO[6] CS SDRAM/FCRAM setting is possible in CS6/CS7 only.

AO[9:0] A9-A0

AO[10]/AP A10/AP A10 is output when this pin is used as row addressoutput; otherwise, AP is output.

AO[13:11] A13-A11 Connect to the address that is used by SDRAM/FCRAM

AO[14] BA[0] 2BANK product: BA

AO[15] BA[1] 2BANK product is not used

D[31:0] DQ Connection is changed according to endian and databus width. For the details, see 5.6 “Bus operation”.

DQMUU(WRXO[0]),DQMUL(WRXO[1]),DQMLU(WRXO[2]),DQMLL(WRXO[3])

DQM Connection is changed according to endian and databus width. For the details, see 5.6 “Bus operation”.

CSX[6] orCSX[7] A13-A0

SRASX (ASX)

SCASX(BAAX)

SWEX(WEX) MCLKE

DQMUU(WRX[0])DQMUL

(WRX[1])DQMLL(WRX[3])

DQMLU(WRX[2])

MCLK D31-0

CS

CS

CS

CS

IA13-IA0

IA13-IA0

IA13-IA0

IA13-IA0

RAS CAS WE CKE DQM

RAS CAS WE CKE DQM

RAS CAS WE CKE DQM

RAS CAS WE CKE

CLK DQ7-DQ0

CLK DQ7-DQ0

CLK DQ7-DQ0

CLK DQ7-DQ0DQM

[31-24]

[23-16]

[15-8]

[7-0]

LSI in this macro

SDRAM(No.1)

SDRAM(No.4)

SDRAM(No.3)

SDRAM(No.2)


189

5.7.3.6.2 When 16-bit SDRAM/FCRAM is Used

Total data width 32 bit. . .use two or four SDRAM.

Total data width 16 bit. . .use one SDRAM.

When SDRAM with 64M bit capacity is used, (two bank addresses, twelve low addresses) are indicated.

• When data width 16 bit is used, SDRAM No.2, No.3, No.4 are unnecessary, leave DQ15~0, DQM1~0 open.

• When two SDRAM are used, SDRAM No.2, No.3 are unnecessary.

CSX[7] CSX[6] A13-A0SRASX (ASX)

SCASX(BAAX)

SWEX(WEX) MCLKE

DQMUU(WRX[0])DQMUL


DQMLU(WRX[2])

MCLKO D31-0

CS IA13-IA0 RAS CAS WE CKE DQMU DQML

RAS CAS WE CKE DQMU DQML

CLK DQ15-DQ0

CLK DQ15-DQ0

CLK DQ15-DQ0

CLK DQ15-DQ0

[31-16]

[15-0]

[31-16]

[15-0]

LSI in this macro

SDRAM(No.1)

SDRAM(No.4)

SDRAM(No.3)

SDRAM(No.2)CS

CS

CS

IA13-IA0

IA13-IA0

IA13-IA0




190

5.7.3.6.3 When 32-bit SDRAM is Used

Total data width 32 bit. . .use one or two SDRAM.

When SDRAM with 64M bit capacity, (one bank addresses, twelve low addresses) are indicated.

When only one SDRAM is used, SDRAM No.2 is unnecessary.

CS7X CS6X A12-A0SRASX (ASX)

SCASX(BAAX)

SWEX(WEX) MCLKE

DQMUU(WRX[0])DQMUL


DQMLU(WRX[2])

MCLK D31-0

LSI in this macro

CS IA12-IA0 RAS CAS WE CKE DQM3 DQM2 DQM1 DQM0 CLK DQ31-DQ0

SDRAM(No.1)

SDRAM(No.2)

CS IA12-IA0 RAS CAS WE CKE DQM3 DQM2 DQM1 DQM0 CLK DQ31-DQ0

[31-0]

[31-0]


191

5.7.4 Register Setup ProcedureWhen carrying out setup procedures for the external bus interface, following the principles summarized below.

(1) Before updating the contents of registers for a chip select area, be sure to set the corresponding bit in the CSER register to "0" to disable that area. If register settings are changed with the CSE bit is "1", the results of access to the area before and after making the changes are unpredictable.

(2) Follow the procedure below to update registers for a chip select area.1) Set the corresponding bit in the CSER register to "0".2) Set the ASR and ACR at the same time by word access.3) Set the AWR.4) Set the corresponding bit in the CHER.5) Set the corresponding bit in the CSER.

(3) The CSX[0] area is enabled immediately after a reset. If the area has been used as a program area, the registers must be updated with "1" held in the CSER. In this case, take steps 2) to 4) in the initial state in which the internal clock speed is low. After that, switch the clock to a faster one.

(4) Follow the procedure below to change register values for a prefetch-enabled area.1) Set the corresponding bit in the CSER register to "0".2) Set both of the PSUS and PCLR bits in the TCR register to "1".3) Set the ASR and ACR at the same time by word access.4) Set the AWR.5) Set the corresponding bit in the CHER.6) Set both of the PSUS and PCLR bits in the TCR register to "0".7) Set the corresponding bit in the CSER to “1”.


192


209

CHAPTER 6 PERIPHERAL RESOURCES

6.1 Interrupt Controller

6.1.1 OverviewThe interrupt controller manages interrupt reception and arbitration.

Hardware configuration

This module consists of the following components:

• ICR registers• Interrupt priority evaluation circuit• Interrupt level and interrupt number (vector) generator• Hold request to cancel request generator

Main functions

This module has the following functions:

• NMI/interrupt request detection• Priority evaluation (by level and number)• Transfer of interrupt level (to CPU)• Transfer of interrupt number (to CPU)• Request for return from stop mode in response to NMI or interrupt request with interrupt level other

than "11111" (to CPU)• Hold request cancel request to bus master.


210

6.1.2 Register list

Address bit 7 6 5 4 3 2 1 0

00000440 H ⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ICR00










0000044A H ⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ICR10

0000044B H ⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ICR11

0000044C H ⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ICR12

0000044D H ⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ICR13

0000044E H ⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ICR14

0000044F H ⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ICR15

















R R/W R/W R/W R/W


211

Address bit 7 6 5 4 3 2 1 0

















R R/W R/W R/W R/W

00000045 H MHALTI LVL4 LVL3 LVL2 LVL1 LVL0 HRCL

R/W R R/W R/W R/W R/W


212

6.1.3 Block Diagram

Figure INTC-1 Block diagram

HLDREQ

cancel

request

R-BUS

6

/

5

/

WAKEUP (LEVEL = 11111: " 1 ")UNMI

Priority

LEVEL4 to

LEVEL0

MHALTI

VCT5 to VCT0

NMI

servicing

Level/vecto

r gen

era

tio

n

RI00

RI47

(DLYIRQ)

Vector

evaluation

Level

evaluation

ICR00

ICR47

..

.

..

.


213

6.1.4 Register description(1) ICR (Interrupt Control Register)

The interrupt control register (ICR) is provided for each interrupt input and is used to set the interrupt level of the corresponding interrupt request.

[Bits 4-0] ICR4-ICR0

These bits are used to specify the interrupt level of the corresponding interrupt request.

If the interrupt level set in this register is higher than the level mask value set in the ILM register in the CPU, an interrupt request is masked on the CPU side.

The register is initialized to 11111B at a reset.

Table INTC-1 below lists the combinations of values of the interrupt level setting bits and their respective interrupt levels.

Table INTC-1

The ICR4 bit is fixed at “1”; it can not be set to “0.”

bit 7 6 5 4 3 2 1 0 Initial value

⎯ ⎯ ⎯ ICR4 ICR3 ICR2 ICR1 ICR0 ---11111

R R/W R/W R/W R/W

ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level

0 0 0 0 0 0 Reserved by the system

0 1 1 1 0 14

0 1 1 1 1 15 NMI

1 0 0 0 0 16 Highest level acceptable

1 0 0 0 1 17 (High)

1 0 0 1 0 18

1 0 0 1 1 19

1 0 1 0 0 20

1 0 1 0 1 21

1 0 1 1 0 22

1 0 1 1 1 23

1 1 0 0 0 24

1 1 0 0 1 25

1 1 0 1 0 26

1 1 0 1 1 27

1 1 1 0 0 28

1 1 1 0 1 29

1 1 1 1 0 30 (Low)

1 1 1 1 1 31 Interrupt disabled


214

(2) HRCL (Hold Request Cancel Level register)

This register is used to set the interrupt level for issuing a hold request cancel request.

[Bit 7] MHALTI

This bit suppresses DMA transfer by an NMI request. The bit is set to "1" by an NMI request; writing "0" to the bit clears it. Clear the bit at the end of the NMI routine in the same way as an ordinary interrupt routine.

[Bits 4-0] LVL4-LVL0

These bits are used to set the interrupt level for issuing a hold request to cancel request to the bus master.

If an interrupt request having a higher level than that set in this register is generated, a hold request cancel request is issued to the bus master.

The LVL4 bit is fixed at "1"; it cannot be set to "0".

6.1.5 Descriptions of operation(1) Priority evaluation

This module selects the interrupt source of the highest priority from among the interrupt sources occurring at the same time and outputs that interrupt level and interrupt number to the CPU.

The criteria for evaluating the priorities of interrupt sources are as follows:

1) NMI

2) Interrupt sources satisfying the following conditions:

• Interrupt sources with an interrupt level value other than 31. ("31" disables interrupts.)• Interrupt sources with the smallest interrupt level value• Interrupt source with the smallest interrupt number among above

If no interrupt source is selected according to the above criteria, the interrupt controller outputs an interrupt level of 31 (11111B) and an undefined interrupt number.

Table INTC-3 lists interrupt sources, interrupt numbers, and interrupt levels.

Bit7 6 5 4 3 2 1 0

Address:00000045 H MHALTI - - LVL4 LVL3 LVL2 LVL1 LVL0 HRCL

R/W R R/W R/W R/W R/W0—11111

(Initial value)


215

Table INT-3Interrupt source Interrupt No. Interrupt

levelOffset TBR default

addressRN

Dec Hex

Reset 0 00 - 3FCH 000FFFFCH -

Mode vector 1 01 - 3F8H 000FFFF8H -

Reserved by the system 2 02 - 3F4H 000FFFF4H -

Reserved by the system 3 03 - 3F0H 000FFFF0H -

Reserved by the system 4 04 - 3ECH 000FFFECH -

Reserved by the system 5 05 - 3E8H 000FFFE8H -

Reserved by the system 6 06 - 3E4H 000FFFE4H -

Coprocessor absence trap 7 07 - 3E0H 000FFFE0H -

Coprocessor error trap 8 08 - 3DCH 000FFFDCH -

INTE instruction 9 09 - 3D8H 000FFFD8H -

Instruction break exception 10 0A - 3D4H 000FFFD4H -

Operand break trap 11 0B - 3D0H 000FFFD0H -

Step trace strap 12 0C - 3CCH 000FFFCCH -

NMI request (tool) 13 0D - 3C8H 000FFFC8H -

Undefined instruction exception 14 0E - 3C4H 000FFFC4H -

NMI request 15 0F Fixed at F H 3C0H 000FFFC0H -

External interrupt 0 16 10 ICR00 3BCH 000FFFBCH 4

External interrupt 1 17 11 ICR01 3B8H 000FFFB8H 5



External interrupt 4 20 14 ICR04 3ACH 000FFFACH -




Reload timer 0 24 18 ICR08 39CH 000FFF9CH 6

Reload timer 1 25 19 ICR09 398H 000FFF98H 7

Reload timer 2 26 1A ICR10 394H 000FFF94H -

UART0 (Reception complete) 27 1B ICR11 390H 000FFF90H 0

UART1 (Reception complete) 28 1C ICR12 38CH 000FFF8CH 1

UART0 (Transmission complete) 29 1D ICR13 388H 000FFF88H 2

UART1 (Transmission complete) 30 1E ICR14 384H 000FFF84H 3

DMAC0 (Termination, Error) 31 1F ICR15 380H 000FFF80H -

DMAC1 (Termination, Error) 32 20 ICR16 37CH 000FFF7CH -

DMAC2 (Termination, Error) 33 21 ICR17 378H 000FFF78H -



Reserved by the system 36 24 ICR20 36CH 000FFF6CH -

Reserved by the system 37 25 ICR21 368H 000FFF68H -





Reserved by the system 42 2A ICR26 354H 000FFF54H -

Reserved by the system 43 2B ICR27 350H 000FFF50H -

Reserved by the system 44 2C ICR28 34CH 000FFF4CH -

U-TIMER0 45 2D ICR29 348H 000FFF48H -

U-TIMER1 46 2E ICR30 344H 000FFF44H -

Time-base timer overflow 47 2F ICR31 340H 000FFF40H -


216

(Continued)

(2) Non maskable interrupt (NMI)NMIs have the highest priority among the interrupt sources handled by this module.An NMI is always selected whenever other types of interrupt sources occur at the same time.

If an NMI occurs, the interrupt controller passes the information to the CPU:- Interrupt level: 15 (01111B) - Interrupt number: 15 (001111B)

NMI detectionNMIs are set and detected by the external interrupt/NMI controller. This module only generates an interrupt level, interrupt number, and MHALTI upon NMI request.

Suppressing DMA transfer upon NMI requestWhen an NMI request occurs, the MHALTI bit in the HRCL register is set to "1", suppressing DMA transfer. To permit DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.

Interrupt source Interrupt No. Interrupt level

Offset TBR default address

RN

Dec Hex











Reserved by the system 58 3A ICR42 314H 000FFF14H -

Reserved by the system 59 3B ICR43 310H 000FFF10H -

Reserved by the system 60 3C ICR44 30CH 000FFF0CH -

Reserved by the system 61 3D ICR45 308H 000FFF08H -

Reserved by the system 62 3E ICR46 304H 000FFF04H -

Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H -

Reserved by the system(used by REALOS *1)

64 40 - 2FCH 000FFEFCH -

Reserved by the system(used by REALOS *1)

65 41 - 2F8H 000FFEF8H -

Reserved by the system 66 42 - 2F4H 000FFEF4H -

Reserved by the system 67 43 - 2F0H 000FFEF0H -

Reserved by the system 68 44 - 2ECH 000FFEECH -

Reserved by the system 69 45 - 2E8H 000FFEE8H -



Reserved by the system 72 48 - 2DCH 000FFEDCH -

Reserved by the system 73 49 - 2D8H 000FFED8H -

Reserved by the system 74 4A - 2D4H 000FFED4H -

Reserved by the system 75 4B - 2D0H 000FFED0H -

Reserved by the system 76 4C - 2CCH 000FFECCH -

Reserved by the system 77 4D - 2C8H 000FFEC8H -

Reserved by the system 78 4E - 2C4H 000FFEC4H -

Reserved by the system 79 4F - 2C0H 000FFEC0H -

Used by INT instruction

80to

255

50toFF

-2BCH

to000H

000FFEBCH

to000FFC00H

-


217

(3) Hold request cancel request

When a high-priority interrupt needs to be performed when the CPU has been put on hold, it is necessary to request the hold request issuer to cancel the hold request. Use the HRCL register to set the interrupt level as the reference level for generating a hold request to cancel request.

Conditions for generating a hold request to cancel request

A hold request cancel request is issued when an interrupt source of a higher interrupt level than that set in the HRCL register occurs.

Interrupt level set in HRCL register > Interrupt level after priority evaluation → Cancel request

Interrupt level set in HRCL register ≦ Interrupt level after priority evaluation → No cancel request

Once issued, the cancel request remains in effect until the interrupt source causing that request is cleared. As a result, the DMA transfer remains pending. Therefore, be sure to clear the interrupt source.

When an NMI is used, the MHALTI bit in the HRCL register is "1" and thus the cancel request is in effect.

Selectable Interrupt levels for generating a hold request cancel request

The HRCL register accepts a value from 10000B to 11111B like the ICR register.

If the HRCL register is set to "11111B", a cancel request is issued for every level of interrupt. If it is set to "10000B", a cancel request is issued for NMIs only.

Table INTC-4 lists the interrupt levels set in the HRCL register and the interrupt levels for which a can-cel request is generated.

Table INTC-4

When a reset occurs, suppress DMA transfer for any level of interrupt. When an interrupt occurs, DMA transfer is not executed. So, set the HRCL register to an appropriate value.

(4) Return from standby mode (stop or sleep mode)

This module provides the function to return from stop mode when an interrupt request occurs. If even one interrupt request (with an interrupt level of 11111 or higher), including an NMI, occurs from a peripheral resource, this module issues a request to the clock control unit to return from stop mode.

Since the priority evaluation circuit does not restart operation until the clock supply recovers after returning from the stop mode, the CPU continues to execute instructions until an priority evaluation result is obtained.

Even after returning from the sleep state, this module operates in the same way.

Note also that the registers in this module are accessible even in sleep mode.

HRCLregister Cancel-applicable interrupt level

16 NMI only

17 NMI or interrupt level 16

18 NMI or interrupt level 16 or 17

~ ~

31 NMI or interrupt levels 16 to 30 (Initial value)


218

Precautions

• Even an NMI request causes return from the stop mode. This assumes an appropriate NMI setting to detect a valid input in the stop state.

• To prevent an interrupt source from causing return from the stop or sleep state, use the relevant control register of the corresponding peripheral resource to set the interrupt level to 11111.

(6) Example of using the hold request cancel register (HRCR)

To execute a high-priority process during DMA transfer, the CPU must request the DMA controller to cancel the hold request for releasing itself from the hold status. That is, the HRCR can use an interrupt to make the DMA controller to cancel a hold request, or to give priority to the CPU.

Control registers

1) Hold request cancel level (HRCL) register: This module

If an interrupt request of a higher level than that set in this register is generated, a hold request cancel request is issued to the DMA controller. This register is used to set the reference level.

2) Interrupt control register (ICR): This module

A higher level than that in the HRCL register should be set in the ICR register corresponding to the interrupt source to be used.


219

Hardware Configuration

The flow of each signal is illustrated below.

Sequence

Figure INTC-2 Interrupt Level: HRCL > a

If an interrupt request is generated and the interrupt level becomes higher than that set in the HRCL register, MHALTI becomes active to the DMA controller. Then the DMA controller cancels the access request, allowing the CPU to return from the hold status for servicing the interrupt.

Given below is an example of handling multiple interrupts.

Figure INTC-3 Interrupt Level: HRCL > a > b

Example of interrupt routine1), 3): Interrupt source clearto2), 4): RETI

In the above example, an interrupt of a higher priority occurs during execution of interrupt routine I. DHREQ remains low when an interrupt of a higher level than the interrupt level set in the HRCL register has been generated.

Precaution Pay attention to the relationship between the interrupt level set in the HRCL register and that set in the

ICR.

This module Bus access request

IRQ MHALTI DHREQ DHREQ: D-bus hold

request

I-UNIT DMA B-UNIT CPU DHACK: D-bus hold

acknowledge

(ICR) IRQ: Interrupt request

(HRCL) DHACK MHALTI: Hold request

cancel request

MHALTI

LEVEL

IRQ

DHACK

DHREQ

Bus access

request

CPU

B us holdR UN

Example of interrupt

routine

2) RETI

to

1) Interrupt request claer

B us hold (DMA transfer)Interrupt service

MHALTI

LEVEL

IRQ2

DHACK

DHREQ

Bus access

request

CPU

Bus holdRUN Bus hold (DMA transfer)Interrupt IInterrupt II

4) 2)1)3)

Interrupt I

IRQ1


220

6.2 External Interrupt/NMI Controller

6.2.1 OverviewThe external interrupt/NMI controller is the block for controlling external interrupt requests input to the NMIX and INT[7:0] pins.

The request detection level can be selected from among: H, L, rising edge, and falling edge (except for NMIs).

6.2.2 Register list

6.2.3 Block diagram

Figure EINT-1 Block Diagram

7 6 5 4 3 2 1 0 Enable interrupt request register

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (ENIR)

15 14 13 12 11 10 9 8 External interrupt request register

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (EIRR)

15 14 13 12 11 10 9 8 External level register

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (ELVR)

7 6 5 4 3 2 1 0

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

Enable interrupt request registerInterrupt

request

R BUS

Gate

Interrupt request register

Interrupt sourceF/F

External level register

Edge detection circuit

8

9

8

8

INT[7:0]

NMIX

9


221

6.2.4 Register description(1) ENable Interrupt request Register (ENIR)

[R/W]

The enable interrupt request register (ENIR) controls the masking of external interrupt request outputs. When a bit in this register is set to "1", the corresponding interrupt request output is enabled (for example, INT[0] enabled under control of EN0) and an interrupt request is output to the interrupt controller. When a bit in this register is set to "0", the corresponding pin holds an interrupt source but no request is issued to the interrupt controller.

Note that the register has no mask bit for NMIs.

(2) External Interrupt Request Register (EIRR)

[R/W]

The external interrupt request register (EIRR) indicates the presence of an external interrupt request at each output pin when read. When written, this register clears the value of the flip-flop (NMI flag) indicating the request. If a value of "1" is read from a bit in this register, there is an external interrupt request to the pin corresponding to that bit.

When "0" is written to a bit in this register, the request flip-flop of that bit is cleared. Writing "1" has no effect.

Reading a bit in this register using a read modify write instruction always returns "1".

Note that the user cannot read or write the NMI flag.

*: For the NMI flag, see Figure EINT-5 in (5) "NMI in Section 5.

bIt 7 6 5 4 3 2 1 0 Initial value

ENIR Address:000041 H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000


EIRR Address:000040 H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000


222

(3) External LeVel Register (ELVR)

[R/W]

The external level register (ELVR) is used to select the request detection level. A pair of bits is allocated to each from INT0 to INT7 as shown in Table EINT-1. If a request input level is active even after each bit in the EIRR is cleared, the corresponding bit is set again.

Table EINT-1 Allocation of External Interrupt Request Levels

An NMI is detected always at the falling edge (except in the stop state). In the stop state, it is detected at the low level.


ELVR Address:000042 H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 00000000


ELVR Address:000043 H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000

LBx LAx Operation

0 0 Request on the low level

0 1 Request on the high level

1 0 Request at the rising edge

1 1 Request at the falling edge


223

6.2.5 Descriptions of operation(1) External interrupt operation

When a request corresponding to the request level set in the ELVR is input to a relevant pin after the ELVR and ENIR are set, this module generates an interrupt request signal to the interrupt controller. The interrupt controller identifies the priorities of simultaneously generated interrupts. If the interrupt request from this module has the highest priority, the requested interrupt is generated.

Figure EINT-2 Operation of External Interrupt

(2) Recovering from the standby stateTo use an external interrupt for recovering from the standby state in the clock stop mode, the input request level is "H" level regardless of the setting of the external interrupt request level setting register (ELVR).

(3) External interrupt procedureWhen setting the registers in the external interrupt unit, follow the procedure below:

1. Disable the corresponding bit in the enable interrupt request register (ENIR).2. Set the corresponding pair of bits in the external level register (ELVR).3. Clear the corresponding bit in the external interrupt request register (EIRR).4. Enable the corresponding bit in the ENIR.

(For the settings in steps 3 and 4, it is possible to write at the same time with 16-bit data.)

Before setting registers in this module for an external interrupt request output, be sure to disable the corresponding bit in the enable interrupt request register (ENIR). Also, before enabling the bit in the ENIR, be sure to clear the corresponding bit in the external interrupt request register (EIRR). This is to prevent an inadvertent interrupt source from being generated during register setting or in the interrupt enabled state.

Precaution: All of the external interrupt channels can be used to recover from the standby state. Before entering the standby state, be sure to disable the channels not to be used.

ELVR

EIRR

ENIR

ICR y y

ICR x x

IL

ILM

Interrupt

source

External interruptResource

requestInterrupt controller CPU

CMP CMP


224

(4) External interrupt request level

1) When the request detection level is edge request, the pulse width should be at least three machine cycles (peripheral clock machine cycles) to detect the edge.

2) When the request detection level is set to "H" or "L" level, an external request input to the interrupt controller remains active even if it is canceled later because the interrupt controller contains the interrupt source hold circuit.To cancel a request to the interrupt controller, the external interrupt request register (EIRR) must be cleared.

Interrupt source held until cleared

Figure EINT-3 Clearance of the Source Hold Circuit at Level Setting

Figure EINT-4 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled

(5) NMI1) Nonmaskable interrupts (NMIs) have the highest priority among user interrupts and cannot be masked.

As an exception, if NMI is started without setting ILM, NMI source is detected but CPU does not accept NMI request. In this case, NMI source is held until ILM is set to the level where NMI can be accepted. After a reset, set ILM to a value of 16 or higher and use NMI.The internal souce flag of NMI cannot be accessed from CPU. So, NMIX pin after the reset should hold “H” level .

2) An NMI is accepted at the following timings:- Normal state: Falling edge- Stop state: "L" level

3) An NMI can be used to release the device from the stop state. If an "L"-level signal is input in the stop state, the device is released from the stop state and enters the oscillation stabilization wait state.The NMI request detection circuit has an NMI flag that is set by an NMI request and cleared either upon receipt of the NMI itself or at a reset. This bit cannot be read or written.

Figure EINT-5 NMI Request Detection Circuit

Interrupt input Level detection Interrupt source F/F (Source hold circuit)

Enable gate Interruptcontroller

Interrupt inputH level

Interrupt request tointerrupt controller

Deactivated by clearance of interrupt source F/F

Q SX

R

Falling edge

detectionNMIXI

STOP

NMI request

(NMI flag)

clear (RST,interrupt acknowledge)

(Stop state canceled)

0

1 φ


225

6.3 REALOS-related Hardware REALOS-related hardware is used by the real-time OS. It cannot be used by user programs when REALOS is used.

6.4 Delayed Interrupt Module

6.4.1 OverviewThe delayed interrupt module generates a task switching interrupt.

This module enables software to issue or cancel an interrupt request to the CPU.

6.4.2 Register list

6.4.3 Block diagram

6.4.4 Register descriptionDICR (Delayed Interrupt Control Register)

This register controls a delayed interrupt.

[Bit 0] DLYI

This bit controls the generation and clearance of the relevant interrupt source.

bit 7 6 5 4 3 2 1 0

Address:00000044 H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DLYI DICR

[R/W]

bit 7 6 5 4 3 2 1 0

⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DLYI -------0 (Initial value)

[R/W]

DLYI Description

0 Clear delayed interrupt source or indicate no request (Initial value)

1 Generate delayed interrupt source

R-bus

Interrupt requestDLYI


226

6.4.5 Descriptions of operationThe delayed interrupt module generates a task switching interrupt. This module enables software to issue or cancel an interrupt request to the CPU.

(1) Interrupt number

A delayed interrupt is assigned to the interrupt source of the highest interrupt number.

The FR70 family core macro assigns interrupt number 63 (3FH) to the delayed interrupt.

(2) DLYI bit in the DICR

Writing "1" to this bit generates a delayed interrupt source. Writing "0" to the bit clears the delayed interrupt source.

The DLYI bit has the same effect as the interrupt source flag for a general interrupt. Clear this bit and switch the task in the interrupt routine.


227

6.5 Bit Search Module

6.5.1 OverviewThe bit search module searches data written to an input register for 0, 1, or a change point and returns the detected bit position.

6.5.2 Register list

6.5.3 Block diagram

Figure BSM-3 Block diagram

31 0

Address:000003F0 H BSD0 Data register for 0-detection

Address:000003F4 H BSD1 Data register for 1-detection

Address:000003F8 H BSDC Data register for change point detection

Address:000003FC H BSRR Detection result register

Input latch

1-detected data processing

Bit search circuit

D-BUS

Address decoder Detection mode

Search result


228

6.5.4 Register description6.5.4.1 Data register for 0-detection (BSD0)

Read/write → WInitial value → Undefined

This register checks written data for "0".The initial value after a reset is undefined. The read value is also undefined.For data transfer, use a 32-bit data transfer instruction. (Do not use an 8-bit or 16-bit data transfer instruction.)

6.5.4.2 1 Data register for 1-detection (BSD1)

Read/write → R/WInitial value → UndefinedFor data transfer, use a 32-bit data transfer instruction. (Do not use an 8-bit or 16-bit data transfer instruction.)1) At write

This register checks written data for "1"2) At read

The internal status save data for the bit search module is read from this register. The register is used to save and restore the original status when the interrupt handler uses the bit search module. Even when data has been written to the data register for 0-detection or change point detection, the original status can be saved and restored by using only this register.The initial value after a reset is undefined.

6.5.4.3 Data register for change point detection (BSDC)

Read/write →WInitial value →UndefinedThis register checks written data for any change point.The initial value after a reset is undefined. The read value is also undefined.For data transfer, use a 32-bit data transfer instruction. (Do not use an 8-bit or 16-bit data transfer instruction.)

6.5.4.4 Detection result register (BSRR)The 0, 1, or change point detection data is read from this register.The data type is determined by the data register written to last.

Read/write →RInitial value →Undefined

31 0

000003F0 H

31 0

000003F4 H

31 0

000003F8 H

31 0

000003FC H


229

6.5.5 Operation

1) 0-detection

The bit search module scans data written to the data register for 0-detection from MSB to LSB and returns the bit position at which "0" is detected first.

The detection result is obtained by reading the detection result register.

Table BSM-5 shows the relationship between detected positions and return values.

If "0" does not exist (i.e, when the register contains FFFFFFFFH), the module returns a value of 32 as the search result.

[Example of execution]

Written data Read value (decimal) 11111111111111111111000000000000 B (FFFFF000 H) → 20

11111000010010011110000010101010 B (F849E0AA H) → 510000000000000101010101010101010 B (8002AAAA H) → 111111111111111111111111111111111 B (FFFFFFFF H) → 32

2) 1-detection

The bit search module scans data written to the data register for 1-detection from MSB to LSB and returns the bit position at which "1" is detected first.



If "1" does not exist (i.e, when the register contains 00000000H), the module returns a value of 32 as the search result.


Written data Read value (decimal)00100000000000000000000000000000 B (20000000 H) → 200000001001000110100010101100111 B (01234567 H) → 700000000000000111111111111111111 B (0003FFFF H) → 14

00000000000000000000000000000001 B (00000001 H) → 3100000000000000000000000000000000 B (00000000 H) → 32


230

3) Change point detection

The bit search module scans data written to the data register for change point detection from bit 30 to LSB. The module then compares that range of data to the MSB value to return the bit position at which a value different from the MSB value is detected first.



If no change point exists, the module returns a value of 32 as the search result.

The module never returns 0 as the result of change point detection.


Written data Read value (decimal)00100000000000000000000000000000 B (20000000 H) → 200000001001000110100010101100111 B (01234567 H) → 700000000000000111111111111111111 B (0003FFFF H) → 14

00000000000000000000000000000001 B (00000001 H) → 3100000000000000000000000000000000 B (00000000 H) → 3211111111111111111111000000000000 B (FFFFF000 H) → 2011111000010010011110000010101010 B (F849E0AA H) → 510000000000000101010101010101010 B (8002AAAA H) → 111111111111111111111111111111111 B (FFFFFFFF H) → 32

Table BSM-5 Detected Bit Positions and Return Values (Decimal)

6.5.6 Save/Restore ProcessingWhen it is necessary to save and restore the internal status of the bit search module, for example, when the bit search module is used in the interrupt handler, follow the procedure below:

1) Read data from the data register for 1-detection and save it. (Save)

2) Use the bit search module.

3) Write the data saved in step 1) to the data register for 1-detection. (Restore)

With the above value procedures, the value obtained when you read the detection result register next time is corresponding to the value written to bit search module before taking procedure 1). Even when the data register written to last is the one for 0-detection or change point detection, the above procedure restores the original status of the bit search module correctly.

Detected bit position

Return value


Return value


Return value


Return value

31 0 23 8 15 16 7 24

30 1 22 9 14 17 6 25

29 2 21 10 13 18 5 26

28 3 20 11 12 19 4 27

27 4 19 12 11 20 3 28

26 5 18 13 10 21 2 29

25 6 17 14 9 22 1 30

24 7 16 15 8 23 0 31

None 32


231

6.6 16-bit Reload Timer

6.6.1 OverviewThe 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for internal count clock generation, and a control register.

The input clock signal can be selected from among three internal clock signals (1/2, 1/8, and 1/32 of the machine clock frequency) and an external clock.

The output pins (TOUT[3:0]) output a toggle output waveform at each underflow in reload mode but a square waveform indicating counting in one-shot mode.

The input pins (TTG[3:0]) can serve as event input in external event count mode and for trigger input or gate input in internal clock mode.

Using the external event count function in reload mode, this module can be used as a frequency divider for the external clock.

The FR70 family core macro contains three channels (0 to 2) of the 16-bit reload timer.

Channels 0 and 1 of the reload timer can activate DMA transfer using its interrupt request signals.

6.6.2 Register list15 14 13 12 11 10 9 8 (TMCSR )

⎯ ⎯ ⎯ ⎯ CSL1 CSL0 MOD2 MOD1 Control status register

7 6 5 4 3 2 1 0

MOD0 ⎯ OUTL RELD INTE UF CNTE TRG

15 0 16-bit timer register

(TMR)

15 0 16-bit reload register

(TMRLR)


232

6.6.3 Block diagram

Figure RTIM-1 Block diagram

Internal clock

Prescaler clear

Clock selector

16bit down counter UF

16 bit reload register

IN CTL .

Retrigger

GATEIRQ

EXCK

CSL0

MOD0

MOD1

TRG

CNTE

UF

INTE

OUTL

OUTE

OUT

CTL.

RELD

3

3

22

2

16

8

16

MOD2

CSL1

Reload

21

23

25

R-B

US

TTG[2:0]

TOUT[2:0]

φ φφ


233


1) Control status register (TMCSR)

The control status register (TMCSR) controls the 16-bit timer operation modes and interrupts.

Rewrite a bit other than UF, CNTE, and TRG when the CNTE bit is set to "0".

Two or more bits can be written at the same time.

[Bits 11, 10] CSL1, CSL0 (Count clock SeLect)

These bits are used to select a count clock signal.

Table RTIM-1 lists the available clock sources. The valid count edge for external event count mode is set by the MOD1 and MOD0 bits.

Table RTIM-1 CSL Bit Settings and Clock Sources

The minimum pulse width required for the external clock is 2-T (T: peripheral clock machine cycle).

TMCSR bit

Address 11 10 9 8 7 6 5 4 3 2 1 0Initial value

0000004E H00000056 H0000005E H

CSL1 CSL0 MOD2 MOD1 MOD0 ‘0’ RELD INTE UF CNTE TRG000000000000 b

R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W

CSL1 CSL0 Clock source (φ : machine clock)

0 0 φ /21

0 1 φ /23

1 0 φ /25

1 1 External clock (event)


234

[Bits 9-7] MOD2-MOD0 (MODe)

These bits are used to set the operation mode and the input pin function.

The MOD2 bit is used to select the input pin function. Setting the MOD2 bit to "0" causes the input pin to serve as a trigger input pin. When an effective edge is input, the contents of the reload register are loaded to the counter to continue counting. Setting the bit to "1" activates the gate count mode and causes the input pin to serve as a gate input pin. In the gate count mode, counting is performed only when the effective level signal is input.

The MOD1 and MOD0 bits are used to set the pin function in each mode. Tables RTIM-2 and RTIM-3 list the settings of the MOD2 to MOD0 bits.

Table RTIM-2 Settings of the MOD2 to MOD0 Bits (1) Internal clock mode

(CSL0 and CSL1 = 00, 01, or 10)

Table RTIM-3 Settings of the MOD2 to MOD0 Bits (2) Event count mode (CSL0 and CSL1 = 11)

Note: X in the table indicates an arbitrary value.

[Bit 6] (Reserved)

This bit is not used.

"0" is always read when reading.

[Bit 4] RELD

This bit enables reloading. The reload mode is established when this bit is set to "1", where a counter underflow from 0000H to FFFFH causes the reload register contents to be loaded to the counter to continue counting.

When this bit is set to "0", where a counter overflow from 0000H to FFFFH causes counting to stop.

[Bit 3] INTE

This bit enables an interrupt request. When this bit is "1", an interrupt request is generated as soon as the UF bit becomes "1". When this bit is "0", no interrupt request is generated.

MOD2 MOD1 MOD0 Input pin function Effective edge/level

0 0 0 Trigger inhibited ⎯⎯

0 0 1

Trigger input

Rising edge

0 1 0 Falling edge

0 1 1 Both edges

1 X 0 "L" level

1 X 1 "H" level

MOD2 MOD1 MOD0 Input pin function Effective edge/level

X

0 0 ⎯⎯ ⎯⎯

0 1

Trigger input

Rising edge

1 0 Falling edge

1 1 Both edges


235

[Bit 2] UF

This bit is a timer interrupt request flag. A counter underflow from 0000H to FFFFH sets this bit to "1". Writing 0 to the bit clears it.

Writing "1" to this bit has no effect.

"1" is read out when reading with read-modify write instructions.


236

[Bit 1] CNTE

This bit enables timer counting. Writing "1" to this bit places the timer in the trigger wait status. Writing "0" to the bit causes the timer to stop counting.

[Bit 0] TRG

This bit is a software trigger bit. Writing "1" to this bit generates a software trigger that causes the reload register contents to be loaded to the counter to start counting.

Writing "0" to the bit has no effect. Read value is always "0".

Trigger input by this register is valid only when the CNTE bit is "1"; nothing happens when the CNTE bit is "0".

2) 16-bit timer register (TMR)

The 16-bit timer register (TMR) can read the count value of the 16-bit timer. The initial value is undefined. To read this register, be sure to use a 16-bit data transfer instruction.

3) 16-bit timer register (TMRLR)

The 16-bit reload register (TMRLR) can hold the initial count value.

The initial value is undefined. To read this register, be sure to use a 16-bit data transfer instruction.

15 0

Address: 00004A H000052 H00005A H

R R R R --- R R R R R

Initial value X X X X --- X X X X X

15 0

Address: 000048 H000050 H000058 H

W W W W --- W W W W W

Initial value X X X X --- X X X X X


237

6.6.5 Descriptions of operation

1) Internal clock operation

When operating the timer on a frequency-divided internal clock, the clock source can be selected from among 1/2, 1/8, and 1/32 of the machine clock.

The external input pin can be used for trigger input or gate input depending on the register setting.

To enable and start counting simultaneously, write "1" to both of the CNTE and TRG bits in the control status register. Trigger input by the TRG bit is always effective in any operation mode when the timer is active (CNTE="1").

Figure RTIM-2 shows the counter activation and operation timings.

It takes time T (peripheral clock machine cycle) from when a counter start trigger signal is input until data is loaded from the reload register to the counter.

Figure RTIM-2 Counter Activation and Operations

2) Underflow operation

An underflow means a change of the counter value from 0000H to FFFFH. Therefore, an underflow occurs at the count of "reload register set value + 1."

When an underflow occurs with "1" held in the RELD bit in the control register, the values of the reload register are loaded to the counter to keep counting. When an underflow occurs with "0" in the RELD bit, the counter stops counting at FFFFH.

An underflow sets the UF bit in the control register and, when the INTE bit is "1", generates an interrupt request.

Figure RTIM-3 shows the underflow operation.

-1 -1 -1

T

Counterclock

Counter ReloadData

Data load

CNTE (Register)

TRG (Register)


238

Figure RTIM-3 Underflow Operating Timings

3) Counter operation status

The counter status is determined by the CNTE bit in the control register and the internal signal WAIT. The counter can be set to: the STOP status with CNTE=0 and WAIT=1, the WAIT status with CNTE=1 and WAIT=1, or the RUN status with CNTE=1 and WAIT=0. Figure RTIM-8 shows the state transition.

Figure RTIM-4 Counter State Transition

0000 H

0000 H

-1 -1 -1

FFFF H

Counter clock

Counter

Dataload

Underflow set

Count Clock

Counter

Underflow set

Reload data

[RELD=1]

[RELD=0]

Reset

Counter: Holds the value at a stop

(Undefined immediately after reset)

T0: General-purpose

T1: Input prohibitedState transition by register access

State transition by hardware

CNTE="0", WAIT="1"STOP

Counter: Holds the value at a stop

(Undefined immediately after

reset until loading)

T0: Initial value output

T1: Only trigger input valid

End of loadinTrigger from TIN

RELD UF

RELD UF

CNTE="0"CNTE="0"

TRG="1" TRG="1 "

TRG="1"

CNTE= "1"

TRG=’ 0’

CNTE="1"

CNTE="1", WAIT="1"WAIT

Counter: Operating

T0: Serves as T0

CNTE="1", WAIT="0"RUN

Load reload register contents to

counter

CNTE="1", WAIT="0"LOAD

T1: Serves as T1

.

.


239

Others

Channels 0 and 1 of the reload timer can activate DMA transfer using its interrupt request signals.

Upon receipt of a transfer request, the DMA controller clears the reload timer interrupt flag.

6.6.6 Notes(1) The internal prescaler becomes ready for operation by being triggered (software trigger or external

trigger) when bit 1 (CNTE timer enable bit) in the control status register is set to "1".

Even when the timer is used only in gate count mode, be sure to trigger the prescaler once before the valid gate level signal is input. (It is recommended that "1" should be written to bit 0 (TRG) in the same register when setting the CNTE bit.)

(2) If attempts to set and clear the interrupt request flag are made at the same timing, the flag set request takes precedence and the clear request becomes invalid.

(3) If attempts to write to and reload from the 16-bit timer reload register are made at the same timing, old data is loaded to the counter and then new data is loaded to the counter at the next reload timing.

(4) When the load and count operations of the 16-bit timer register are attempted at the same timing, the load (reload) operation takes priority over the count operation.


240

6.7 U-Timer (16-bit Timer for UART Baud Rate Generation)

6.7.1 OverviewThe U-timer is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set by the combination of the chip operating frequency and U-timer reload value.

The U-timer can be used as an interval timer as it generates an interrupt at a counter underflow.

The FR70 family core macro contains two channels of the U-timer. When used as the interval timer, two pairs of U-timers can be cascaded so that it can count for an interval of up to " 2 32 x φ "

6.7.2 Register list

6.7.3 Block diagram

15 8 7 0

UTIM (R)

UTIMR (W)

UTIMC (R/W)

underflow

load

15

15 0

0

to UART

clock

(Peripheral clock)

UTIMR reload register

UTIM timer

MUXChannel 0

only

under flow U-TIMER 1

f. f.

controlφ


241


(1) UTIM (U-TIMmer)

The UTIM register holds the timer value. Use a 16-bit transfer instruction to access this register.

(2) UTIMR (reload register)

The UTIMR register stores the value to be reloaded to the UTIM register when the UTIM register causes an underflow. Use a 16-bit transfer instruction to access this register.

(3) UTIMC (U-Timer control register)

The UTIMC register controls the operation of the U-timer.

[Bit 7] UCC1 (U-timer Count Control 1)

The UCC1 bit controls the U-timer count mode.

n: UTIMR set value

α: Frequency of output clock signal to UART

The U-timer can set the output clock signal of the normal 2(n+1) frequency to the UART and a frequency divided by an odd number as well.

UTIM 15 14 − − − − − 2 1 0

ch0 Address:

ch1 Address:

0000 0064 H0000 006C H

b15 b14 b2 b1 b0

←⎯− − − − − − ⎯⎯ R Access

←⎯− − − − − − ⎯⎯ 0 Initial value

UTIMR 15 14 − − − − − 2 1 0

ch0 Address:

ch1 Address:

0000 0064 H 0000 006C H

b15 b14 b2 b1 b0

←⎯− − − − − − ⎯⎯ W Access

←⎯− − − − − − ⎯⎯ 0 Initial value

UTIMC 7 6 5 4 3 2 1 0

ch0 Address:ch1 Address:

0000 0067 H0000 006F H

UCC1 ⎯ ⎯ UTIE UNDR CLKS UTST UTCR

R/W ⎯ ⎯ R/W R/W R/W R/W R/W Access

0 ⎯ ⎯ 0 0 0 0 1 Initial Value

UCC1 Count mode

0 Normal mode, α = 2n + 2 (Initial value)

1 +1 mode, α = 2n + 3


242

Setting the UCC1 bit to "1" generates the "2n+3" frequency.

Example settings:

1. UTIMR = 5, UCC1 = 0: Generated frequency = 2n + 2 = 12 cycles



To use the U-timer as the interval timer, set the UCC1 bit to "0".

[Bits 6, 5] (Reserved)

[Bit 4] UTIE (U-Timer Interrupt Enable)

The UTIE bit enables an interrupt at a U-timer underflow.

0: Disable interrupts. (Initial value)

1: Enable interrupts.

[Bit 3] UNDR (UNDeR flow flag)

The UNDR bit is the flag to indicate the occurrence of an underflow. When the UNDR bit is set with the UTIE bit being "1", an underflow interrupt occurs. The UNDR bit is cleared either at a reset or writing "0" to it.

Reading this bit using a read modify write instruction always reads out "1".

Writing "1" to the UNDR bit has no effect.

[Bit 2] CLKS (clock select)

The CLKS bit specifies the cascade connection of channels 0 and 1 of the U-timer.

0: Use the peripheral clock ([φ]) as the clock source. (Initial value)

1: Use the channel-1 underflow signal (f.f in the block diagram) as the source clock timing for channel 0 of the U-timer.

The CLKS bit is valid only to channel 1. For channel 1, set it always to "0".

*: The frequency of [φ] (peripheral clock) varies according to the gear setting.

[Bit 1] UTST (U-Timer STart)

This bit enables the U-timer for operation.

0: Disable the U-timer. Writing "0" to the bit stops the U-timer even during operation. (Initial value)

1: Enable the U-timer. Writing "1" to the bit during operation lets the U-timer operate continuously.

[Bit 0] UTCR (U-Timer CleaR)

Writing "0" to the UTCR bit clears the U-timer to 0000H (and the f.f. to "0" as well).

Reading this bit always returns "1".


243

Precautions:

1) Asserting the start bit UTST (to start the U-timer) in the stop state causes automatic reloading.

2) If the clear bit UTCR and start bit UTST are asserted at the same time in the timer stop state, the counter is cleared to "0" and generates an underflow at the subsequent countdown.

3) When the clear bit UTCR is asserted during operation, the counter is cleared to "0". At this time, the output waveform may include a whisker-like short pulse which can cause the UART or the upper- channel U-timer in cascade mode to malfunction. When the output is used, do not use the clear bit to clear the counter during operation.

4) Counting is not performed correctly if "0" or "1" is set to the upper-channel UTIMR (reload register) in cascade mode.

5) If bit 1 (U-timer start bit UTST) and bit 0 (U-timer clear bit UTCR) in the U-timer control register are asserted at the same time in the timer stop state, bit 3 (underflow flag UNDR) in the same register is set at the same timing as the load to the cleared counter. Also, the internal baud rate clock goes high at the same timing.

6) If attempts to set and clear the interrupt request flag are made at the same timing, the flag set request takes precedence and the clear request becomes invalid.

7) When channel 0 is not used in cascade mode or this module is used as a simple timer, always write "0" to bit 2 (reference clock select bit CLKS) in the U-timer control register. If you change the CLKS setting, stop the U-timer in advance.

8) If attempts to write to and reload from the U-timer reload register are made at the same timing, old data is loaded to the counter and then new data is loaded to the counter at the next reload timing.

9) When the timer clear, count, and reload operations are attempted at the same timing, the time clear operation takes the highest priority.


244

6.7.5 Explanation of operation

1) Baud rate calculation

The UART (UART0/UART1) uses the underflow flip-flop (f.f in the block diagram) of the corresponding U-timer (U-timer 0→UART0, U-timer 1→UART1) as the clock source for the baud rate.

(1) Asynchronous (start-stop) mode

The UART uses the U-timer output frequency-divided by 16.

φ n: UTIMR (Reload value)bps = ⎯⎯⎯⎯⎯⎯⎯ ----- UCC1=0

(2n+2) x 16 φ: Peripheral machine clock frequency

φ (Variable with gear) bps = ⎯⎯⎯⎯⎯⎯⎯ ----- UCC1=1

(2n+3) x 16

Maximum bps: 257812.5 bps at 33 MHz

(2) CLK synchronous mode

φ n: UTIMR (Reload value)bps = ⎯⎯⎯⎯⎯⎯⎯ -----UCC1=0

(2n+2) φ: Peripheral machine clock frequency

φ (Variable with gear)bps = ⎯⎯⎯⎯⎯⎯⎯ -----UCC1=1

(2n+3)

Maximum bps: 4125000 bps at 33 MHz

2) Cascade mode

U-timer channels 0 and 1 can be used in cascade mode.

Example: Timings with UTIMR ch. 0 set to 0100 and UTIMR ch. 1 set to 0002

0000000000 0101010101 020202020200010200

0100000000010002

01

UTIM ch.0

f.f . ch.0

f.f . ch.1

UTIM ch.1

φ


245

6.8 UART

6.8.1 OverviewThe UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module has the features listed below. The FR70 family core macro contains two channels of UART.

• Full-duplex double buffer• Asynchronous (start-stop) or CLK synchronous communication• Multiprocessor mode supported• Fully programmable baud rate• Arbitrary baud rate set by built-in timer (See Section "U-timer".)• Free baud rate setting by external clock• Error detection function (parity, framing, and overrun)• NRZ-code transfer signal• MSB/LSB-first selectable• DMA transfer activation by interrupt• Clearing DMAC interrupt source by writing to DRCL register

6.8.2 Register list15 8 7 0

SCR SMR (R/W)

SSR SIDR(R) (R/W)

DRCL (W)

8-bit 8-bit

7 6 5 4 3 2 1 0 Serial input/output register (SIDR/SODR)D7 D6 D5 D4 D3 D2 D1 D0

7 6 5 4 3 2 1 0

PE ORE FRE RDRF TDRE MSBF RIE TIE Serial status register (SSR)

7 6 5 4 3 2 1 0

MD1 MD0 ⎯ ⎯ CS0 ⎯ SCKE ⎯ Serial mode register (SMR)

7 6 5 4 3 2 1 0

PEN P SBL CL A/D REC RXE TXE Serial control register (SCR)

7 6 5 4 3 2 1 0

⎯ -⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (DRCL)


246

6.8.3 Block diagram

R-BUS

Control signal

Transmission

interrupt (to CPU)

Reception

interrupt (to CPU)

SCKOUT

SIN (Reception data)

External clock

From U-timer

SMR register

DMA reception error

generation signal (To

DMAC)

SIDR

End of

reception

Start of

transmission

PE

ORE

FRE

RDRF

TDRE

RIE

TIE

PEN

P

SBL

CL

A/D

REC

RXE

TXE

MD1

MD0

CS0

SOE

Control signal

Reception shifter

counter

Reception bit

counter

Transmission clock

Reception clock

Reception status check

circuit

Reception control

circuit

circuit

Clock selector

counter

Transmission

counter

Transmission control

circuit

Transmission start

circuit

SODR

SOUT

Transmission shifter

SCR register SSR register

SCKIN

Start bit detection

Reception parity Transmission parity

(Transmission

data)


247

6.8.4 Register description1) SMR (Serial mode register)

The serial mode register (SMR) specifies the operation mode of the UART. Set the operation mode when the UART is stopped. Do not write to this register when the UART is in operation.

[Bits 7, 6] MD1, MD0 (MoDe select)

These bits are used to select a UART operation mode.

Table UART-1 Selection of UART Operation Mode

Precautions:

In CLK asynchronous, (multiprocessor) mode, several slave CPUs are connected to a single host CPU. This resource cannot identify the format of received data and thus supports only the master in multiprocessor mode.

Since the parity check function is not available, set the PEN flag in the SCR register to "0".

[Bits 5, 4] (Reserved)

Always write "1" to these bits.

[Bit 3] CS0 (Clock Select)

This bit is used to select the operation clock for the UART.

0: Internal timer (U-timer) (Initial value)

1: External clock

[Bit 2] (Reserved)

Always write "0" to this bit.

[Bit 1] SCKE(Serial Clock Enable)

The value of this bit is input to SCKE[1], SCKE[0] and used to control direction of SCKOUT[1:0] and SCLOM[1:0].

[Bit 0] (Reserved)

This bit is not used.

SMR 7 6 5 4 3 2 1 0 Initial value

Addressch0ch1

000063 H00006B H

MD1 MD0 ⎯− ⎯− CS0 ⎯− SCKE ⎯− 00—0-0- B

R/W R/W W R/W

Mode MD1 MD0 Operation mode

0 0 0 Asynchronous (start-stop), normal mode (Initial value)

1 0 1 Asynchronous (start-stop), multiprocessor mode

2 1 0 CLK synchronous mode

- 1 1 Setting prohibited


248

2) SCR (Serial control register)

The serial control register (SCR) controls the transfer protocol for serial communication.

[Bit 7] PEN (Parity Enable)

This bit selects whether to add parity to serial data communication.

0: No parity (Initial value)

1: Parity

Precaution:

Parity can be added only in normal asynchronous (start-stop) communication mode (mode 0). No parity can be added in multiprocessor asynchronous communication mode (mode 1) or CLK synchronous communication mode (mode 2).

[Bit 6] P (Parity)

This bit selects even or odd parity to be added to data communication.

0: Even parity (Initial value)

1: Odd parity

[Bit 5] SBL (Stop Bit Length)

This bit specifies the length of stop bits that serve as a frame end mark for asynchronous (start-stop) communication.

0: One stop bit (Initial value)

1: Two stop bits

[Bit 4] CL (Character Length)

This bit specifies the data length of each frame to be transmitted and received.

0: 7 bits (Initial value)

1: 8 bits

Precaution:

Seven-bit data can be handled only in normal asynchronous (start-stop) communication mode (mode 0). Set the data length to 8 bits for communication in asynchronous multiprocessor mode (mode 1) or CLK synchronous communication mode (mode 2).

[Bit 3] A/D (Address/Data)

This bit specifies the data format of frames to be transmitted and received in multiprocessor asynchronous communication mode (mode 1).

0: Data frame (Initial value)

1: Address frame

[Bit 2] REC (Receive Error Clear)

Writing "0" to this bit clears the error flags (PE, ORE, and FRE) in the SSR register.

Writing "1" has no effect. Reading the bit always returns "1".

SCR 7 6 5 4 3 2 1 0 Initial value

Addressch0ch1

000062 H00006A H

PEN P SBL CL A/D REC RXE TXE 00000100 B

R/W R/W R/W R/W R/W W R/W R/W


249

[Bit 1] RXE (Receive Enable)

This bit controls UART reception.

0: Disable reception (Initial value)

1: Enable reception

Precaution:

If reception in process is disabled (with data being input to the reception shift register), the UART stops reception after finishing receiving the current frame and storing the received data to the receive data buffer (SIDR).

[Bit 0] TXE (Transmitter Enable)

This bit controls UART transmission.

0: Disable transmission. (Initial value)

1: Enable transmission.

Precaution:

If transmission in process is disabled (with data being output from the transmission register), the UART stops transmission after the SODR register in the transmit data buffer becomes empty.

3) SIDR (Serial input data register)/SODR (Serial output data register)

These registers are data buffer registers for reception and transmission.

When the data length is 7 bits, the D7 (bit 7) is invalid. Write to the SODR register only when the TDRE bit in the SSR register is "1".

Precaution:

Write access to this address means a data written to the SODR register; read access means a data read from the SIDR register.

4) SSR (Serial status register)

The serial status register (SSR) consists of flags indicating UART operation states.

SIDR 7 6 5 4 3 2 1 0 Initial value

Addressch0ch1

000061 H000069 H

D7 D6 D5 D4 D3 D2 D1 D0 Undefined

R R R R R R R R

SODR 7 6 5 4 3 2 1 0 Initial value

Addressch0ch1

000061 H000069 H

D7 D6 D5 D4 D3 D2 D1 D0 Undefined

W W W W W W W W

SSR 7 6 5 4 3 2 1 0 Initial value

Addressch0ch1

000060 H000068 H

PE ORE FRE RDRF TDRE MSBF RIE TIE 00001000 B

R R R R R R/W R/W R/W


250

[Bit 7] PE (Parity Error)

This bit is the interrupt request flag that is set when a parity error occurs during reception.

To clear the flag once set, write "0" to the REC bit (bit 10) in the SCR register.

Setting this bit makes the SIDR data invalid.

0: No parity error (Initial value)

1: Parity error occurred

[Bit 6] ORE (Overrun Error)

This bit is the interrupt request flag that is set when an overrun error occurs during reception.



0: No overrun error (Initial value)

1: Overrun error occurred

[Bit 5] FRE (FRaming Error)

This bit is the interrupt request flag that is set when a framing error occurs during reception.



0: No framing error (Initial value)

1: Framing error occurred

Precautions:

Switching the internal/external baud rate clock by the CS0 bit (bit 3) in the serial mode register is reflected immediately after the new value is written to the bit. This should therefore be performed when the UART is inactive.

*: Bit 3 in the serial mode register is write only.

[Bit 4] RDRF (Receiver Data Register Full)

This bit is the interrupt request flag indicating that the SIDR register currently contains receive data.

This flag is set when receive data is loaded to the SIDR register and automatically cleared when the data is read from the SIDR register.

0: No receive data (Initial value)

1: Receive data present

[Bit 3] TDRE (Transmitter Data Register Empty)

This bit is the interrupt request flag indicating that transmit data can be written to the SODR register.

This flag is cleared when transmit data is written to the SODR register. When the written data is loaded to the transmission shifter and data transfer starts, this flag is set again to indicate that next transmit data can be written.

0: Disable transmit data write

1: Enable transmit data write (Initial value)

[Bit 2] MSBF (MSB First)

This bit controls selecting the data transfer direction.

0: Transfer the serial data from the lowest bit. (LSB First) (Initial value)

1: Transfer the serial data from the upper most bit. (MSB First)


251

Note:

When reading and writing to the serial data register, this bit inverts the upper and lower side of the data. Therefore, if this bit is rewritten after writing the data to SODR, the data becomes invalid.

[Bit 1] RIE (Receiver Interrupt Enable)

This bit controls a reception interrupt.

0: Disable interrupts (Initial value)

1: Enable interrupts

Note:

A reception interrupt can occur either when an error indicated by the PE, ORE, and FRE bit occurs or upon normal reception indicated by the RDRF bit.

[Bit 0] TIE (Transmitter Interrupt Enable)

This bit controls a transmission interrupt.

0: Disable interrupts (Initial value)

1: Enable interrupt

Note:

A transmission interrupt can occur at a transmit request of the TDRE bit.

5) DRCL

The DRCL register is used to clear a DMAC interrupt source. Writing an arbitrary value to this register clears the source of an interrupt to the DMAC. When activating the DMAC for the first time or after having used the UART, use this register to clear the DMAC interrupt request.

(This register is write only.)

DRCL 7 6 5 4 3 2 1 0 Initial value

Addressch0ch1

000066 H00006E H

⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ -------- B

W W W W W W W W


252

6.8.5 Explanation of operation1) Operation modes

The UART has the operation modes listed in Table UART-2 below. Each of the modes can be selected by writing the corresponding values to the SMR and SCR registers.

Table UART-2 UART Operation Modes

Note that the stop bit length in asynchronous (start-stop) mode can be specified for transmission only. The length is fixed at one bit for reception. Do not set the stop bit length in other modes because the set-ting becomes invalid.

2) UART clock selection

a) Internal timer

If CS0 is set to "0" to select the U-timer, the UART baud rate is determined by the reload value set for the U-timer. The baud rate is calculated as follows:

Asynchronous (start-stop) mode: φ / (16 x β)

CLK synchronous mode: φ / βφ: Peripheral machine clock frequency

β: Frequency set by the U-timer (2n+2 or 2n+3, where "n" is a reload value.)

Baud rate in asynchronous (start-stop) mode is transferable between the range of -1% and +1% of the set baud rate.

b) External clock

If CS0 is set to "1" to select an external clock, the baud rate can be calculated from the external clock frequency (f) as follows:

Asynchronous (start-stop) mode: f/16

CLK synchronous mode: f

The maximum value of f is the peripheral clock frequency divided by 8. When the peripheral clock frequency is 33 MHz, the maximum external clock frequency is 4.125 MHz.

Mode Parity Data length Operation mode Stop bit length

0Yes/No 7

Asynchronous (start-stop), normal mode1 or 2 bitsYes/No 8

1 No 8+1 Asynchronous (start-stop), multiprocessor mode

2 No 8 CLK synchronous mode None


253

3) Asynchronous (start-stop) modes

a) Transfer data format

The UART handles data in the Non Return to Zero (NRZ) format only. Figure UART-2 shows the transfer data format in asynchronous (start-stop) modes.

Figure UART-2 Transfer Data Format (in Mode 0/1)

As shown in Figure UART-2, data transfer always starts from the start bit ("L"-level data). After the speci-fied number of bits are transferred starting from the LSB, the data transfer ends at the stop bit ("H"-level data). If an external clock is selected, always enter clock pulses. The data length can be set to 7 or 8 bits in normal mode (mode 0) but must always be 8 bits in multiprocessor mode (mode 1). No parity can be added in multiprocessor mode. Instead, the A/D bit is always added.

b) Reception

Reception is always in progress when the RXE bit (bit 1) in the SCR register is "1".

If a start bit appears in the reception line, a frame of data is received in the SCR-specified data format. Once a frame of data has been received and an error occurs, an error flag is set and the RDRF flag (bit 4 in the SSR register) is set. If the RIE bit (bit 1) in the same register is "1" at this time, a reception interrupt is issued to the CPU. Check each flag in the SSR register, then read the SIDR register if the reception status is normal or execute necessary processing if abnormal.

The RDRF flag is cleared when the SIDR register is read.

c) Transmission

When the TDRE flag (bit 3) in the SSR register is "1", transmit data is written to the SODR register. When the TXE bit (bit 0) in the SCR register is "1", the data is transmitted.

Data set in the SODR register is loaded to the transmission shift register and transmission starts. Then the TDRE flag is set again to allow the next transmit data to be set. If the TIE bit (bit 0) in the SSR register is "1", however, a transmission interrupt request is issued to the CPU to set transmit data in the SODR register. The TDRE flag is cleared once when data is set in the SODR register.

SIN, SOUT

0 1 0 1 1 0 0 1 0 1 1

Start LSB MSB STOPA/ D STOP

(Mode 0)(Mode 1)

Transferred data is 01001101 B


254

4) CLK synchronous mode

a) Transfer data format

The UART handles data in the NRZ (Non Return to Zero) format only. Figure UART-3 shows the transfer data format in CLK synchronous mode.

Figure UART-3 Transfer Data Format (in Mode 2)

If the internal clock (U-timer) has been selected, data transmission automatically generates synchronous clock pulses for data reception.

If an external clock has been selected, check that there is data in the SODR register in the transmit data buffer of the transmission-side UART (TDRE flag value is "0"). Then, one byte of clock pulses should be supplied accurately. Also, be sure to set the mark level before the start of transmission and after the end of it.

Data must be 8 bits long with no parity. Since the start and stop bits are not supported, any error other than overrun errors cannot be detected.

b) Initialization

To use the CLK synchronous mode, set each control register to the following values:

(1) SMR register

MD1, MD0: 10

CS: Specify clock input.

SOE: 1 for transmission, 0 for reception

(2) SCR register

PEN: 0

P, SBL, A/D: These bits do not have any meaning.

CL: 1

REC: 0 (for initialization)

RXE, TXE: 1 (at least either one)

(3) SSR register

RIE: 1 for interrupts, 0 for no interrupt

TIE: 0

c) Start of communication

Communication starts when data is written to the SODR register. Even for reception only, temporary transmit data must be written to the SODR register.

SCLK

RXE , TXE

SIN, SOUT

1 0 1 1 0 0 1 0LSB MSB (Mode2)

Write to SODR

Mark

Transferred data is 01001101 B


255

d) End of communication

When communication ends in CLK synchronous mode, the RDRF flag in the SSR register changes to "1". Check the ORE flag in the SSR register to see if the communication has been completed normally.

5) UART interrupt generation and flag setting timingsThe UART has five flags and two interrupt sources.

The five flags are the PE, ORE, FRE, RDRF, and TDRE bits in the SSR register. PE stands for parity error, ORE for overrun error, and FRE for framing error. These flags are set when their respective errors occur during reception. They are cleared when "0" is written to the REC bit in the SCR register. The RDRF flag is set when receive data is loaded into the SIDR register and cleared when the SIDR register is read. Note that the parity detection function is not supported in mode 1 and the parity and framing error detection functions are not supported in mode 2. The TDRE flag is set when the SODR register becomes empty and ready for write and cleared when data is written to the SODR register.

The two interrupt resources are for reception and transmission. At reception, PE, ORE, FRE, or RDRF is used for an interrupt request. At transmission, TDRE is used for an interrupt request. These interrupt flags are set in each mode at the timings shown in the figures below.

a) Reception in mode 0When the last stop bit is detected at the end of transfer for reception, the PE, ORE, FRE, and RDRF flags are set to issue an interrupt request to the CPU. The SIDR data is invalid when the PE, ORE, and FRE flags are active.

Figure UART-4 PE, ORE, FRE, and RDRF Flag Setting Timings in Mode 0

b) Reception in mode 1When the last stop bit is detected at the end of transfer for reception, the ORE, FRE, and RDRF flags are set to issue an interrupt request to the CPU. Since the receivable data length is 8 bits, the last bit (bit 9) holding an address or data becomes invalid. The SIDR data is invalid when the ORE and FRE flags are active.

Figure UART-5 ORE, FRE, and RDRF Flag Setting Timings in Mode 1

D6 D7 STOP

PE, ORE, FRE

RDRF

Data

Reception interrupt

D7 STOP

PE, ORE, FRE

RDRF

Data

Reception interrupt

Address/data


256

c) Reception in mode 2

When the last data (D7) is detected at the end of transfer for reception, the ORE and RDRF flags are set to issue an interrupt request to the CPU. The SIDR data is invalid when the ORE flag is active.

Figure UART -6 ORE and RDRF Flag Setting Timings in Mode 2

d) Transmission in Modes 0, 1, and 2

The TDRE flag is cleared when transmit data is written to the SODR register and set when the SODR register value is transferred to the internal shift register because the SODR register becomes ready for writing next data. When this flag is set, an interrupt request is issued to the CPU. If "0" is written to the TXE bit in the SCR register (including RXE in mode 2) during transmission, the TDRE flag in the SSR register becomes "1". After the transmission shifter stops, the UART is disabled for transmission. During transmission, 0 is written to the TXE bit in the SCR register (including RXE in mode 2). Data written to the SODR register before the end of transmission is transmitted regardless.

Figure UART -7 TDRE Flag Setting Timings in Modes 0 and 1

D5 D7

PE, ORE, FRE

RDRF

D6Data

Reception interrupt

ST D0 D1 D2 D3 D4 D5 D6 D7 SPA/ D SP ST D0 D1

TDRE

SOUT[n] output

ST: Start bitSP Stop bit :

D0~ D7: Data bitA/D : Address/data multiplexer

Write to SODR

SO interrupt

Requests an interrupt to CPU


257

Figure UART-8 TDRE Flag Setting Timings in Mode 2

6.8.6 Notes on useSet the communication mode when the UART is not in operation. Data transmitted and received during mode setting cannot be guaranteed. Before starting DMA transfer using an interrupt for the first time, write any value to the DRCL register.

6.8.7 Example of UART applicationMode 1 is used when several slave CPUs are connected to a single host CPU (as shown in Figure UART-9). This resource supports the host-side communication interface only.

Figure UART-9 Example of System Construction in Mode 1

Address data transfer by the host CPU triggers communication. Address data is the data when the A/D bit in the SCR register is "1". This data selects a slave CPU as the communication party to establish communication with the host CPU. Ordinary data is the data when the A/D bit in the SCR register is "0". Figure UART-10 shows the flowchart of communication in mode 1.

Since the parity check function cannot be used in this mode, set the PEN bit in the SCR register to "0".

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4

TDRE

SO interrupt

SOUT[n] output

D0 ~ D7 : Data bit

D5

Write to SODR

Request an interrupt to CPU

SOUT[n]

SIN[n]

Host CPU

SO SI SO SI

Slave CPU # 0 Slave CPU #1


258

Figure UART-10 Flowchart of Communication in Mode 1

(Host CPU)

START

Set transfer mode to 1

Set D0-D7 to slave CPU

selection data and A/D bit to

"1" to 1-byte transfer

Set A/D bit to "0"

Enable reception

Communicationcomplete?

Communicate with slave CPU

Disable reception

Communicate withanother slave CPU?

END

Yes

No

Yes

No


259

Baud rates and U-timer reload value setting examples

The tables below list baud rates and setting examples of U-time reload values.

The frequencies in the tables represent peripheral machine clock frequencies. UCC1 indicates the value to which the UCCI bit in the U-timer UTIMC register is set.

"-" indicates that the corresponding entry cannot be used because an error exceeds ± 1 %.

*: There is an error of more than ± 1 %

Asynchronous (start-stop) mode

Baudrate ms 16.5MHz 12.5MHz 10MHz 8.25MHz

1200 833.33 428(UCC1=1) 324(UCC1=1) 259(UCC1=1) 214(UCC1=0)

2400 416.67 214(UCC1=0) 162(UCC1=0) 129(UCC1=0) 106(UCC1=1)

4800 208.33 106(UCC1=1) 80(UCC1=1) 64(UCC1=0) 52(UCC1=1)

9600 104.17 52(UCC1=1) 39(UCC1=1) 31(UCC1=1) 26(UCC1=0)

19200 52.08 26(UCC1=0) 19(UCC1=1) 12(UCC1=1)

38400 26.04 12(UCC1=1) 12(UCC1=1) 57600 17.36 8(UCC1=0) 3(UCC1=1)

10400 96.15 49(UCC1=0) 36(UCC1=1) 29(UCC1=0) 24(UCC1=0)

31250 32.00 15(UCC1=1) 11(UCC1=1) 9(UCC1=0) 62500 16.00 4(UCC1=0)

CLK synchronous mode

Baudrate ms 16.5MHz 12.5MHz 10MHz 8.25MHz

250Ｋ 4.00 　 32(UCC1=0) 　 24(UCC1=0) 　 19(UCC1=0) 　 15(UCC1=1)

500Ｋ 2.00 　 15(UCC1=1) 　 11(UCC1=1) 9(UCC1=0) 7(UCC1=1)

１Ｍ 1.00 7(UCC1=1) 　* 5(UCC1=0) 4(UCC1=0) 3(UCC1=1)


260

6.9 DMAC (DMA Controller)

6.9.1 OverviewThe DMA controller (DMAC) is a module to realize direct memory access (DMA) transfer with the FR71 family. DMA transfer controlled by this module enables many types of data transfer to be performed at high speed without CPU intervention, thereby improving system performance.

Hardware configuration

This module consists mainly of the following components:

• Five independent DMA channels• 5-channel independent access control circuit• 32-bit address registers (reload-specifiable: 2 per channel)• 16-bit transfer count registers (reload-specifiable: 1 per channel)• 4-bit block transfer count registers (1 per channel)• External transfer request input pins: DREQ[3:0] (Channels 0, 1, 2, and 3 only)• External transfer request acknowledge output pins: DACKX[3:0] (Channels 0, 1, 2, and 3 only)• DMA end output pins: DEOPX[3:0] (Channels 0, 1, 2, and only)• Fly-by transfer (memory to I/O, and I/O to memory)

IORX and IOWX are output for I/O-side access signals.• Two-cycle transfer

Main functions

This module has the following major functions for data transfer:

• Multi-channel independent data transfer (5 channels)(1) Priority (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)

(2) Rotation of priority between ch.0 and ch.1

(3) DMAC activation sources

• Dedicated external pin input (Edge or level detection selectable for ch.0-ch.2 only)• Internal peripheral request (Interrupt request sharing, including external interrupts)• Software request (Register write)

(4) Transfer modes

• Demand, burst, step, or block transfer• Addressing mode: 32-bit full addressing (increment, decrement, or fixed)

(The address increment/decrement can be specified between -255 to +255.)

• Data length: Byte, halfword, or word• Single-shot or reload selectable


261

FR core

DREQ0

DACKX0

IORDX

EOPX0

EOTX0

DREQ1

DACKX1

IORDX

EOPX1 OPEN

EOTX1

DMAC(ch.2-4)

External IF

MB91402

* Factors from other than DREQ

DMAC(ch.0)

DMAC(ch.1)

Ethernet MAC IF


262

6.9.2 Register list

(bit) 31 24 23 16 15 08 07 00

ch.0 Control/status register A DMACA0 00000200H

ch.0 Control/status register B DMACB0 00000204H


ch.1 Control/status register B DMACB1 0000020CH




ch.3 Control/status register B DMACB3 0000021CH



General control register DMACR 00000240H

ch.0 Source address register DMASA0 00001000H

ch.0 Destination address register DMADA0 00001004H


ch.1 Destination address register DMADA1 0000100CH




ch.3 Destination address register DMADA3 0000101CH




263

6.9.3 Block diagram

Bu

s c

on

tro

l u

nit

State transition

circuit

DMA controller

Ad

dre

ss c

ou

nte

r

Read/write

control

BLK register

DTC 2-stage registersDTCR

DSAD 2-stage registers

DDAD 2-stage registers

DDNO register

TYPE.MOD,WS

DSS[3:0]

ERIR,EDIR

SADM,SASZ[7:0]

DADM,DASZ[7:0]

SADR

DADR

Se

lecto

rS

ele

cto

rS

ele

cto

r

DDNO

Read

Write

Access

address

Buffer

Selector

Selector

Counter

Counter

Bu

s c

on

tro

l u

nit

DMA transfer request to

bus controller

X-b

us

To interrupt controller IRQ[4:0]

DMA activation

source selector

circuit & request

reception control

Priority

evaluation circuit

Peripheral activation request/stop input

Write back

Co

un

ter

bu

ffe

r

Write back

Co

un

ter

bu

ffe

r

Wri

te b

ack

Buffer

To bus

controller

DMAC 5-channel block diagram

Peripheral interrupt clear MCLREQ

External pin activation request/stop input


264

6.9.4 Register descriptionRegister setting precautions

When the DMAC is set up, some of the bits in the DMAC registers need to be set when no DMA transfer is in process. Setting such bits during operation (transfer) does not guarantee normal operation.

In this section, the asterisk (*) indicates that setting the bit (string) during DMAC transfer affects the operation. Overwrite the bit (string) when DMAC transfer is at a stop (by disabling or suspending DMAC operation).

If such bits are set with DMA transfer disabled (DMACR:DMAE = 0 or DMACA:DENB = 0), the new settings take effect as soon as DMA transfer is enabled.

If such bits are set with DMA transfer suspended (DMACR:DMAH[3:0] ≠ 0000 or DMACA:PAUS = 1), the new settings take effect as soon as DMA transfer is released from the suspended state.

(1) DMAC channels 0 to 4: Control/status registers A

[DMACA0 to DMACA4]

The DMACA0 to DMACA4 registers exist for their respective DMAC channels independently. Each of these registers controls operations of the corresponding DMAC channel.

The DMACA0 to DMACA4 registers consist of the following bits.

(Initial value: 00000000_00000000_0000XXXX_XXXXXXXX bit)

[Bit 31] DENB (Dma ENaBle): DMA transfer enable bit

This bit enables or disables the corresponding transfer channel for DAM transfer.Once enabled, the channel starts DMA transfer when a transfer request issued to that channel is accepted.Any transfer request issued to the channel is invalid when the channel is disabled.Once transfer by the enabled channel has been completed a specified number of times, this bit becomes "0" and transfer stops.Writing "0" to this bit forces the channel to terminate DMA transfer. Before forcibly terminate DMA transfer (by writing "0"), be sure to suspend DMA transfer using the PAUS bit (bit 30) in the DMACA register. If DMA transfer is terminated forcibly without being paused in advance, transferred data is not guaranteed. Use the DSS[2:0] bits (bits 18-16) in the DMACB register to check whether DMA transfer has been terminated.

• When a stop request is accepted at a reset: The bit is initialized to "0".• This bit can be read and written.• If all the channels are disabled by the DMAE bit (bit 15) in the DMAC general control register

(DMACR), writing "1" to this bit has no effect and the stop status is maintained. If DMA transfer is disabled by the above bit (DMAE) when it is enabled by this bit, this bit becomes "0" and transfer is aborted (forcibly terminated).

[Bit 30] PAUS (PAUSe): Suspend command

This bit is used to suspend DMA transfer on the corresponding channel. Once this bit has been set, DMA transfer is suppressed until the bit is cleared again. (The DSS bits hold "1xx" when DMA transfer is suspended.)If the DMAC is activated with this bit set to "1", the channel remains suspended.

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DENB PAUS STRG IS[4:0] Reserved BLK[3:0]

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DTC[15:0]

DENB Function

0 Disable DMA transfer on corresponding channel. (Initial value)

1 Enable DMA transfer on corresponding channel


265

When this bit is "1", any new transfer request is accepted. The transfer does not however start until the bit is cleared. (See (11) "Acceptance of transfer request and transfer" in 6.9.5 Explanation of operation

6.9.5.1 Overview of operation.)

• At a reset: The bit is initializes to "0".• This bit can be read and written.

[Bit 29] STRG (Software TRiGger): Transfer request

This bit controls the generation of a DMA transfer request to the corresponding channel. When "1" is written to this bit a transfer request is generated at the end of the register write and transfer starts on the channel.

If the corresponding channel is not active, however, manipulation of the bit has no effect.

* If a transfer request by this bit occurs simultaneously with DMA activation by the DMAE bit, the transfer request is valid and starts transfer. If a transfer request by this bit occurs simultaneously with a "1" write to

the PAUS bit, the transfer request is valid but not starts DMA transfer until the PAUS bit is returned to "0".

• At a reset: The bit is initialized to "0".• Reading the bit always returns "0".• The valid value to be written is only "1". Writing "0" has no effect on operation.

[Bits 28-24] IS4-IS0 (Input Select) *: Transfer request source selection

These bits are used to select a transfer request source as shown below. Note, however, that the software

transfer request generated by the STRG bit is valid, irrespective of this setting.

PAUS Function

0 Disable DMA transfer on corresponding channel. (Initial value)

1 Enable DMA transfer on corresponding channel

STRG Function

0 Invalid

1 Request DMA transfer.

IS Function00000 Software transfer request only00001

to01101

Setting is prohibited

01110 Detection of DREQ "H" level or rising edge01111 Detection of DREQ "L" level or falling edge10000 Completion of UART0 reception10001 Completion of UART1 reception10010 Completion of UART0 transmission10011 Completion of UART1 transmission10100 External interrupt 010101 External interrupt 110110 Reload timer 010111 Reload timer 111000 External interrupt 211001 External interrupt 311010 Reload timer 211011

to11111

Setting is prohibited


266

• At a reset: The bits are initialized to "00000".• These bits can be read and written.

* When the demand transfer mode has been selected, the IS[4:0] bits can be set to either 01110 or 01111 only. It is therefore prohibited to activate DMA transfer by any other source.

* External request inputs are available only for Channels 0 to 3; they cannot be selected for channel 4. Also, mode setting determines whether to use level detection or edge detection. (Demand transfer is requested upon level detection; other types of transfer are requested upon edge detection.)

[Bits 23-20] (Reserved)

These bits are reserved for future use.

At a reset: The bits are initialized to "0000".

At a write, set the bits to "0000".

[Bits 19-16] BLK3-BLK0 (BLocK size): Block size specification

These bits specify the block size for block transfer on the corresponding channel. The value of these bits determines the number of words (precisely, the number of repetitions of the set data width) in each transfer unit. Set 01H (size 1) for no block transfer. (In demand transfer mode, the value of these bits is

ignore. The block size is 1 in that mode.)

• At a reset: The bits are not initialized.• These bits can be read and written.• Setting the bits to "0" specifies a block size of 16 words.• The value read from the bits is a block size (reload value).

[Bits 15-0] DTC (Dma Terminal Count register) *: (Transfer count register)

These bits serve as a register that stores a transfer count. The register length is 16 bits.

The register for each channel has a dedicated reload register. When the register for a channel is used, the register is automatically returned to the initial value at the end of transfer if the channel permits

transfer counter register reload.

When DMA transfer is activated, the data in this register is stored to the counter buffer of the DMA- dedicated transfer counter. The counter decrements the count by one for each transfer unit. At the end of DAM transfer, the content of the counter buffer is written back to this register. The transfer count cannot therefore be read during DMA transfer in real time.

• At a reset: The bits are not initialized.• These bits can be read and written. However, DTC access must always be performed in halfword or

word length.• The value read from the bits is always a count value; a reload value cannot be read.• At a reset: The bits are not initialized to.

BLK [3:0] Function

XXXXb Specify block size for corresponding channel

DTC [15:0] Function

XXXXh Specify transfer count of corresponding channel


267

(2) DMAC channels 0 to 4: Control/status registers B

[DMACB0 to DMACB4]

The DMACB0 to DMACB4 registers exist for their respective DMAC channels independently. Each of these registers controls operations of the corresponding DMAC channel.

The DMACB0 to DMACB4 registers consist of the following bits.

(Initial value:00000000_00000000_00000000_00000000 bit)

[Bits 31, 30] TYPE (TYPE) *: Transfer type setting

These bits are used to select the operation type of the corresponding channel as shown below.

Two-cycle transfer mode: This mode transfers data by repeating the read and write operations the set number of times of transfer according to the source address (DMASA) and destination address (DMADA) settings. Both of the transfer source and destination can be addressed in the entire area (32-bit address space).

Fly-by transfer mode: This mode transfers data between internal and external resources in one cycle according to the destination address (DMADA) set as a memory address. The memory address must be specified in an external area.


[Bits 29, 28] MODE (MODE) *: Transfer mode setting

These bits are used to select the operation mode for the corresponding channel as follows:


[Bits 27, 26] WS (Word Size): Transfer data width selection

These bits are used to select the transfer data width for the corresponding channel. Data is transferred for the specified number of times in units of the data width set by these bits.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TYPE[1:0] MOD[1:0] WS[1:0]SADM

DADM

DTCR

SADR

DADR

ERIR

EDIR

DSS[2:0]

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SASZ[7:0] DASZ[7:0]

TYPE[1:0] Function

00 two-cycle transfer (Initial value)

01 fly-by: memory to IO transfer

10 fly-by: IO to memory transfer

11 Setting is prohibited

MOD[1:0] Function

00 Block/step transfer mode (Initial value)

01 Burst transfer mode

10 Demand transfer mode



268


[Bit 25] SADM (Source-ADdr. Count-Mode select) *: Source address count mode setting

These bits specify the type of address update for each transfer to the source address of the corresponding channel.

The address increment or decrement mode increments or decrements the source address according to the source address count width (SASZ) setting after every transfer and writes the next access address to the corresponding address register (DMASA) on termination of DMA transfer.Therefore the source address register is not updated until DMA transfer is finished.For the fixed-address mode, set this bit for address increment or decrement mode and set the source address count size (SASZ) to “0”.

• At a reset: The bit is initialized to "0".• This bit can be read and written.

[Bit 24] DADM (destination-ADdr. Count-Mode select) *: Destination address count mode setting

These bits specify the type of address update for each transfer to the destination address of the corresponding channel.

The address increment or decrement mode increments or decrements the destination address according to the destination address count width (DASZ) setting after every transfer and writes the next access address to the corresponding address register (DMADA) on termination of DMA transfer.Therefore the destination address register is not updated until DMA transfer is finished.For the fixed-address mode, set this bit for address increment or decrement mode and set the destination

address count size (DASZ) to “0”.


[Bit 23] DTCR (DTC-reg. Reload) *: Transfer count register reload control)

This bit controls the reload function for the transfer count register of the corresponding channel.

If the reload function is enabled by this bit, the transfer count in the register is reset to the initial value after transfer to prepare for the next transfer.

If the reload function of the transfer counter is disabled, the transfer is finished after a single shot even when the address register reload function has been specified.

WS [1:0] Function

00 Transfer in bytes (Initial value)

01 Transfer in halfwords

10 Transfer in words


SADM Function

0 Increment source address. (Initial value)

1 Decrement source address.

DADM Function

0 Increment destination address. (Initial value)

1 Decrement destination address.


269


[Bit 22] SADR (Source-ADdr.-reg. Reload) *: Source address register reload control

This bit controls the reload function for the source address register of the corresponding channel.

If the reload function is enabled by this bit, the source address register value is reset to the initial value after transfer.

If the reload function of the transfer counter is disabled, the transfer is finished after a single shot even when the address register reload function has been specified. In this case, the address register stops with the initial value reloaded.

If the reload function is disabled by this bit, the value held in the address register when transfer is finished is the access address that follows the last address. (When the address increment mode has been

selected, the address register value is the incremented address.)


[Bit 21] DADR (Dest.-ADdr.-reg. Reload) *: Destination address register reload control

This bit controls the reload function for the destination address register of the corresponding channel.

If the reload function is enabled by this bit, the destination address register value is reset to the initial value after transfer.

The other features of this bit are equivalent to those of the SADR bit (bit 22).


[Bit 20] ERIE (ERror Interrupt Enable) *: Error interrupt output enable

This bit controls the generation of an interrupt at abnormal termination resulting from an error. DSS2 to DSS0 indicate the type of the error. Note that only specific termination sources cause this interrupt. (See

the description of the DSS2-DSS0 bits.)


DTCR Function

0 Disable transfer count register reload. (Initial value)

1 Enable transfer count register reload.

SADR Function

0 Disable source address register reload. (Initial value)

1 Enable source address register reload.

DADR Function

0 Disable destination address register reload. (Initial value)

1 Enable destination address register reload.

ERIR Function

0 Disable error interrupt request output. (Initial value)

1 Enable error interrupt request output.


270

[Bit 19] EDIE (EnD Interrupt Enable) *: End interrupt output enable

This bit controls the generation of an interrupt at normal termination.


[Bits 18-16] DSS2-DSS0 (DMA Stop Status) *: Transfer stop source indication

These bits present a three-bit code (exit code) indicating the source of the stop or end of DMA transfer on the corresponding channel. The table below lists the exit codes and their meanings.

The transfer stop request is set only when the request is generated by a peripheral or when the external pin DSTP function is used.

*: The "Interrupt" column in the above table indicates the type of interrupt request which can be generated in each case.

• At a reset: The bits are initialized to "000".• Writing "000" to the bits clears them.• Although the bits can be read and written, the valid value to be written is only "000".

[Bits 15-8] SASZ (Source Addr count SiZe) *: Source address count size setting

These bits specify the increment to or decrement from the source address (DMASA) for each transfer on the corresponding channel. The value of these bits indicates the address increment or decrement for each transfer unit. The address increment or decrement mode is selected by the source address count mode (SADM) setting.

• At a reset: The bits are not initialized.• These bits can be read and written.

[Bits 7-0] DASZ (Des Addr count SiZe) *: Destination address count size setting

These bits specify the increment to or decrement from the destination address (DMADA) for each transfer on the corresponding channel. The value of these bits indicates the address increment or decrement for each transfer unit. The address increment or decrement mode is selected by the

destination address count mode (DADM) setting.

• At a reset: The bits are not initialized.• These bits can be read and written.

EDIE Function

0 Disable end interrupt request output. (Initial value)

1 Enable end interrupt request output.

DSS[2:0] Function Interrupt

000 Initial value None

x01 Address error (underflow or overflow) Error

x10 Transfer stop request Error

x11 Normal termination End

1xx DMA suspended (DMAH,PAUS bit, interrupt, etc) None

SASZ[7:0] Function

XXh Specify source address increment or decrement between 0 and 255

DASZ[7:0] Function

XXh Specify destination address increment or decrement between 0 and 255


271

(3) DMAC channels 0 to 4: Source/destination address setting registers

[DMASA0-DMASA4 and DMADA0-DMADA4]

The DMASAn and DMADAn registers exist for their respective DMAC channels independently. Each of these registers controls operations of the corresponding DMAC channel.

The registers consist of the following bits.

(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX bit)

(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX bit)

The DMAC source/destination address registers are a group of registers to store source and destination addresses. Each register is 32 bits long.

[Bits 31-0] DMASA (DMA Source Addr) *: Source address setting

This register sets the DMA source address.

[Bits 31-0] DMADA (DMA Destination Addr) *: Destination address setting

This register sets the DMA destination address.

When DMA transfer is activated, the data in this register is stored to the counter buffer of the DMA- dedicated transfer counter. The counter increments or decrements the count as specified for each trans-fer unit. At the end of DAM transfer, the content of the counter buffer is written back to this register. The address counter value cannot therefore be read during DMA transfer in real time.

The register for each channel has a dedicated reload register. When the register for a channel is used, the register is automatically returned to the initial value at the end of transfer if the channel permits trans-fer counter register reload. This does not affect other address registers.

• At a reset: The register is not initialized.• The register can be read and written. However, access to the register must always be performed in

32- bit data length.• The value read from the register is the last address during transfer or the next access address upon

termination of transfer. No reload value can be read. Transfer address cannot therefore be read in read time.

Precaution:

Do not set these registers to the addresses of any DMAC's own register. DMA transfer to DMAC registers cannot be performed.

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DMASA[31:16]

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMASA[15:0]

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DMADA[31:16]

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMADA[15:0]


272

(4) DMAC channels 0 to 4: DMAC General Control Register (DMACR)

The DMAC general control register (DMACR) controls operations of five channels of the DMAC. Be sure to access this register in byte length.

The DMACR consists of the following bits

(Initial value:0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX bit)

[Bit 31] DMAE (DMA Enable): DMA transfer enable

This bit controls DMA transfer on all the DMA channels.

When DMA transfer is disabled by this bit, transfer is barred on any of the DMAC channels, irrespective of the DMA transfer enable/disable setting for each channel or its operation status. A channel currently performing for transfer cancels the request and stops transfer at the block boundary. In the disabled status, any attempt to activate each channel is invalid.

If DMAE transfer is enabled by this bit, the activation and termination of each channel is valid. Note, however, that a channel is not activated only by enabling DMA transfer using this bit.

Writing "0" to this bit forces all the channels to terminate DMA transfer. Before forcibly terminate DMA transfer (by writing "0"), be sure to suspend DMA transfer using the DMAH[3:0] bits (bits 27-24) in the DMACR. If DMA transfer is terminated forcibly without being paused in advance, transferred data is not guaranteed. Use the DSS[2:0] bits (bits 18-16) in the DMACB register to check whether DMA transfer has been terminated.


[Bit 28] PM01 (Priority mode ch0/1 robine): Channel priority reverse control

This bit selects whether to reverse priority between channels 0 and 1 for each transfer.


bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DMAE

⎯ PM01

DMAH[3:0] ⎯

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

⎯

DMAE Function

0 Disable DMA transfer on all channels (Initial value)

1 Enable DMA transfer on all channels

PM01 Function

0 Fix channel priority (ch0 > ch1) (Initial value)

1 Reverse channel priority (ch0 > ch1 ←→ ch1 > ch0)


273

[Bit 27-24] DMAH (DMA Halt): DMA halt

These bits are used to pause all the DMA channels. Once this bit has been set, DMA transfer on all channels is suspended until the bit is cleared again.

If the DMAC is activated with this bit set to "1", all the channels remain suspended.

Any new transfer request is valid when it occurs at the channel enabled for DMA transfer (DENB=1) while this bit is set. The transfer is started as soon as the bit is cleared.

• At a reset: The bit is initialized to "0".

• This bit can be read and written.

[Bits 30, 29, 23-0] (Reserved): These bits are not used.

The values read from these bits are undefined.

DMAH [3:0] Function

0000 Enable DMA transfer on all channels (Initial value)

other than 0000

Suspend DMA transfer on all channels


274

6.9.5 Descriptions of operation6.9.5.1 Overview of operation

The DMAC built in the FR71 family is a multifunctional DMA controller to control data transfer at high speed without CPU instructions.

[Main operations]

• Functions are set independently to each transfer channel.• Even when a channel is enabled for operation, the channel does not start transfer until a set transfer

request is detected.• When the transfer request is detected, the DMAC issues a DMA transfer request to the bus controller

to acquire the bus access right using control of the bus controller to start transfer.• The transfer sequence follows the mode settings made independently for each channel.

[Transfer modes]

Each DMA channel performs transfer in the transfer mode set by the MOD[1:0] bit in the DMACB register.

Block/step transfer

The DMAC transfers only one block transfer unit per transfer request and suspends the transfer request to the bus controller until the next transfer request is received.Block transfer unit: Block size set (by the BLK[3:0] bits in the DMACA register)

Burst transfer

The DMAC executes transfer the specified number of times of transfer continuously on a transfer request.Specified number of times of transfer: Block size x transfer count (DMACA BLK[3:0] x DMACA DTC[15:0])

Demand transfer

The DMAC executes transfer continuously either until the external transfer request input (DREQ pin level detection) is finished or until the specified number of times of transfer is reached.In demand transfer mode, the specified number of times of transfer matches the transfer count (DTC[15:0] in the DMACA register). The block size is fixed at "1"; the relevant register value is ignored.

[Transfer type]

Two-cycle transfer (Normal transfer)

The DMAC handle each combination of read and write as a single unit of operation.

The DMAC reads data from the address held in the source address register and writes the data to the address in the destination address register.

Fly-by transfer (memory to I/O)

The DMAC handles a read as a single unit of operation.

When DMA transfer is started in fly-by transfer mode, the DMAC issues a fly-by transfer (read) request to the bus controller and the bus controller causes the external interface to perform fly-by transfer (read).

Fly-by transfer (I/O to memory)

The DMAC handles a write as a single unit of operation.

The operations performed are the same as those for fly-by transfer (memory to I/O).

The fly-by transfer access area must always be an external area.


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[Transfer addresses]

The following types of addressing are available, which are set independently for the source and destination of transfer on each channel.

The address registers (DMASA and DMADA) are set differently between two-cycle transfer and fly-by transfer.

Addressing for two-cycle transfer

The values read from the address holding registers (DMASA and DMADA) are used for access.When a transfer request is received, the DMAC stores the addresses from the address registers to temporary storage buffers and starts transfer. The address counter generates the next access address (in increment, decrement, or fixed-address mode) at each access and returns the address to the temporary storage buffer. The address in the temporary storage buffer is written back to the address register (DMASA, DMADA) at the end of each block transfer unit.During DMA transfer, therefore, the values in the address registers (DMASA and DMADA) are updated only for each block transfer unit and cannot be read in real time.

Addressing for fly-by transfer

For fly-by transfer, the value read from the destination address register (DMADA) is used for access. The source address register (DMASA) is ignored. Be sure to set the address to a location in an external area.When a transfer request is received, the DMAC stores the address from the address register to the temporary storage buffer and starts transfer. The address counter generates the next access address (in increment, decrement, or fixed-address mode) at each access and returns the address to the temporary storage buffer. The address in the temporary storage buffer is written back to the address register (DMADA) at the end of each block transfer unit.During DMA transfer, therefore, the value in the address register (DMADA) are updated only for each block transfer unit and cannot be read in real time.

[Number of times of transfer and the termination of transfer]

Number of times of transfer

The transfer count register is decremented by one (-1) at the end of each block transfer unit. Once the register value has become "0" after the specified number of times of transfer, the DMAC terminates or reactivates the channel (1) with the exit code displayed.

(1) If transfer count register reload has been disabled for the channel, the DMAC terminates transfer at that point of time. If it has been enabled, the register value is initialized and the channel enters the transfer wait state. (DMACB:DTCR)

Termination of transfer

The termination of transfer is triggered by the following events (transfer termination sources). When transfer terminates, an exit code is displayed, indicating the termination source. (DMACB:DSS[2:0])

• Transfer repeated the specified number of times (DMACA BLK[3:0] x DMACA DTC[15:0]) => Normal termination

• Transfer stop request from peripheral circuit or external pin (DSTP) => Error• Address error => Error• Reset => Reset

When transfer terminates by each type of termination source, the corresponding exit code is displayed by transfer stop source indication (DSS) by a transfer end interrupt or error interrupt can be generated.


276

(2) Setting a transfer request

DMA transfer is activated by the three types of transfer requests below. The software request can always be used, irrespective of the settings for other requests.

External transfer request

A transfer request is generated by the input to a single input pin provided for each of only channels 0 to 3. (DREQ0, 1, 2, and 3)The effective input is selected from among the following sources by transfer type and transfer request source setting.

Edge detection

Edge detection is selected when the transfer type is block, step, or burst transfer.

• Falling edge detection: Set by the transfer request source select register. DMACA IS[4:0] = 01110• Rising edge detection: Set by the transfer request source select register. DMACA IS[4:0] = 01111

Level detection is selected when the transfer type is demand transfer.

• "H"-level detection: Set by the transfer request source select register. DMACA IS[4:0] = 01110• "L"-level detection: Set by the transfer request source select register. DMACA IS[4:0] = 01111

Internal peripheral request

A transfer request is generated by an interrupt from an internal peripheral circuit.Set a peripheral interrupt type as a transfer request trigger for each channel. (DMACA IS[4:0] = 1xxxx)This request cannot be used along with an external transfer request.

Precaution:

An interrupt request used for a transfer request can look like an interrupt request to the CPU. Disable the interrupt using the ICR register of the interrupt controller.

Software request

A transfer request is generated when the trigger bit in the register is written. (DMACA:STRG)This request can always be used independently of the above two requests.If a software request is issued upon activation (transfer enabled), the DMAC promptly outputs a DMA transfer request to the bus controller to start transfer.


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(3) Transfer sequence

The transfer type and transfer mode can be set independently for each channel to determine the operation sequence immediately after the activation of DMA transfer. (DMACB:TYPE[1:0] and MOD[1:0] settings)

Selecting a transfer sequence

The operation sequence can be selected from among the following options depending on the register settings:

• Two-cycle burst transfer• Two-cycle demand transfer• Two-cycle block/step transfer• Fly-by burst transfer • Fly-by demand transfer• Fly-by block/step transfer

Two-cycle burst transfer

Transfer is executed for the specified number of times on a transfer request. For two-cycle transfer, the source and destination addresses can be specified within the entire 32-bit area.The transfer activation source can be selected from among: peripheral transfer request, software transfer request, external pin (DREQ) edge input detection request.

(Acceptable transfer address table)

[Features of burst transfer]

• Once a transfer request has been received, transfer is repeated until the transfer count register value becomes “0”. The number of times of transfer is "block size x transfer count".(DMACA:BLK[3:0] x DMACA DTC[15:0])

• Any other request generated during transfer is ignored.• If the reload function for the count register is effective, the next transfer request is accepted after the

end of transfer.• If a transfer request is received from another channel with a higher priority during transfer, the DMAC

switches execution to the new channel at a boundary between units of transfer (block) and does not return to the former channel until the transfer request from the new channel is cleared.

(Example of burst transfer started at rising edge of external pin input. Number of blocks = 1, Number of times of transfer = 4)

Fly-by burst transfer

Fly-by burst transfer is almost the same as two-cycle burst transfer. Only the differences are: 1) the transfer area is an external area only, 2) the transfer unit is only "read" (for memory to I/O transfer) or

"write" (for I/O to memory transfer).


Source addressing Direction Destination addressing

Entire 32-bit area → Entire 32-bit area


Not required (Invalid) → External area

CPU SA DA SA SA SADA DA DA CPU

4 3 2 1 0

Transfer request (rising edge)

Bus operation

Transfer count

Transfer end


278

Two-cycle demand transfer

The demand transfer sequence is performed only when the "H" or "L" level of the DREQ pin has been selected as the transfer request source. (Use the IS[3:0] bits in the DMACA register for level selection.)

[Features of continuous transfer]

• The transfer request is checked for each unit of transfer. As long as the external input level matches the transfer request level, the DMAC continues transfer without clearing the transfer request. When the external input level changes, the DMAC clears the request and stops transfer at a boundary between units of transfer. This is repeated up to the specified number of times of transfer.

• The other operations are the same as those for burst transfer.

(Example of demand transfer started on detection of "H" level at external pin. Number of blocks = 1, Number of times of transfer = 3)


Precaution:

For demand transfer, be sure to set either or both of the source and destination addresses to a location(s) within an external area. Demand transfer always requires access to an external area because DMA transfer in demand transfer mode is executed to the external bus timings.

Fly-by demand transfer

Fly-by demand transfer is almost the same as two-cycle demand transfer. Only the differences are: 1) the transfer is an external area only, 2) the transfer unit is only "read" (for memory to I/O transfer) or




External area → External area

External area → Internal IO

External area → Internal RAM

Internal IO → External area


Not required (Invalid) → External area

CPU SA DA SA SADA DA CPU

3 2 1 0

CPU

Transfer request (H level)

Bus operation

Transfer count

Transfer end


279

Two-cycle step/block transfer

In this mode, transfer is executed only for the specified number of times on a transfer request. For step/

block transfer, the source and destination addresses can be specified within the entire 32-bit area.


Step transfer

Setting the block size to "1" selects the step transfer sequence.

[Features of step transfer]

• Once a transfer request has been received, the DMAC executes one unit of transfer and clears the transfer request to complete the transfer. (The DMAC cancels the DMA transfer request issued to the buss controller.)

• Any other request generated during transfer is ignored.• If a transfer request is received from another channel with a higher priority during transfer, the DMAC

terminates the current transfer and switches execution to the new channel to start the new transfer. In step transfer, therefore, channel priority is meaningful only when transfer requests are generated simultaneously.

Block transfer

Setting the block size to a value other than "1" selects the block transfer sequence.

[Features of block transfer]

• The transfer sequence is exactly the same as that for step transfer, except that a single unit of transfer consists of several transfer cycles (as many as the number of blocks).

(Example of block transfer started at rising edge of external pin input. Number of blocks = 2, Number of times of transfer = 2)

Fly-by step/block transfer

Fly-by step/block transfer is almost the same as two-cycle step/block transfer. Only the differences are:

1) the transfer is an external area only, 2) the transfer unit is only "read" (for memory to I/O transfer) or




Entire 32-bit area → Entire 32-bit area


Not required → Extra area

CPU SA DA SA SADA DA CPU

2 1 10

CPU

00

SA DA

2 1

Transfer request (rising edge)

Bus operation

Block count

Transfer count

Transfer end


280

(4) General information on DMA transfer

Block size

• A unit of transfer is the set of data corresponding to the number (multiplied by the data width) specified in the block size setting register.

• Since the amount of data transferred in one transfer cycle depends on the data width setting, the unit of transfer will be the number of block-size transfer cycles.

• Block transfer does not stop until the end of a unit of transfer even if a transfer request of a higher priority is received or a transfer halt request occurs during transfer. Although this protects data in a block not to be divided or suspended, it may deteriorate system response if the block size is large.

• Block transfer stops immediately only when the reset occurs, the transferring data is not secured.

Reload functions

This module allows the following three types of reload functions to be set for each channel:

(1) Transfer count register reload function

After the specified number of times of transfer, this function resets the transfer count register to the initial value to be ready for receiving the next transfer request.Set this function to repeat an entire transfer sequence.If this function is not set, the count register value after the series of transfer remains 0 and no more transfer is executed.

(2) Source address register reload function

After the specified number of times of transfer, this function resets the source address register to the initial value.Set this function to repeat transfer from a fixed area in the source address area.If the reload function is not specified, the source address register value after the series of transfer becomes the next address. This function is used when the address area is not fixed.

(3) Destination address register reload function

After the specified number of times of transfer, this function resets the destination address register to the initial value.Set this function to repeat transfer to a fixed area in the destination address area.(Same as (2) above.)

• If only the reload functions of the source and destination registers are enabled, only the address register values are reset, without re-activation of transfer, after the specified number of times of transfer.

*: Operation modes and special example of reloading

• If the transfer count register reload function is enabled in continuous transfer mode based on the external pin input level, the module reloads the register value to continue transfer even when transfer is terminated despite the continuous supply of input. The exit code is set also in this case.

• Do not specify the reload function to stop transfer once and start again from input detection.• If the transfer count register reload function is enabled in burst, block, or step transfer mode, the

module reloads the register value at the end of transfer to complete the process once. Then the module executes no transfer until a new transfer request input is detected.


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(5) Addressing mode

The destination and source addresses for transfer are specified independently for each channel.

The source and destination addresses are specified in the following ways. Set them appropriately depending on the transfer sequence to be used.

Using the address registers

• For two-cycle transfer mode, set the source address setting register (DMASA) and destination address setting register (DMADA) to the transfer source and destination addresses, respectively.

• For fly-by transfer mode, set the source address setting register (DMASA) to a memory address. The value in the destination address setting register (DMADA) is ignored in this case.

[Features of address registers]

Each address register is up to 32 bits long. If the register length is 32 bits, the entire space on the memory map can be accessed.

[Functions of address registers]

• Each address register is read at each access and the value is released to the address bus.• At the same time, the address counter calculates the next access address and the address register is

updated according to the result of calculation.• The address calculation type is selected from Increment, Decrement, and Fixed independently for

each channel, destination, and source. Increment and decrement width of address varies according to the value of address count size setting register. (DMACB: SASZ, DASZ)

• If the reload function is disabled, the last address calculation result is left in the address register at the end of transfer.

• When the reload function is enabled, the initial address value is reloaded.

Precautions:

• If 32-bit full address calculation causes an overflow or underflow, it is detected as an address error and the transfer on the channel is suspended. (See items (15) later in this section.)

• Do not set registers to the address of any DMAC's own register.• For demand transfer, be sure to set either or both of the source and destination addresses to a

location(s) within an external area.• Do not use the DMAC to transfer data to any DMAC's own register.


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(6) Types of data transferred

Select a data length (data width) for a unit of transfer from among the following:

• byte • halfword • word

The word boundary specification is observed even in DMA transfer. If a specified destination or source address does not match the selected data length, therefore, the wrong lower bits are ignored.

• Word: The actual access address is four bytes, starting with lower two bits of "00".• Halfword: The actual access address is two bytes, starting with a lower one bit of "0".• Byte: The actual access address matches the specified address.

If the lower bits of the source and destination addresses do not match, the set addresses are output to the internal address bus as they are. At each transfer point on the bus, however, the addresses are cor-rected for access according to the above rules.

(7) Transfer count control

Specify the transfer count within the length of up to 16 bits (1 to 65536 times). Set a transfer count in the transfer count register (DMACA: DTC).

When transfer is started, the register value is stored to the temporary storage buffer and decremented by the transfer counter. When the counter value becomes 0, the expected end of transfer is detected and the channel stops transfer or gets ready for re-activation (if the reload function has been specified).

[Features of the transfer count register group]

• Each register length is 16 bits.• All registers have a dedicated reload register.• If the DMAC is activated when the register value is 0, data will be transferred 65536 times.

[Reloading]

• Reloading valid only to a register with a reload function provided and enabled.• The initial value of the count register is saved to the reload register at the start of transfer.• If the transfer counter value becomes 0, the end of transfer is reported and the initial value is read

from the reload register and written to the count register.

(8) CPU control

When a DMA transfer request is received, the DMA issues a transfer request to the CPU.

The bus controller passes the internal bus access right to the DMA at a boundary of bus operations to start DMA transfer.

DMA transfer and interrupts

• Basically, no interrupts are accepted during DMA transfer until the transfer is finished.• When a DMA transfer request occurs when an interrupt is being performed, the request is accepted and

the interrupt service is stopped until the end of transfer.• If an NMI request or an interrupt request of a higher level than the hold suppression level set by the

interrupt controller is generated, exceptionally, the DMAC temporarily cancels the transfer request from the bus controller at a boundary between units of transfer (blocks) and pauses the transfer until the interrupt request is cleared. In this period, the DMAC holds the transfer request internally. After the interrupt request is cleared, the DMAC re-issues the transfer request and acquires the bus access right to start DMA transfer again.

Suspending DMA transfer

• When an interrupt source of a higher priority is generated during DMA transfer, the FR71 family suspends the DMA transfer and causes a branch to the corresponding interrupt routine. This mechanism remains in effect as long as an interrupt request exists. If the interrupt source is cleared, however, the suspend mechanism stops working and the interrupt service routine restarts the DMA transfer. Use the DMA suspend function to prevent the routine handling an interrupt source which interrupts DMA transfer from restarting the DMA transfer after the interrupt source is cleared. The DMA


283

suspend function is enabled by writing a value other than "0" to the DMAH[3:0] bits in the DMA general control register; it is disabled by writing "0" to the bits.

• This function is mainly used in an interrupt service routine. In the interrupt service routine, increment the DMA suspend register by one before clearing the interrupt source. THis prevents further DMA trans-fer from being performed. Before returning control after servicing the interrupt, decrement the value in the DMAH[3:0] bits by one. When the performed interrupt is a multi-level interrupt, the DMAH[3:0] value does not yet become 0, suppressing DMA transfer continuously. Otherwise, the DMAH[3:0] value becomes 0, enabling DMA requests immediately.

Precautions• Since the DMA suspend register is four bits long, the DMA suspend function cannot be used for

multi-level interrupts exceeding 15 levels.• For DMA tasks, be sure to assign an interrupt priority level at least 15 levels higher than other tasks'

levels.

(9) Hold arbitrationThe external bus hold request based on BREQ and the DMA transfer request by this module have the following relationships.

DMA transfer request in external hold statusDMA transfer starts but stops immediately when the external bus area is accessed. DMA transfer starts again as soon as the external hold status is cleared.

External hold request during DMA transferThis establishes the external hold status. Access by DMA transfer to the external bus area immediately stops the DMA transfer. DMA transfer starts again as soon as the external hold status is cleared.

DMA transfer request and external hold request occurring simultaneouslyThis establishes the external hold status and starts DMA access internally. Access by DMA transfer to the external bus area immediately stops the DMA transfer. DMA transfer starts again as soon as the external hold status is cleared.

(10) Starting DMA transfer

All of the DMAC channels must be enabled for operation before the starting of DMA transfer can be controlled independently for each channel.

Enabling all channels for operationBefore activating each of the DMAC channels, enable them all for operation using the DMA enable bit (DMACR:DMAE). If the bit is not set, any activation setting or transfer request will be invalid.

Activating transferSet the transfer enable bit in the control register for each channel to activate transfer on that channel. When a transfer request to the activated channel is accepted, DMA transfer starts in the specified mode.

Restarting from pause statusIf transfer is paused by channel-specific control or DMA general control before activation, transfer activation does not clear the pause status. Transfer requests generated in that pause status are received and held. The transfer is restarted when the pause status is cleared.

(11) Reception of transfer request and transfer• When the channels are activated, the DMAC starts sampling set transfer requests from each channel.• If a transfer request is detected when edge detection has been selected as the external pin activation

source, the DMAC holds the request internally until the transfer request clear conditions are satisfied. (When the external pin activation source has been selected for block, step, or burst transfer.)

• When level detection as the external pin activation source or peripheral interrupt activation has been selected, the DMAC continues transfer until the transfer request is cleared. Once it has been cleared, the DMAC stops transfer after processing a singe unit of transfer. (Demand transfer/peripheral interrupt activation)


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A peripheral interrupt is handled as an interrupt activated upon level detection. Use the DMAC to clear the interrupt.

• A transfer request is always received even when transfer is being executed on a transfer request from another channel. After each unit of transfer, the next processing channel is determined by checking the priority.

(12) Clearing peripheral interrupts by DMAC

• The DMA has the function for clearing a peripheral interrupt. This function works when "peripheral interrupt" has been selected as the DMA activation source. (IS[4:0] = 1xxxx)

• The function clears a peripheral interrupt only when the interrupt has been activated by the selected activation source. That is, the function clears only the interrupts generated by the IS[4:0]-specified type of transfer request source.

Interrupt clear signal generation timings

• The interrupt clear signal generation timing varies with the transfer mode. (See the operation flow of each mode.)[Block/step transfer]

When block transfer has been selected, the clear signal is generated at the end of each block (step) transfer.

[Burst transfer]

When burst transfer has been selected, the clear signal is generated when the specified number of times of transfer has been completed.

[Demand transfer]

In demand transfer mode, only activation requests from the external pin are supported and the clear signal is not generated accordingly.

(13) Suspending DMA transfer

DMA transfer is suspended in the following conditions:

Suspending transfer by writing to the control register

(Pausing each channel independently or halting all channels collectively)

If the pause bit is set, transfer on the corresponding channel is suspended until the pause cancel setting is made. Use the DSS bit to check the transfer end status.

Transfer is restarted when the pause status is cleared.

NMI or hold suppression level interrupt being performed

If an NMI request or an interrupt request of a higher level than the hold suppression level is generated, the DMAC suspends all the current transfer channels at a boundary between units of transfer and releases the bus access right to give priority to the NMI/interrupt handler. The DMAC holds a transfer request accepted during NMI/interrupt handling and waits until NMI handling is finished.

The request-held channel restarts transfer after NMI/interrupt handling.

(14) Terminating DMA transfer and disabling all channels

Termination of DMA transfer is controlled independently for each channel. In addition, all channels can be disabled at one time as required.

Terminating DMA transfer

If the reload function is disabled, transfer stops as soon as the transfer count register value becomes 0. The exit code indicating "normal termination" is displayed and any subsequent transfer request becomes invalid. (DMACA:Clear the DENB bit.)

If the reload function is enabled, the transfer count register is reloaded with the initial value as soon as its value becomes 0. The exit code indicating "normal termination" is displayed and the next transfer request is awaited. (DMACA:Do not clear the DENB bit.)


285

Disabling all channels

If all channels are disabled using the DMA enable bit (DMAE), all DMAC channels including ones in operation stop. Simply using the DMAE bit to enable all the channels for DMA transfer does not start DMA transfer until each channel is activated. Any interrupt is not generated when all the channels are disabled

(15) Termination on error

DMA transfer terminates normally after the specified number of times of transfer. It is also terminated by errors or abortion.

Transfer stop request from peripheral circuit

Some peripheral circuits that output a transfer request might generate a transfer stop request if an abnormal status is detected (e.g. reception or transmission error from a communication peripheral).

When this transfer request is received, the DMAC reports "Transfer stop request" by the exit code and stops transfer on the corresponding channel.

* For details on the transfer stop request generating conditions, refer to the specifications of each peripheral circuit.

Address error

In each addressing mode, the following inappropriate addressing is detected as an address error.

(Address counter overflow or underflow when a 32-bit address is specified)

If an address error is detected, the exit code indicating "address error" is displayed and transfer on the corresponding channel is stopped.

IS FunctionTransfer stop

request

00000 Software transfer request only

No

00001to

01101(Setting is prohibited)

01110 Detection of DREQ "H" level or rising edge

01111 Detection of DREQ "L" level or falling edge

10000 Completion of UART0 reception

Yes10001 Completion of UART1 reception

10010 Completion of UART0 transmission

10011 Completion of UART1 transmission

10100 External interrupt 0

No


10110 Reload timer 0

10111 Reload timer 1



11010to

11111(Setting is prohibited)


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(16) DMAC interrupt control

In addition to peripheral interrupts that result in transfer requests, the following interrupts can be output to each DMAC channel:

• Transfer end interrupt: Generated only upon normal termination• Error interrupt:Transfer stop request from peripheral circuit (Error traceable to peripheral)

Address error (Error traceable to software)

These interrupts are all output according to the contents of exit codes.

To clear these interrupt requests, write "000" to the exit code bits (DSS2 to DSS0) in the DMACS register. Be sure to clear these bits before reactivating DMA transfer.

If the reload function is enabled, transfer restarts automatically but the exit code is not cleared and held until a new exit code is written at the end of the next transfer.

Only one termination source can be displayed by the exit code. If several sources occur simultaneously, therefore, the result of priority evaluation is displayed. The interrupt generated at this time conforms to the currently displayed exit code.

The priorities of exit codes are as follows (in descending order of priorities):

1. Reset

2. Clear by writing "000"

3. Transfer stop request by peripheral circuit or external pin input (DSTP)

4. Normal termination

5. Termination on address error

6. Channel selection and control

(17) DMA transfer in sleep mode

• The DMAC can operate even in sleep mode.• For DMAC operation in sleep mode, take the following precautions:

(1) Any DMAC register cannot be updated because the CPU is suspended. Finish setting the required DMAC registers before entering the sleep mode.

(2) The sleep mode is canceled by an interrupt. If "peripheral interrupt" has been selected as the DMAC transfer request source, use the interrupt controller to disable interrupts.

To prevent a DMAC end interrupt from canceling the sleep mode, disable the interrupt in the same way.

(18) Channel selection and control

Up to five transfer channels can be set at the same time. Basically, function can be set independently for each of the channels.

Channel priority

DMA transfer cannot be executed simultaneously on several channels but on a single channel only. The individual channels are therefore assigned priorities.

There are two prioritization modes, fixed and rotational, either of which is selected for each channel group (described later).

(1) Fixed mode

Priorities are always given to channels in ascending order of channel numbers:

(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)

If a transfer request of a higher priority is accepted during transfer, the transfer channel is switched to the higher-priority channel after one unit of transfer (value set in the block size setting register x data width).

As soon as the higher-priority transfer is completed, the transfer on the original channel is resumed.


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(2) Rotational mode (only between channels 0 and 1)

Initially after the channels are enabled for operation, their priorities are assigned the same as in the fixed mode in (1). Whenever a unit of transfer is completed, the priorities of channels 0 and 1 are reversed. When transfer requests for the two channels are output simultaneously, therefore, the transfer channel is toggled between the tow channels at the end of each unit of transfer.

This mode is effective when continuous or burst transfer is set.

Channel group

Select a priority for each group listed in the Table below.

(19) Additional information on external pins and internal operation timings

Minimum effective pulse width of DREQ pin input (Only Channel 0, 1, 2, and 3)

For burst, step, block, or demand transfer, the minimum effective pulse width should be five system clock cycles (5 cycles of the external bus clock) during operation.

*: The DACKX output does not indicate the acceptance of DREQ input. The DREQ input is always accepted before transfer in the DMA enabled state. Therefore, the DREQ input need not be held until the DACKX output is asserted (except in demand transfer mode).

DREQ pin input negate timings when demand transfer request is stopped

(1) Two-cycle transfer mode

For demand transfer, be sure to set either or both of the source and destination addresses to a location(s) within an external area.

• Transfer between external areasNegate the DREQ pin input in the interval in which the external WRXO[3:0] pin output remains low during access to the source of the last DMA transfer.(Interval in which DACKX = L & WRXO[3:0] = L) If DREQ is negated after this interval, it must stay negated until the next transfer.

Mode Priority Remarks

Fixed ch0 > ch1

Rotational

ch0 > ch1Upper order in initial stateReversed to lower order after transfer in upper one

↑ ↓

ch1 > ch0

SA DA SA DA SA DA SA DACPU CPU

ch1 ch0 ch0 ch1

Ch0 transfer request


Bus operation

Transfer ch

Ch0 transfer end

Ch1 transfer end

SA DA SA DA SA DA SA DACPU CPU

ch1 ch0 ch1 ch0



Bus operation

Transfer ch

Ch0 transfer end

Ch1 transfer end


288

• Transfer between external and internal areasNegate the DREQ pin input in the interval in which the external RDXO pin output remains low during access to the source of the last DMA transfer.(Interval in which DACKX = L & RDXO = L) If DREQ is negated after this interval, it must stay negated until the next transfer.

(Examples of DREQ Pin Input Negate Timings for External-Internal Two-cycle Transfer)

• Transfer between internal and external areasNegate the DREQ pin input in the interval in which the external WRXO[3:0] pin output remains low during access to the source of the last DMA transfer.(Interval in which DACKX = L & WRXO[3:0] = L) If DREQ is negated after this interval, it must stay negated until the next transfer.

(2) Fly-by (read/write) transfer mode

For demand transfer, be sure to set the destination addresses to an address in an external area.

• Fly-by (read) transferNegate the DREQ pin input in the interval in which the external RDXO pin output remains low during access to the source of the last DMA transfer.(Interval in which DACKX = L & RDXO = L) If DREQ is negated after this interval, it must stay negated until the next transfer.

• Fly-by (write) transferNegate the DREQ pin input in the interval in which the external WRXO[3:0] pin output remains low during access to the source of the last DMA transfer.

(Interval in which DACKX = L & WRXO[3:0] = L) If DREQ is negated after this interval, it must stay negated until the next transfer.

(Examples of DREQ Pin Input Negate Timings for Fly-by (Write) Transfer)

CPU SA SADA DA CPU SA SADA DA CPU

Bus operation

Area

D[31:0]

DACKX[n]

DEOPX[n]

RDXO

WRXO[3:0]

DREQ(H level)

External Internal External Internal External Internal External Internal

Bus operation

Area

D[31:0]

DACKX[n]

DEOPX[n]

RDXO

WRXO[3:0]

DREQ(H level)

External External External External External External External External


289

DREQ pin input timing for continuous transfer on the same channel

• Burst, step, block, or demand transferContinuous transfer on the same channel by DREQ pin input cannot be guaranteed. Even if DREQ is reasserted at the earliest timing to clear the request held inside at the end of transfer, the detection of a transfer request from another channel is effective for at least one system clock cycle (one CLK output cycle). Consequently, a transfer request from another channel will be accepted to start transfer if it has a higher priority.Even when DREQ is re-asserted earlier, the assertion will be ignored because the current transfer has not yet finished. If there is no transfer request from another channel, re-asserting DREQ when the DACKX pin output is asserted, thereby restarting transfer on the same channel.

DACKX pin output timings

• The DACKX output from the DMAC indicates that transfer on an accepted transfer request is being exe-cuted.

• The DACKX output is basically synchronous with the address output at the external bus access timing. To use the DACKX output, enable it using the port.

DEOPX pin output timings

• The DEOP output from the DMAC indicates that DMA transfer on the requested channel has been finished the specified number of times.

• DEOPX is output when external area access is started for the last transfer block. If the block size is set to a value other than 1 (in block transfer mode), DEOPX is output at the last data transfer of the final block. When the DACKX pin output has been asserted, in this case, reception of the next DREQ has been started even when that transfer has been still in process (before DEOPX output).

• DEOPX is output in synchronization with RDXO and WRXO[3:0] at the external bus access timing. Note, however, that DEOPX is not output when the source or destination address is in the internal area.

DEOTX pin input timings

• For burst, step, block, or demand transfer, the minimum effective pulse width should be five system clock cycles (5 cycles of the external bus clock) during operation.

• Like DREQ, DEOTX should be input in synchronization with external access.(Use the signal decoded with DACKX output and RDXO or WRXO[3:0].)

• Use DEOTX to abort DMA transfer. If the DEOTX pin input is used, DMA transfer is forced to terminate but status register (DMACB:DSS[2:0]) outputs the exit code indicating "transfer stop request" as an error. An interrupt is generated when interrupts have been enabled.

Another transfer request during transfer

• Burst, step, or block transferUntil the DACKX signal is asserted in the DMAC, the next transfer request remains invalid. Since the external bus control unit and the DMAC are not completely synchronous in operation, however, the circuit that creates DREQ pin input from the DACKX and DEOP outputs should be initialized to enable transfer requests on DREQ input.

• Demand transfer When transfer has been executed the specified number of times, another transfer request is acceptable if

the transfer count register reload function has been enabled.

Another transfer request during block transfer

No other request is detected until the transfer of a specified block is completed. Accepted transfer requests are evaluated at a block boundary and transfer is executed on the channel of the highest priority.

Transfer between external I/O device and external memory

The DMAC does not distinguish between an external I/O device and external memory as targets of transfer by the DMAC. For the external I/O, set a fixed external address.

For fly-by transfer, set the destination address register to the external memory address. For the external I/O device, IORDX and IOWRX outputs can be used.

DMAC AC characteristics

The external pins related to the DMAC are the DREQ input pins, DACKX output pins, and DEOPX output pins. The output timings are synchronized with the external bus access timings. (See the DMAC AC standards.)


290

6.9.6 Operation flowcharts Block transfer

Load Initial address, transfer count,

and block count

Wait for activation

request

Access source address and

operate address

Access destination address

and operate address

Decrement blockcount by 1

Clear interrupt

End of DMA transfer DMA interrupt occurred

Interrupt cleared

BLK=0

DTC=0

Stop DMA

DENB=1

DENB=>0

Write back address, transfer

count, and block count

Decrement transfer count by 1

Activation request

Single access for fly-by

transfer

Block transfer

- Transfer can be activated by any activation source (selected).

- Access to all areas is possible.

- The number of blocks can be set.- A interrupt clear signal is generated when the block count is exhausted.

- A DMA interrupt is generated when the set number of transfers has been completed.

Enablereloading

Only when peripheral interrupt request

source has been selected


291

Burst transfer

Load Initial address,

transfer count, and block count

Wait for activation

request


operate address


and operate address

Decrement blockcount by 1


Interrupt cleared

BLK=0

DTC=0

Stop DMA

DENB=1

DENB=>0

Write back address, transfer

count, and block count

Decrement transfer count by 1

Clear interrupt


transfer

Burst transfer

- Transfer can be activated by any activation source (selectable).

- Access to all areas is possible.

- The block count can be set.

- A interrupt clear signal and a DMA interrupt are generated when the set number of transfers has been

completed.

Enable

reloading

Only when peripheral interrupt

request source has been selected


292

Demand transfer

Load Initial address, transfer count,

and block count


operate address


and operate address


Clear interrupt

DTC=0

Stop DMA

DENB=1

DENB=>0

Write back address, transfercount, and block count

Decrement transfer count by1

Any activationrequest?

Interrupt cleared


transfer

Wait for activationrequest

No

Demand transfer

- Only the requests (level detection) from the external pint (DREQ) are accepted. Activation by any other source is prohibited.

- Access to an external area is mandatory (access to an external area triggers the next transfer).

- The block count is fixed at 1 regardless of the setting.

- A interrupt clear signal and a DMA interrupt are generated when the set number of transfers has been completed .

Enable

reloading

Only when peripheral interrupt

request source has been selected


293

6.9.7 Data paths Data flow for two-cycle transfer

• Six examples of transfer are illustrated below. (Other combinations are omitted.)

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Read cycle

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Write cycle

Ext

ern

al b

us

inte

rface

Ext

ern

al b

us

inte

rface

External area -> external area transfer

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Read cycle

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Write cycle

Ext

ern

al b

us

inte

rface

Ext

ern

al b

us

inte

rface

External area -> internal RAM area transfer

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Read cycle

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Write cycle

Ext

ern

al b

us

inte

rface

Ext

ern

al b

us

inte

rface

External area -> built-in I/O area transfer


294

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Read cycle

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Write cycle

Internal RAM area -> external area transfer

DMAC

Bus controller

Data buffer

CP

U

I -bus

RAM

D-bus

I/O

X-bus

FR71E

Read cycle

DMAC

Bus controller

Data buffer

CP

U

I -bus

RAM

D-bus

I/O

X-bus

FR 71E

Write cycle

Internal RAM area -> built-in I/O area transfer

DMAC

Bus controller

Data buffer

CP

U

I -bus

RAM

D-bus

I/O

X-bus

FR71E

Read cycle

DMAC

Bus controller

Data buffer

CP

U

I -bus

RAM

D-bus

I/O

X-bus

FR 71E

Write cycle

Built-in I/O area -> internal RAM area transfer

Exte

rna

l in

terf

ace

Exte

rna

l in

terf

ace

Exte

rna

l in

terf

ace

Exte

rna

l in

terf

ace

Exte

rna

l in

terf

ace

Exte

rna

l in

terf

ace


295

Data flow for fly-by transfer

DMAC

Bus controller

Data buffer

CP

U

I-bus

RAM

D-bus

I/O

X-bus

FR71E

Read cycle

Fly-by transfer (I/O to memory)

IO

Write to memory using WRXO[3:0] and CSXO[n].

Read I/O using WRXO[3:0] and DACKX[n] or IORX.

mem

ory

Exte

rna

l b

us in

terf

ace

20050712 MB91403 HARDWARE MANUAL - Fujitsu · CONTROLLER MANUAL MB91403 HARDWARE MANUAL...

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