2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist...
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SDV SMU Dynamic Verilog Visualization 2 Ralph Marczynski [email protected] Peter-Michael Seidel [email protected] Southern Methodist University Dallas, TX 75275 Computer Science and Engineering
description
2 SDV SMU Dynamic Verilog Visualization HDL Design SDV 2 Schematic Visualization Text Based Values/Time Dynamic Signal Propagation Simulation StructureFunctionality
Transcript of 2 SDV SMU Dynamic Verilog Visualization Ralph Marczynski Peter-Michael Seidel Southern Methodist...
SDV SMU Dynamic Verilog Visualization2
Ralph Marczynski
Peter-Michael Seidel
Southern Methodist University
Dallas, TX 75275Computer Science and
Engineering
SDV SMU Dynamic Verilog Visualization2
HDLs
Schematic Entry
Waveform
Text
SDV SMU Dynamic Verilog Visualization2
HDL Design
SDV2
Schematic Visualization
Text BasedValues/Time
Dynamic Signal Propagation
Simulation
Structure Functionality
SDV SMU Dynamic Verilog Visualization2
•Syntax-Error Free Verilog Hardware Description
•Structural, Behavioral, or Mixed
•Physically Feasible Design
SDV 2
SDV SMU Dynamic Verilog Visualization2
Visualization Configuration
•Module Selection
•Module Placement / Geometry
•Port Orientation
•Lines Customization
SDV 2
SDV SMU Dynamic Verilog Visualization2
Veriwell 2.3 Command Line Simulator
Visualization
Signal Propagation
Text Output
Visualization and Animation Front-End
Visualization Configuration
SDV 2
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
SDV SMU Dynamic Verilog Visualization2
SIMULATION APPROACH
2 Bit Ripple Carry Adder
Independent Atomic Module Simulations with Dynamic Variable Initialization
vs.
Complete System Simulation
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
{Direct ConnectionContinuous/Procedural Assignment
Function/Task
Primitive/User Defined Primitive
Output Input Dependencies
Simulation Order
Availability of Variables at TimeOf Independent Module Simulation
Determine
Guarantees
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER EXTRACTION
2 Step Extraction Procedure
1. Local Dependency Dependency Among Instantiations in a
Defined Module
2. Global Dependency Dependency Considering The Entire System
Local Input/Output Instantiation Dependency
Top-Level
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
In-Order Traversal Generates the Simulation
Order
1. During Visit- inputs to the Instantiation are known
Local Input/Output Instantiation Dependency
Top-Level
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
Local Input/Output Instantiation Dependency
Top-Level2. Return Visit- all inputs from the module’s instantiations are known
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
Local Input/Output Instantiation Dependency
Top-Level2. Return Visit- all inputs from the module’s instantiations are known
3. Final Return - all Values within the Module are resolved.
SDV SMU Dynamic Verilog Visualization2
MODULE SIMULATION ORDER
Local Input/Output Instantiation Dependency
Top-Level 121
n
iiIS
S – Total Simulations/time unit
I – Total instantiations within module i
SDV SMU Dynamic Verilog Visualization2
VARIABLE INTIALIZATION AND EVENT EXTRACTION
Variable Initialization
Event Extraction
Dynamically Created Top Level Modules
.V
.V
Event Monitoring always@
Statements
SDV SMU Dynamic Verilog Visualization2
VARIABLE INTIALIZATION AND EVENT EXTRACTION
Variable Initialization
Event Extraction
Dynamically Created Top Level Modules
.V
.V
t-1t
value
value
initial begin
<assignments>
#1
<assignments>
end
t (event) = t (SDVV) + t (Veriwell) -1
SDV SMU Dynamic Verilog Visualization2
VARIABLE INTIALIZATION AND EVENT EXTRACTION
Variable Initialization
Event Extraction
.V
.V
t (event) = t (SDVV) + t (Veriwell) -1
Static Module Definition
Veriwell.V
.log
Events
Log File
SDV SMU Dynamic Verilog Visualization2
• OPTIMIZATIONOPTIMIZATION
• Number Of Simulations / time unit
• Data Structures• Searching/Sorting
• INTERFACE
• Graphics Enhancement• Visualization
Configuration• Text Editor• Error Detection
SDV SMU Dynamic Verilog Visualization2
LIBRARY
Extension of Verilog HDL for Animation of Dynamically Re-configurable Systems
Static Module
Definitions
DEMO
SDV SMU Dynamic Verilog Visualization2
SDV Homepage www.engr.smu.edu/~ralphm/sdvv
Ralph [email protected]
Peter-Michael [email protected]
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Marczynski’s Homepage www.engr.smu.edu/~ralphm
THANK YOU
