· 2 DIQITAL CONTINUM RECEIILER HARDWARE Dwayne R. Schiebel After using and modifying the present...
Transcript of · 2 DIQITAL CONTINUM RECEIILER HARDWARE Dwayne R. Schiebel After using and modifying the present...
NATIONAL RADIO ASTRONOMY OBSERVATORY
GREEN BANK, WEST VIRGINIA
ELECTRONICS DIVISION INTERNAL REPORT No. 242
DIGITAL CONTINUUM RECEIVER HARDWARE
DWAYNE R. SCHIEBEL
JANUARY 1984
NUMBER OF COPIES: 150
2
DIQITAL CONTINUM RECEIILER HARDWARE
Dwayne R. Schiebel
After using and modifying the present Digital Standard Receiverit was felt that instead of duplicating this receiver it wouldbe better to build a new receiver. There were several changesincorporated in the new receiver. Some of these changes arelisted below:
1. Higher resolution of a phase period, 15.5 ps insteadof 1 ms.
2. Phases 0 and 2 will have the same period and phasesand 3 will have the same period.
3. Blanking time can be set for one part in sixty-fourof a phase period, and can be set for two differenttimes -- one for signal and one for reference.
4. A new switching signal can be generated under calculatorcontrol. This signal can switch in advance of thereceiver switching signal.
5. Chart recorder channels have been reduced from eightto six; two of the channels have 12-bit resolutionand the other four have 8-bit resolution.
6. There are four calibration channels; each channel canfire on any one of four phases.
Programming
The new receiver was designed to give the programmer more flexibilityin his control of the receiver. This receiver can be controlledby the HP9826 or the HP9825 desk top computer. The programinstructions that follow are for the 9826.
In order for the 9826 to output data to the Digital ContinuumReceiver, the program will first have to set a counter to thecorrect count. This can be accomplished as follows:
Let DSR = 12Control DSR,2;2Output DSR using "#,14";X (X =Control DSR,00.Control DS11,203
- 12)
Data can be output with consecutive output commands startingwith the highest number and counting down to zero. The wordswould be output as below:
2021222324252627
2829210211212213214215
Phase 0 CH 0
2
Phase 0 CH12
Phase 0 CH 212
Phase 0 CH 3
23
3
Word
123
7
10
1112
Note 1
Data to host computer (as many words as necessary)D/A 1 (12 bits). (See note 4.)D/A 2 (12 bits). (See note 4.)D/A 3 and 4 (two channels of 8 bit D/A)
(See note 5.)D/A 5 and 6. (See Note 5.)Cal Control. (See Note 1.)#Chsr #Phases, Sig/Ref Adv. (See Note 2.)Blanking. (See Note 3.)Cycles/Integration.Period for Phase 0 and 2Period for Phase 0 and
(See Note 6.)Period for Phase 1 and 3Period for Phase I and
(See Note 6.)
There are four channels of cal; a 16-bit word is requiredto control all four channels. A one is output toturn the cal on. At power on cal state is undetermined.The following table lists the cal control.
2 0 - 2152 216- 2 21 left justified.
2 0 - 2 15 . (See Note 6.)3 2 16 - 2 21 left justified.
Note 2 20212223242526272829210211212213214215
Sig Adv LSB (one part in 64 of phase 0 and 2)
Ref Adv LSB (one part in 64 of phase 1 and 3)
Number of Phase Periods LSB
Number of Channels LSB
Note 3 2 0 Blanking (one part in 64 of Phase 0 and 2) Signal21222324252 6 Blanking (one part in 64 of Phase 1 and 3) Reference272829210211
Note 4 215 214 213 212 211 210 29 2 8 2 7 2 6 2 5 240 1 I 1 1 1 1 1 1 1 1 1 *0 0 0 0 0 0 0 0 0 0 0 0 **1 0 0 0 0 0 0 0 0 0 0 0 ***
+Full scale** 0 V*** -Full scale
Note 5
215 2 14 213 212 211 210 29 28 27 26 25 24 23 22 21 200 1 I I 1 1 1 1 0 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0_____ Dipi& D/A & - - --
4-Full scale** 0 V*** -Full scale
Note 6 The actual phase period output is the phase period
minus one. For example, if you output all zeros,you would have a period of 15.5 us.
Various conditions can be controlled within the receiver asfollows:
Control DSR,2;1Output DSR using "#,W";Z (see below)Control DSR,0;1Control DSR,2;0
Output word Z can control from one to three functions at onetime:
5
2 0 0 = Reset Fifo2 1 I 1 = Force End of Scan2 2 I 2 = No Reset, No End of Scan
3-7 = Not Used2 3= Reset Error Status2 4= Reset Time Base Counters
The host computer will be interrupted when the 9826 executesthe following:
Control DSR,20Control DSR,0;1Control DSR,2;0
Receiver data can be input by an "Enter" statement. To readall four channels, a total of 32 words must be input. The dataformat is listed below:
First Word Phase 3 MS Channel 43 LS2 MS2 LS1 MS1 LS0 MS0 LS
The other three channels are input in sequence (3,2,1) in thesame manner as channel 4. The two words for each phase hasthe following format:
Calculator Bits:
215 214 213 212 211 210 29 28 27 26
1° 0 227 - MN, ex. ON. 215 MS Data
214 - O.^ 1111., 2 0LS Data
After the data has been input, a status word is available fromthe time the last data word is read until the start of the nextintegration period. If an error condition exists, it will remainuntil the program resets the error status. If the program readsthis status word, it should normally reset the status word afterthe start of the scan. The following information is containedin the status word.
2 0 = 0 Receiver 1 Error (VCO too high or integration2 1 . 0 Receiver 2 Error counter overflow)2 2 . 0 Receiver 3 Error2 3 = 0 Receiver 4 Error24 . 0 Missed Reading a Sample2 5 = 0 Timing is External
Under normal conditions the status word should be 63, if anerror developes that status bit will be zero. Status bit 25will be zero as long as the timing is on external, and is unaffectedby reset status.
Digital Electronics
The digital electronics is composed of six different types ofwire-wrap cards. The following is a brief descriptioin of eachcard's function:
Card 1 (Slot 3)
The first page of this drawing contains the phase period counters.These counters are loaded with a count depending on which oddor even phase the receiver is on.
Page two of the drawings contain storage--for phase periods,blanking times and advance signal and reference time.
On the left hand side of page three is contained the blankingtime generator. The right hand side contains the advanced referencesignal.
Page four contains the phase counter and decoder. There aretwo signals of importance that exit this card:
Cycle Decrements Cycle/Integration Counter on Card 4.
2 Cycle Decrements Center of Integration Counter onCard 4.
rar_d_2 (Slots 4, 5, 6, & 7)
The first page of this card contains tri-state switches thatapply data to the 9826 input bus. These switches are controlledby signals originating on card 4.
The remaining pages contain the integration counters.
7
Card 3 (Slot 8)
The top of page one of this card contains output data buffersto the host computer. The bottom of the page contains two 8-bitD/A's.The second page and top of the third page contains four D/A's,two 8-bit and two 12-bit.
The four channel cal generator is at the bottom of page 3.
Card 4 (Slot 9)
This card's main function is communication with the 9826. Pageone of this card is involved in generating various control func-tions. The top of the second page contains the logic that controlsthe input data to the 9826, while the bottom controls outputdata. The very bottom of page two contains logic that enablesthe status word to be applied to the 9826 input bus.
The cycle per integration counter will be found at the top ofpage three. The logic at the bottom of this page is used tocontrol the integration counters and to skip one receiver cycleafter setup data has been output.
Page four contains the host computer interrupt logic. Thislogic generates three interrupts, center of integration, dataand end of scan. The D flip-flop in the lower right of thepage disables error checking between scans.
The hex inverters at the top of page five buffer the outputbus of the 9826. The logic at the bottom of the page placesreceiver status on the calculator status lines and interruptsthe calculator at start of scan.
Card 5 (Slot 10)
The top half of the first page of Card 5 contains optical-isolatedgates. These gates are connected to the receiver voltage controlledoscillator. At present a Teledyne Philbrick 4707 voltage tofrequency converter is being used. Blanking is applied to theVCO signal before it goes to the integrator counters (Card 2).The bottom of this page contains logic that interfaces externalswitching, calibration, and blanking to the digital logic.
The logic on page two is used to check the VCO frequency. Whenthe VCO reaches about 4.1 MHz an error will be indicated. The
D flip-flop at the bottom of the page is used to prevent theerror checking logic from getting a false counter overflow conditionat integrator reset time.
The top two-thirds of page three has logic that sets a errorcondition on a one to zero transition out of the last stageof the integrator counters. The logic at the bottom of thepage applies status information to the 9826 input bus.
Page four contains logic for front panel indication of receivererror and VCO input level.
Card 6 (Slot 11)
The first page of Card 6 contains logic to driver front panellight emitting diodes and a power supply monitor at the bottomof the page. The signal "PSTS" can be checked by the 9826 tosee if the digital logic has power applied.
The last page of this set of drawings contains drivers for cali-bration, switching, advanced switching, blanking and all fourphases.
Diagnotics
A diagnostic disk has been prepared for this system. To usethe diagnostics, insert the disk and turn on power. Instructionswill he displayed on the CRT. Test 3 is a useful test of theintegration counters. With a known frequency in on the testbox, this program computes the integrator count and displaysthe difference. A full test, reading receiver data and sendingdummy data to the host computer is available in Test 5.
Credits
Credit is given to R. Weimer and R. Fisher for their help indesigning this system. The construction of this project wasperformed by W. Vrable and J. Turner. The chassis was builtby the Green Bank Machine Shop.
MemoRi c List
Bemonic Orlqin Slot
ADV SIG 3 Advanced Switching Signal
BLO 9 Loads Blanking Time
BLTM OUT 3 Combined Internal & External Blanking
CA X 10 Blanked VCO Signal
CAL CH x 8 Calibration Signal
CHSEL 9 Input Word Channel Select
CRX 8 Analog Out to Chart Recorder
CTLX 8 Control Signals from Calculator
CYCLE 3 One Cycle of Receiver
2 CYCLE 3 Twice the Frequency of Cycle
DACXX 9 Data Strobe for DiA
DAR X 9 Calculator Input Counter Decoded
DAVAIL 9 Data is available for Calculator
DO-15 9 Buffered Calculator Output Data
D10-15 4-7, 10 Calculator Input Bus
DO-0-15 Calculator Data Out of Calculator
DOUT CX 4•7 Carry from Last Integrator Stage
DOA X 8 Data to Host Computer
EIR 9 Interrupt to Calculator
ENB ERR 9 Inhibits Error Condition Between Scan
END Host Comp. End Scan from Host Computer
HDSTB 9 Data Strobe for Host Computer
IlA I2A 3 Phase Counter before Decode
INT WA 3 Internal Blanking
10
memonic origin. slot
I/0 Calculator Input/Output from Calculator
LAST 9 Indicates Calculator Read All CounterData
LINTD 8 Latch Integrator Data
LP5 9 Data Strobe for Calibration
LP6 9 Data Strobe for #Chs, #Phases, ADV.SIG.
PCTL Calculator Peripheral Control Line
PFLG 9 Completes Data Transfer with Calculator
PHASE X 3 One of a Possible of Four Rec. Phases
PILO9 SET 9 Interrupt to Host Computer
PLX 9 Loads Phase Period in Buffer
RCTR 9 Reset Phase Period Counters
RESET Calculator Peripheral Reset
RESET INT 9 Reset Integrator Counters
RESET OFSTAT 9 Reset VCO Error Status
RFIFO 9 Reset Host Computer Fifa
SAMPLE IGNORED 9 Calculator Missed a Sample
SCAN Host Comp. Start Scan from Host Computer
STIX 9 Receiver Status to Calculator
VCO X Receiver VCO from .Receiver
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