Wafer/Panel Level Fine Pitch SubstrateInspection/Metrology ProjectPhase 2

Project Leaders: Feng Xue – IBMCharles Woychik – i3 ElectronicsCharles Reynolds - IBM

Call for Participation WebinarNovember 01, 2017

iNEMI Staff: M. Tsuriya

Link to recording (available for up to 6 months after webinar):https://inemi.webex.com/inemi/lsr.php?RCID=e6b42baae9764d30ac34c0ee3517c255

Agenda

• Introduction of Project Chairs and Facilitators

• iNEMI Project Development Process

• Project Briefing– Background & Objectives

– Project Scope• Project IS/IS Not

– Timeline

• How to Join

• Q&A

Note: All phones will be on mute until the end of the presentation

Introduction of Project Chairs & Facilitators

3

Project Leader:Feng Xue

IBM

Project Leader:Charlie Reynolds

IBM

iNEMI Staff:M. Tsuriya

Project Leader:Charles Woychik

i3 Electronics, Inc.

INPUT

SELECTION

DEFINITION

PLANNING

EXECUTION / REVIEW

CLOSURE

1

2

3

4

5

iNEMI Project Development Process - 5 Steps

“ Project”

Limited to committed Members

“ Initiative”

Open for Industry input

0

------------------- iNEMI Technical Committee (TC) Approval Required for Execution

iNEMI Project Management Policy

• Two governing documents for projects

– SOW (statement of work): sets out project scope,

background, purpose, benefits, and outlines required

resources, materials, processes, project schedule,

etc.

– Project Statement (PS): signed by participating

companies to secure commitment on resource and

time contributions.

• iNEMI Project requires iNEMI membership

– Signed membership agreement

– Commitment to follow iNEMI By-laws and IP policy

5

Project Briefing

Background

– Integrated SiP packages are becoming more popular as an electronic packaging

solution. This package type requires finer circuit patterns designs.

– Fine line and space requirements provide high density interconnects which

supports the high I/O high bandwidth memory and other component integration of

fine pitch memory, and other fine pitch devices.

7

Background

– Inspection capability in detecting defect features on fine line (<10um) and

space(<10um) on the panel size substrates/ board impacts both yield and

performance capability.

• Typical defect features are: a) Line width violations; b) Spacing violations; c) Excess copper

or missing copper; d) Short or open circuits; e) Cuts; f) Holes; g) Via bottom integrity; h) line

neck down and i) micro bump shape and bump shear strength performance.

– Inspection & measurement capability for fine circuit pattern substrate for high

bandwidth application is defined as a technical gaps in the iNEMI package

roadmap as “2/2um & 1/1um” design rules

8

Optics: Right Resolution

Seeing enough, but not too much

Selectable Magnification is needed

Light: Right Light

For different geometries and materials

Bright Field and Dark Field is needed

Free adjustable combination

Color filter to enhance contrast

Alignment: Perfect merged images

Smart algorithm to stich all taken image to one perfect picture. Any small mistake results in false alarm or missing a defect.

Detection: Multiple Algorithms

Different designs and different materials needs different algorithms. A combination of different types of algorithms gives best flexibility and highest detection.

Filter: ADC

In order to separate the defects, a smart filtering is needed which categorizes the defects into predefined groups automatically.

Dark Field Illumination

Bright Field Illumination

Wafer

Multiple Resolution

Camera

Background: Key Element for AOI

Type of Analyses:

Inspection:

Detection of any variation based on given requirement.

Comparing against Reference (CAD or Golden Ref. Image)

Comparing against Fixed Values (Absolute Reflection Values)

Comparing against Neighborhood

Metrology:

Measuring of defined Objects

Absolute Measuring (Measuring the dimension of a defined Object)

Overlay Measuring (Position of defined Objects to each other or Ref. Point)

Post Processing:

Analyzing data based on given Models (coplanarity for Bumps)

Process Control based on feedback of variations over Lots/Time

Generating Maps and Reports

Background: Key Functions for AOI

Background

– iNEMI started Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology

Project in 2016. Phase One, which included an industry-wide survey to assess the

measurement and inspection capability and readiness for fine circuit pattern

substrates, was completed in Feb 2017 with the following key findings and

recommendations• The limited manufacturing experience with fine pitch technology results in an environment of uncertainty

• The capabilities of today’s toolsets allow for development investigation and evaluations but are not

designed for manufacturing volumes

• The development timeline indicates fine feature inspection and measurement must be available within the

next 3-5 years.

– Phase 1 also delivered an industry paper “Inspection/Metrology Benchmarking on

Fine Pitch Design Substrate for Advanced Packages”, Feng Xue, et al. , in 2017

International Conference on Electronics Packaging (ICEP2017, April 19-22, 2017,

page 47-50)

http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7934495

– Team decided to move to next phase to conduct an inspection capability study on

fine pitch patterns which are less than 10um lines and spaces with various defect

patterns based on the key recommendations from Phase One.

11

The Purpose of Project

• This project is a continuation from Phase One. The purpose of this project is to further characterize and quantify industry capability by conducting an inspection capability study and analysis using test vehicles (TV) with fine line space features and defect patterns.

– Design and fabrication of glass test vehicle has been executed as the pre-work for Phase Two. Silicon test vehicle fabrication is an option for the further inspection capability limitation study.

– A defect pattern design with 7 different line widths is fabricated in wafer form to create the Test Vehicle.

– Defect patterns includes a) Line width violations; b) Spacing violations; c) Excess copper or missing copper; d) Short or open circuits; e) Cuts and other features.

– Line widths are designed with 10um, 8um, 6um, 4um, 3um, 2um, and 1um features. These lines width might be changed due to fabrication techniques.

Scope of Work

• The goal of phase 2 is to conduct the inspection capability limitation

study by correlating the inspection results to the Test Vehicle

design. Glass and silicon test vehicle (TV) are used for phase 2, and

plan to use the organic TV in phase 3 (the laminate TV design will be

determined based on results from the glass and silicon TV study).

– Design the defect patterns which are used for inspection capability study.

– Glass TV is fabricated on a round, 4-inch wafer size). This is conducted

as pre-work. (details from page 15-17)

– Distribute glass TV’s to Metrology companies and users for evaluation.

– Create a Silicon TV in parallel to Glass TV inspection and evaluation

(optional)

– Collect data and analyze the inspection data.

– Propose organic TV design (based on Glass TV and Silicon TV results) for

phase 3

Defect Patterns 1

Extraneous Metal; Shorts; Spacing, Line Width Violations

14

Defects Pattern 2

Extraneous Metal; Shorts; Spacing, Line Width Violations

15

Remark:

Radiused turns not drawn!

Remark:

Length ‘n’ based on available area and

design requirements

Defects Pattern 3

Notches, Nicks, Mousebites, Holes, Voids

16

Milestone

Task 1 - Verify the dimensions of glass TV by SEM or other methods

Task 2 - Inspection & Measurement of Glass Test Vehicles

Task 3 - Review design rules for defects patterns for Silicon TV fabrication

Task 4 - Silicon TV fabrication – optional

Task 5 - Verify the dimensions of Silicon TV by SEM or other methods

Task 6 - Inspection & Measurement of Silicon Test Vehicles

Task 7 - Summarize and analyze the inspection data for both Glass TV and

Silicon

Task 8 - Propose recommendation and define plan for phase 3

IS / IS NOT Analysis

Outcome of Project

• Inspection results are shared among the project

members, which include the metrology options, technical

gaps and technical plans on the metrology and

inspection systems.

• Comparison and assessment of the inspection results,

and recommendations are provided for the metrology

option in selection.

• The analysis results will be used as key inputs for Phase

Three Test Vehicle Design

• A summary report is available to all iNEMI members.

How to Join

Sign-Up Due on Nov 30, 2017

• iNEMI membership is required to join the project

• Download SOW and PS from iNEMI web:

http://community.inemi.org/wafer-panel-level-fine-

pi?utm_source=hs_email&utm_medium=email&utm_content=57448333&_h

senc=p2ANqtz-

9Zf2M9XIhqPIjw5dgwpWf2L4kta2zv_xOEd5Rh0iRt3Q4YHW7DIF1Wc9tZLEp

89HyIYVLFG4JNhm8tRq2VlmVK4Gz66Q&_hsmi=57457022

• Process to participate this project:

– Sign the PS

– Send scanned PS to infohelp@inemi.org

– iNEMI VP of Operations will approve your participation and send you

back the completed PS with acceptance

• Join iNEMI membership, or questions, contact M. Tsuriya

(m.tsuriya@inemi.org)

21

Path to Kick-off Meeting

• Call for Participation Webinar: Nov.1, 2017

• Sign-up Due: by Nov.30, 2017

• Kick-off Meeting:

Dec.6, 2017 from 9:00PM Japan time

Note:

Meeting time might be changed due to the participants’ preference and

availability

22

Questions?

Project web page:

http://www.inemi.org/fine_pitch_circuit

www.inemi.org

Masahiro Tsuriya

m.tsuriya@inemi.org

Backup