1st International Conference on Nano-electronics, Circuits & Communication Systems ... · PDF...

IETE Ranchi ARTTC BSNL Ranchi ISVE Ranchi

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1st International Conference on Nano-electronics, Circuits & Communication Systems (NCCS-2015)

9-10th May 2015 at ARTTC BSNL Ranchi-835217 Jharkhand India, [email protected]


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List of Messages of Eminent Persons

Message of President IETE New Delhi Smt. Smiriti Dagur, New Delhi

Message of Vice President Prof Laxminarayana Karre

Message of Vice Chancellor, RU Dr. R.K. Pandey,

Message of TPPC IETE Dr. A. K. Saini

Message of Guest of Honor Dr. Mrityunjay Chakraborty IIT Kharagpur

Message of Keynote Speaker Dr. Subir Kumar Sarkar, Jadavpur University

Message of Invited speakers / Keynote speakers Dr. P.K. Barhai, Former VC BIT Mesra

Message of Expert Invited Lecture Dr. J.S. Roy, KIIT Bhubneshwar

Message of Expert Invited Lecture Dr. J.K. Mandal, Kalyani University

Message of Expert Invited Lecture Dr. S.P. Tiwari, IIT Jodhpur

Message of Expert Invited Lecture Dr. Manish Mishra, DDU University Gorakhpur

Message of Chairman NCCS 2015 Sh. Sanjay Kumar Jha, Executive Engineer, Jharkhand Govt.

Message of Co-chairman NCCS-2015 Sh Ajay Kumar, AGM BSNL Ranchi

Message of General Chair NCCS 2015 Dr. Vijay Nath, BIT Mesra, Ranchi

Message of Organizing Secretary NCCS 2015 Dr. Anand Kr. Thakur SSMC, RU

Message of expert Invited Lecture Dr. K. Solomon Raju, CEERI Pilani

Message of expert Invited Lecture Dr. K. Khatua, NIT Rourkela

List of Session Chair Persons

S.N. 1 Dr. Mrityunjay Chakraborty IIT Kharagpur 2 Dr. Subir Kumar Sarkar Jadavpur University 3 Dr. P.K. Barahi Former VC BIT Mesra 4 Dr. J.K. Mandal Kalyani University 5 Dr. J.S. Roy KIIT Bhubaneswar 6 Dr. S.P. Tiwari IIT Jodhpur 7 Dr. K. Khatua NIT Rourkela 8 Dr. Mahesh Chandra BIT Mesra 9 Dr. P.R. Thakura BIT Mesra 10 Dr. R.K. Lal BIT Mesra 11 Dr. S.S.Tripathi BIT Mesra 12 Dr. K.K. Senapati BIT Mesra 13 Dr. V.K. Jha BIT Mesra 14 Dr. Vijay Nath BIT Mesra 15 Dr. Anand K. Thakur SSMC RU 16 Dr. I. Mukherjee BIT Mesra 17 Dr. A. Islam BIT Mesra 18 Dr. Dileep Kr. Upadhyay BIT Mesra 19 Dr. K. Solomon Raju CEERI Pilani 20 Dr. Manish Mishra DDU GU 21 Dr. Gaurav Trivedi IIT Guwahati 22 Dr. P. Kumar IIT Patna 23 Prof. Richa Pandey BIT Mesra 24 Dr. D.K. Malik BIT Mesra 25 Dr. Vijay Laxmi BIT Mesra 26 Dr. A.K. Tiwari BIT Mesra 27 Dr. N. Chattoraj BIT Mesra


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28 Dr. Sukalayan Chakraborty BIT Mesra 29 Dr. Abhishek Rawat IIT RAM Amhedabad 30 Dr. D. Devraj KLU Tamilnadu 31 Dr. D. Acharya PIET Rourkela 32 Dr. S.S. Solanki BIT Mesra 33 Dr. Sanjeet Kumar BIT Mesra 34 Sh. Vijay Bhusan Pandey ARTTC, BSNL Ranchi 35 Sh. Ajay Kumar ARTTC, BSNL Ranchi 36 Dr. Rishi Sharma BIT Mesra 37 Dr. R. K. Sinha BIT Mesra 38 Dr. Pawan Kumar CIT Ranchi 39 Dr. V.S. Rathore BIT Mesra 40 Dr. Sanjay Kumar BIT Mesra 41. Dr. Sukalyan Chakraborty BIT Mesra 42. Dr. Nutan Lata Nath BIT Mesra 43. Dr. A. K. Tiwari BIT Mesra 44 Dr. Gaurav Trivedi IIT Guwahati


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SN. Paper ID Corresponding Authors

PAPER TITLE Page Number

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NCCS103 T. Sasikala

CROSS LAYERED ADAPTIVE RATE OPTIMIZED ERROR CONTROL CODING FOR WSN

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NCCS104 Jai Kishan

A COMPACT U-SHAPES PRINTED UWB ANTENNA WITH TRIPLE BAND REJECTION CHARACTERISTICS

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NCCS112 Dr.Nukala S. Rao

ANTENNA SIGNATURE ALTERATION USING METAMATERIAL FOR MOBILE PHONE APPLICATIONS

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NCCS117 Abhishek Nag

AN AUTONOMOUS POWER AND CLOCK GATING TECHNIQUE IN SRAM BASED FPGA

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NCCS119 Ranjith C.

A HARDWARE IMPLEMENTATION OF EVOLVABLE EMBEDDED SYSTEM FOR COMBINATIONAL LOGIC CIRCUITS USING VIRTEX 6 FPGA

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NCCS120 Manas Ray

EVALUATION OF WAVELET BASED SPEECH CODEC FOR VOIP APPLICATIONS

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7 NCCS121 L. Rajesh

USER DEMAND WIRELESS NETWORK SELECTION USING GAME THEORY

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NCCS122 P. Ramesh

DETECTION OF MALICIOUS NODES USING ENHANCED INTEGRATED DYNAMIC TRUST RECOMMENDER IN MANET

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9 NCCS123 Trupa Sarkar

LEAKAGE REDUCTION BY TEST PATTERN REORDERING

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NCCS125 Ankur Saxena

REVIEW ON BAND-NOTCHING TECHNIQUES FOR ULTRA WIDEBAND ANTENNA

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11 NCCS126 S. Sridevi

REAL TIME SIMULATION DESIGN FOR CONTINUOUS PROCESS INDUSTRIES

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NCCS128 Ranjan Mishra

ANTENNA PATH LOSS PROPAGATION MODEL IN THE DEHRADUN VALLEY AT 1800 MHZ IN L- BAND

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NCCS130 Ram Kumar

LINEARITY ANALYSIS AND OPTIMIZATION OF 5.5 GHZ INDUCTIVE SOURCE DEGENERATION LOW NOISE AMPLIFIER

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NCCS131 Mughelan R.

PERFORMANCE ENHANCEMENT OF LTE HETNET USING EVM BASED CONSTELLATION COMBINER (ECC) IN WARP

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NCCS132 Pallavi Dutta

PERFORMANCE ANALYSIS OF 3-PHASE INDUCTION MOTOR: USING SIMULINK AND TMS320C6713

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16 NCCS135 R. Benschwartz

NOVEL SYSTEMATIC OPTIMIZED DESIGN APPROACH FOR PROCESS VARIATION

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SENSITIVE OTA IN LOW POWER MSIC DESIGN

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NCCS139 Nabajyoti Mazumdar

A DISTRIBUTED FAULT-TOLERANT MULTIOBJECTIVE CLUSTERING ALGORITHM FOR WIRELESS SENSOR NETWORKS

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NCCS140 Biswajit Ghosh

COMPARING ENERGY EFFICIENCY OF DF RELAY ASSISTED COOPERATIVE AND NON-COOPERATIVE SHORT RANGE WIRELESS SYSTEMS

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NCCS141 D.C. Diana

MODIFIED PSO BASED EQUALIZERS FOR CHANNEL EQUALIZATION

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NCCS143 Sudhanshu Kumar

INVESTIGATION OF ELECTROSTATIC ACTUATION SCHEME FOR LOW VOLTAGE MEMS SWITCH

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NCCS145 Katara Chauhan R.

INTEGRATION AND MIGRATION OF HETEROGENEOUS BIOLOGICAL DATA RESOURCES TO CLOUDS

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NCCS146 Abahan Sarkar

ON ONLINE COUNTING OF CIGARETTE IN PACKETS - AN IMAGE PROCESSING APPROACH

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NCCS149 Dr. Vijay Kumar Jha

FUZZY MIN MAX NEURAL NETWORK BASED INTRUSION DETECTION SYSTEM

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NCCS153 S.P. Thaiyalnayaki

IDENTIFICATION AND ANALYSIS OF ESSENTIAL TREMOR USING RS-FMRI DATA BY ICA

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NCCS154 Abhishek Gandhar

EFFECT OF STATIC SYNCHRONOUS SERIES COMPENSATOR ON POWER BALANCING IN WIND FARMS

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NCCS157 K. Mariammal

DESIGN AND ANALYSIS OF FAST CONVOLUTION BASED MULTIRATE FILTER BANKS

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27 NCCS159 Ravishankar hola

CHARATERISATION OF TFT SENSORS FOR CHEMICAL SENSING APPLICATIONS

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NCCS160 Amiya Sagar Das

IMPLEMENTATION OF BREADTH FIRST SEARCH FOR STORAGE OPTIMIZATION IN RANDOM STORAGE ASSIGNMENT OF AUTOMATED STORAGE AND RETRIEVAL SYSTEMS

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NCCS162 Dr. Abhishek Rawat

DESIGN ANALYSIS OF DUAL BAND OCTAGONAL SHAPE MICROSTRIP PATCH ANTENNA AT 5.70 AND 8.00 GHZ

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NCCS165 Anurag Kumar Paliwal

DESIGN OF A HIGH PERFORMANCE CMOS CHARGE PUMP FOR PHASE-LOCKED LOOP SYNTHESIZERS

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31 NCCS167 Shashi Bhushan MULTIBAND PLANAR ANTENNA WITH 55


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Kumar FRACTAL GEOMETRY

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NCCS171 Neeti Singh

EFFICIENT ALGORITHMS FOR REMOVAL OF HIGH DENSITY RANDOM VALUE IMPULSE NOISES IN IMAGES

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NCCS173 Ram Kumar

OPTIMIZATION OF 5.5 GHZ INDUCTIVE SOURCE DEGENERATION LNA USING NSGA II

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NCCS175 Mohini Yadav

RELIABILITY AND ENERGY BENEFIT ANALYSIS OF DISTRIBUTION SYSTEM INCORPORATING WIND TURBINE GENERATOR

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35 NCCS176 Kovendan

PRESENT CONTEXT OF SMART GRIDS IN INDIA: A SURVEY

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NCCS177 Raju Kumar Allan

AN EFFFICIENT SPECTRUM SENSING USING COMPRESSIVE MEASUREMENT IN COGNITIVE RADIO

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NCCS178 Rajendra Prasad M

SYSTEM LEVEL PERFORMANCE ANALYSIS OF EMBEDDED SYSTEMS FOR GSM APPLICATIONS

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NCCS179 Babulal Sahu

A COMPACT MONOPOLE SLOT ANTENNA FOR X- BAND SATELLITE COMMUNICATION

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NCCS180 V. Hari

ANALYSIS OF SUB-5NM NOVEL FINFET DEVICE OVER 180NM BULK CMOS DEVICE

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40 NCCS181 Adesh Kumar

IC PACKAGING: 3D IC TECHNOLOGY & METHODS

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NCCS182 Jitendra Yadav

MODELING AND SIMULATION OF THE DYNAMIC RESPONSE OF A GENERIC MECHANICAL LINKAGE FOR CONTROL APPLICATION UNDER THE CONSIDERATION OF THE NONLINEARITIES IMPOSED BY FRICTION

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42 NCCS183 Dr. J. Durga Devi

DESIGN OF A THIRD ORDER SELF BIASED ADAPTIVE BANDWIDTH PLL

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43 NCCS186 Megha Agarwal

DESIGN OF ULTRA LOW POWER CLASS E POWER AMPLIFIER

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NCCS187 Akshat Chitransh

ANALYSIS OF A SELF-COMPENSATING, LOW-NOISE, LOW-POWER PLL CIRCUIT @45NM TECHNOLOGY NODE.

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NCCS191 Nancy Mishra

DESIGN OF 3-BIT LOW POWER FLASH ANALOG TO DIGITAL CONVERTER (ADC) IN VLSI

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46 NCCS192 Avi Jain

A 0.75 V UWB LNA FOR 3.1–10.6-GHZ WIRELESS APPLICATIONS

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47 NCCS193 V.H.P.S.S. Arun

DESIGN AND IMPLEMENTATION OF A REACTION TIMER USING CMOS LOGIC

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NCCS194 Sharad Kumar

DESIGN AND ANALYSIS OF CURRENT STARVED VOLTAGE CONTROLLED OSCILLATOR @ 45NM CMOS TECHNOLOGY

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NCCS195 Kumar Amit

EVALUATING THE PERFORMANCE OF DYE SENSITIZED SOLAR CELL WITH THE VARIOUS KEY COMPONENTS LIKE ELECTRODES, DYES & ELECTROLYTES

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50 NCCS197 Namrata Yadav

DESIGN OF LOW POWER OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

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NCCS198 Krishan Kumar Singh

DESIGN OF COMPARATOR IN SIGMA DELTA ADC USING 45NM CMOS TECHNOLOGY

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52 NCCS199 Sarika Tyagi

A 21NW CMOS OPERATIONAL AMPLIFIER FOR BIOMEDICAL APPLICATION

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53 NCCS200

Mohd. Javed Khan

A 1.45 MW CMOS 4 BIT MULTIPLIER CIRCUIT

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NCCS201 Bhabani Shankar

Das

PREDICTION DEPTH AVARAGE VELOCITY AND BOUNDARY SHEAR STRESS DISTRIBUTION IN A SINGLE STAGE CHANNEL BY LATERAL DISTRIBUTION METHOD

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NCCS202 Kamalini Devi

FLOW COMPUTATION IN SYMMETRIC AND ASYMMETRIC COMPOUND CHANNELS USING CONVEYANCE ESTIMATION SYSTEM

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NCCS203 Vishal Kumar

EFFECT OF TEMPERATURE ON DARK CURRENT IN QWIP FOR UNMANNED

AERIAL VEHICLES

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NCCS204

Md Maqubool Hosain

DESIGN OF CIRCULAR DISC MONOPOLE ANTENNA FOR UWB APPLICATION

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MESSAGE

It gives me a great pleasure learn that an International Conference on Nano-electronics,

Circuits & Communication Systems (NCCS-2015) on 11-12th

April-2015 at ARTTC,

Ranchi. The professionals will get exposure to the developments in the frontier

technologies which decide the shape things to come in the future. The technology is

changing so fast in the fields of Electronics and Communications that a professional can

keep pace only by attending such seminars. I am very sure that, you are doing a great

service by organizing this conference at Ranchi.

On behalf of IETE I wish to convey best wishes for the grand success of the International

Seminar.

Prof Laxminarayana Karre

Vice President, IETE


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KIIT University

Declared U/S 3 of UGC Act, 1956

School of Electronics Engineering

Bhubaneswar 751024 Odisha www.kiit.ac.in

Date: 20-04-2015 I am glad to know that IETE and ISVE Ranchi centre are jointly organizing International Conference on

Nano-electronics, Circuits & Communication Systems which is going to be held in Advanced Regional

Telecom Training Center, BSNL, Ranchi, during May 9 & 10, 2015. I learned that the conference will be

devoted to the recent research issues on the above subjects through paper presentations and invited talks

and therefore it will be a good forum of discussion for the participants.

I sincerely appreciate the effort of IETE and ISVE Ranchi centre for organizing this conference and I am

honoured to be a part of this event.

I wish a great success of this technical conference.

Dr Jibendu Sekhar Roy

Professor, School of Electronics Engineering

KIIT University, Bhubaneswar


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Kalyani-741235, Nadia

West Bengal, India

Phone: (033) 25809617 (O)

Mobile: +91- 9434352214

e-mail: [email protected]

Univers i ty o f Kalyani FACULTY OF ENGINEERING, TECHNOLOGY & MANAGEMENT

1) Prof. J. K. Mandal 2) DEPT. OF CSE, FACULTY OF ENGINEERING,

TECHNOLOGY & MANAGEMENT UNIVERSITY OF KALYANI

B.

MESSAGE

I am glad to learn that IETE & ISVE Ranchi Centre is organizing two days First

International Conference on Nano-electronics, Circuits & Communications Systems

(NCCS 2015) on 9th

and 10th

May 2015 at ARTTC, BSNL, near Jumar River, Hazaribag

Road, Ranchi

I am also happy to know that the accepted papers will be published by a reputed publisher

with ISBN number and extended version of selected papers will also be published in

journals of good reputation and indexing.

In my opinion this is a very good platform to share the current trend of technology among

researchers, scholars and industry people.

My best wishes for NCCS 2015.

Prof.(DR.) J. K. Mandal

Professor & Former Dean, FETM

Kalyani University


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Sanjay Kumar Jha Chairman, IETE

Message I feel pleasure that The Institution of Electronics and Telecommunication

Engineers (IETE), Ranchi centre is organizing 1st International Conference on “Nano-

electronics, Circuits & Communication Systems” in an association with Indian Society

for VLSI Education (ISVE), Ranchi on 9-10th May, 2015 at ARTTC, BSNL, Ranchi.

IETE, Ranchi is continuously organizing Zonal, National seminars from last four

years to provide a platform to Researchers, Engineers and Educationist to exchange

their works with each other. This year we are organizing International level seminar to

globalize the platform. As we all know that nano technology is science of future and

huge research works are under progress throughout the world.

I wish great success to this event and also congratulate our organizing team for

their effort. I also welcome the Delegates and Speakers.


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Ajay Kumar, AGM (admin.), BSNL, Ranchi.

CO-Chairman NCCS-2015

Hony. Treasurer, IETE, Ranchi Centre

Message

IETE, Ranchi and ISVE, Ranchi jointly planned to organize 1st International

Conference on “Nano-electronics, Circuits & Communication Systems” during the first

week of January, 2015. Our organizing team continuously worked on the every aspects

of the successful conduction of this event. The response of the delegates from the

different part of the India and their active participation certainly boosted our plan. I

thank to all delegates and speakers who are coming to participate in this mega event.

We tried to choose the topic which is one of the most emerging branches of the

science and I am sure that a good outcome will come during this seminar.

I once again welcome all participants and giving good wishes to our organizing

team for success.

Ajay Kumar


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Message

It is eminence pleasure for us that Institute of Electronics and Telecommunication Engineers

(IETE) & Indian Society for VLSI Education (ISVE) Ranchi centre gives me the opportunity for

General Chair in two days Ist International conference on Nano-electronics Circuits and

Communication System (NCCS 2015) organised at Advanced Regional Telecom Training

Centre BSNL near Jumar River Hazaribag Road Ranchi on 9th

-10th

May 2015. Really this

conference will provide the international forum to exchange research idea in the area of VLSI

Design, Nanoelectronics, Circuits, Communication System, Analog and Digital Signal

Processing, Embedded System Design, Green Energy, Smart Power Plants, Aerospace

Application, Biomedical Instrumentation and Engineering etc. I hope this conference will give

the platform for the researchers to exchange their ideas and publish his article in highly reputed

publications. The main focus of this conference is to enhance the feasibility of electronic system

design and manufacturing in the country. As everybody know my Country is good consumers of

electronics goods, but production is approx 5 to 10% of total consumptions. This conference will

provide the guidance by expert researchers how to develop electronic goods in enough amounts

in the country. On behalf of the general chair I welcome to all the participants expert speakers

session chairs international and national advisory board members, technical program committee

members, expert reviewers technical and nontechnical person media person intellectual person of

India and abroad for his constant support and inspiration for conducting this conference

successfully. These societies are continuously support to government activity to trend the

engineer’s, researchers, professors by organising conference, symposium, workshop, short term

courses, summer and winter schools in VLSI design for electronic system design and

manufacturing. Once again I heartily welcome to all associate members that directly and

indirectly associated with this conference for grand success the program from district, state, and

country and abroad.

Dr. Vijay Nath


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NCCS103

CROSS LAYERED ADAPTIVE RATE OPTIMIZED ERROR CONTROL CODING FOR WSN

T.Sasikala1, M.A.Bhagyaveni2, V.Jawahar Senthil Kumar3

Department of Electronics and Communication Engineering, College of Engineering Guindy, Anna University,Chennai-600025

[email protected], [email protected],[email protected].

Abstract – One of major issues in WSN is the research for reducing the energy consumption and ensuring the reliability of data. Error control is significant in WSN because of their severe energy constraints and the low power communication requirements. In this paper we propose the cross layered adaptive rate optimized low-density parity check codes (CLARL) for WSN. The proposed algorithm uses the physical layer parameters such as coherence time of the channel, BER and SNR also the routing layer parameter such as demanded data rate to determine the rate of the LDPC coder. The algorithm adaptively changes the rates as ¾ ,½, and 1/3 . The performance of the algorithm is evaluated using parameters such as time taken for encoding the message bits and decoding time per iteration for various values of code word length is analysed. Also, the energy model is developed to compute the amount of energy required for transmitting and receiving n-bits using µAMPS-1 mote and it is found to be 0.687mJ and 0.585mJ respectively for n=1000. The complexity of encoding and decoding is found to be O (n) and O (N*E/Rn) respectively.

Key words: Cross layer, Wireless sensor network, Error control code, Energy efficiency, Code rate

mailto:[email protected]


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NCCS104

DESIGN OF A COMPACT TRIPLE BAND PLANAR ANTENNA FOR DCS WLAN AND X-BAND APPLICATIONS

Jai Kishan1, Tejbir Singh2, DV Avasthi3

1,2,3 Subharti Institute of Technology and Engineering, SVSU, Meerut, 250005, India

[email protected]

Abstract— This research proposes a compact triple band planar antenna for a digital communication system (DCS)/2.4-GHz WLAN and X-Band frequencies application. The two resonant modes of the proposed structure are associated with the two monopole radii in the antenna configuration. The circle with larger radius contributes to lower resonant frequencies and the one with smaller radius to higher resonant frequencies. Experimental results indicate that the antenna proposed in this work can provide excellent performance for DCS/2.4-GHz WLAN and X-Band frequencies, resonating at wide frequency band, providing moderate gain, and near Omni-directional radiation coverage. The outcome of experimental results along with design criteria are presented in this work. Index Terms— Digital communication system (DCS), X-band for Radar system, monopole antenna, 2.4-GHz WLAN.



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NCCS112

ANTENNA SIGNATURE ALTERATION USING METAMATERIAL FOR MOBILE PHONE APPLICATIONS

N. Srinivasa Rao1, L. Pratap Reddy2

1 Department of Electronics & Communication Engineering, Matrusri Engineering College, Hyderabad, India.

2 Department of Electronics & Communication Engineering,

Jawaharlal Nehru Technological University, Hyderabad, India.

[email protected] 2 [email protected]

Abstract: Electromagnetic radiation from mobile handset is identified as one of the side effects on brain and nervous system. Monopolar antennas are mounted on mod bile set which causes severe radiation hazard on soft as well as hard tissue of human body. To reduce the radiation hazard on brain and other nervous system it is proposed that a metamaterial based antenna for some improvement in performance of directive gain, Specific Absorption Rate(SAR), VSWR, and return loss including depth of penetration. This paper mainly deals with compact circular patch antenna on a metamaterial substrate for mobile phone applications. To improve the performance of an antenna in terms of directive gain, return loss and size including cost minimization it is proposed that a metamaterial antenna with circular patch on FR-4 substrate. A patch antenna has been designed to operate in 1GHz-3GHz. frequency. The aim of this paper is to design and fabricate metamaterial antenna and study the effect of antenna dimension length, width and substrate parameters Dielectric constant and other electrical parameters. Desired circular patch antenna is initially simulated using HFSS simulator and patch antenna is realized as per proposed design. Keywords— Circular patch antenna, Split ring resonator, SAR, VSWR




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NCCS117

AN AUTONOMOUS POWER AND CLOCK GATING TECHNIQUE IN SRAM BASED FPGA

Abhishek Nag, Sambhu Nath Pradhan

Department of Electronics and Communication Engineering, National Institute of Technology Agartala, India,

[email protected]

Abstract: In this work an autonomous power and clock gating technique for Finite State Machines (FSM) is being implemented in a programmable TILE. A TILE is the basic building block of a Field Programmable Gate Array (FPGA) device, which can be repeated over and again to form the entire FPGA structure. We have designed and simulated a transistor level SRAM based TILE architecture in Cadence Virtuoso spectrum at 45 nm technology. The transistor level design of the TILE provides the scope for in depth and elaborate analysis of the architecture. We have implemented a basic FSM circuit in the TILE and then introduced a dynamic power and clock gating technique. The logic of gating is based on the knowledge of self-loops in an FSM and works at a fine level of granularity. Our approach has successfully resulted in reducing approximately 19% of the total power dissipation of the TILE architecture with a minimal increase in delay. Keywords: Power Gating; Clock gating; Finite State Machine; SRAM; FPGA.



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st International Conference on Nano-electronics, Circuits & Communication Systems (NCCS-2015)


NCCS119

A HARDWARE IMPLEMENTATION OF EVOLVABLE EMBEDDED SYSTEM FOR COMBINATIONAL LOGIC CIRCUITS USING VIRTEX 6

FPGA

Ranjith C1 and S. P. Joy Vasantha Rani2 Electronics Engineering Department,

M.I.T Campus, Anna University, Chennai – 600 044 Tamil Nadu, INDIA

[email protected], [email protected]

Abstract - The main aim of this paper was to develop an architecture model using the concept of evolvable embedded system for automating the design of VLSI circuits. The architecture was modelled for combinational circuits with 8 inputs and outputs. An evolvable hardware system is an integration of evolutionary algorithm with a reconfigurable chip. A Virtual Reconfigurable Architecture IP core is modelled in the FPGA, functions as a substrate for the evolution of combinational circuits. A genetic algorithm program is carried out within the soft core Micro Blaze microprocessor to speed up the evaluation process. The soft processor core along with the reconfigurable architecture are embedded into a single FPGA chip. An experimental model for a 2 bit adder and multiplier was validated to demonstrate the evolution of combinational circuits by evolvable embedded system hardware. This experimental setup is carried out on Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA using the Xilinx Platform Studio 14.6 tools. Keywords - evolvable hardware; genetic algorithm; FPGA; virtual reconfigurable array; evolvable embedded systems; MicroBlaze processor


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NCCS120

EVALUATION OF WAVELET BASED SPEECH CODEC FOR VOIP APPLICATIONS

Manas Ray , Mahesh Chandra

Department of Electronics and Communication Engineering Birla Institute of Technology Mesra

Ranchi – 835215, India

Abstract—This paper evaluates the performance of various wavelets for compression of speech signal to be used for VoIP communication. The prime focus in using wavelet based speech coder is the selection of a best possible wavelet function for signal processing. Haar, different orders of Daubechies wavelets, Coiflets and Discrete Mayer wavelets have been studied in this paper for speech coding. Speech codecs based on these wavelets are simulated and the performance of speech compression has been compared based on Compression Ratio (CR), Retained Signal Energy (RSE), Signal to Noise Ratio (SNR) and Normalized Root Mean Square Error (NRMSE).

Keywords— VoIP, Haar wavelet, Daubechies wavelet, Coiflets, Discrete Meyer wavelet, CR, RSE, SNR, NRMSE


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NCCS121

USER DEMAND WIRELESS NETWORK SELECTION USING GAME THEORY

Mr. L. Rajesh1, K. Boopathy Bagan2, Ramesh B3

Department of Electronics Engineering Madras Institute of Technology

Chromepet, Chennai [email protected], [email protected]

Abstract—The next generation wireless environment depends on the multiple networks supported by different operators for various applications. In this heterogeneous environment users are able to connect to various Radio Access Networks and have seamless connectivity. Network selection play a vital role for users to connect to the best access network available because each access network differ in bandwidth, Cost, energy usage, coverage area. In this paper an access network selection method to select the best suitable network is proposed. Game theory approaches are used for the strategy between the user and network to form cooperation so that users can get better QoS at reasonable cost and each access network can increase their revenue.

Keywords—Cooperative game theory, Network Selection, Heterogeneous wireless networks



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NCCS122

DETECTION OF MALICIOUS NODES USING ENHANCED

INTEGRATED DYNAMIC TRUST RECOMMENDER IN MANET

P.Ramesh1, Dr, H. Abdul Rauf2, S.Malarvizhi3

1,3Anna University, Chennai 2Dhaanish Ahmed info&Tech, Chennai

[email protected], [email protected] , [email protected]

Abstract— Trust and reputation models are utilized in the security

mechanisms of MANET to deal with selfish and misbehaving nodes and ensure

safe delivery of packets from source to destination. The calculation of trust

values and its propagation between the nodes form the rubric of these trust

models. But its effectiveness is often degraded by the propagation of fake trust

values via dishonest recommendations particularly in environments like MANET

due to the lack of centralized administration and mobility of nodes. However

dealing with dishonest recommendation attacks is a highly challenging task. We

propose an enhanced integrated dynamic trust recommender that filters out

dishonest recommendations by clustering, filtering and selecting the

recommended trust values based on certain criteria. This makes the trust

reputation model more robust and accurate in the dynamically changing MANET

environment.

Index Terms—Trust and reputation model; Mobile Ad hoc network; Recommendation management.





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NCCS123

LEAKAGE REDUCTION BY TEST PATTERN REORDERING

Shrabanti Chakraborty, Trupa Sarkar, Sambhu Nath Pradhan

ECE Department National Institute of Technology, Agartala

Agartala, India

[email protected]

Abstract— Power dissipation has become a crucial parameter during testing process, as the design can consume much more power during test than during normal mode of operation. In this paper, importance has been given on leakage power minimization during testing because as scaling increases the leakage power has a major influence over the dynamic power. It is to be considered here that leakage power depends not only on the current input pattern, but also on the previous input pattern applied to the circuit under test (CUT).This fact has been asserted by using four ISCAS’85 benchmark circuits considering different test application time. Test patterns for benchmark circuits are generated by ATALANTA. Genetic Algorithm has been used to reorder the test patterns so that transition density between test vectors is minimum. Using this technique, result shows that the overall improvement in leakage power is maximum in c432 benchmark circuit which is almost 79% for 100 test patterns and 64% for 200 test patterns.

Keywords—Dynamic power,Runtime leakage,CMOS,Vetor reordering, Genetic algorithm.



34 1



NCCS125

REVIEW ON BAND-NOTCHING TECHNIQUES FOR ULTRA WIDEBAND ANTENNA

Ankur Saxena1, R.P.S. Gangwar2, Member, IETE 1,2Deptt. of Electronics and Communication Engineering,

College of Technology, GBPUAT, Pantnagar-263145 Uttarakhand, India

[email protected] , [email protected]

Abstract - A review on band notching techniques used in Ultra-Wide Band (UWB) antenna has been well presented. In the available wide band, the removal of small desired frequency band is termed as band-notching. The researchers have found the ways to avoid the interferences between the UWB (3.1 to 10.6GHz) and other communication systems such as WiMAX (3.3-3.88 GHz), WLAN (4.96-6.23 GHz) and ITU (7.9-8.7 GHz). In this paper, the commonly used band-notching techniques, namely, defective ground structure, slot-loading effects and split ring resonators have been studied and briefly described. A comparison of various antenna designs in each technique is made in terms of antenna size, band-width, frequency band-notches achieved and simulation tools used. The antennas under reference [1]-[2] as examples are implemented.

Index Terms—Band-notching, Defective Ground Structure (DGS), slot loading, split-ring resonator, Ultra-Wide Band (UWB)




35 1



NCCS126

REAL TIME SIMULATION DESIGN FOR CONTINUOUS PROCESS INDUSTRIES

S. Sridevi1 ,, P. Sakthivel 2

1 R&D Department, Bharathiar University, Coimbatore, India 2Department of ECE, Anna University, Chennai, India

[email protected]

, [email protected]

Abstract - Process industries with complex operations require comprehensive training for plant operators / process engineers to understand the dynamics and achieve process control efficiency. Cost effective & highly customizable simulator is the need for many industries. This paper elaborates the design, prototype & features of a generic process simulator framework, components, & interfaces to represent intelligent model formats, knowledge, facts, behaviors & rules. The benefits of fully functional simulator ranges from theoretical learning of processes to the synthesis of modeled & tuned controllers to mimic various stages / sections of a continuous process industry. Keywords - Process Simulators; Process Control; Rule Engine; Neural; MPC; Automated Process Training & Simulation framework



36 1



NCCS128

ANTENNA PATH LOSS PROPAGATION IN THE DEHRADUN REGION AT 1800 MHZ IN L- BAND

Ranjan Mishra, Adesh Kumar, Piyush Kuchhal

Department of Electronics, Instrumentation and Control Engineering, University of Petroleum and Energy Studies, Dehradun India

[email protected], [email protected], [email protected]

Abstract- A proper and good coverage is an important parameter in the planning of cellular network. Path loss models are crucial in the planning of wireless network as they assist in interference estimations, frequency assignments and evaluation of cell parameters. This paper reports results of the propagation path loss with respect to a fixed antenna height at 1800 MHz in the outskirts of Dehradun city in the state of Uttarakhand, India. The results shown in the paper are for propagation path loss considering Okamura-Hata model and Walfish Ikegami mode in the implementation of a digital cellular system in the region on the outskirt of Dehradun. An analysis of co-channel interference is also presented. 1800 MHz falls in the L-band of SHF, and after 900 MHz band, this is the most favorable frequency band for mobile communication. Keywords: Propagation Model, Spectral efficiency, Co-Channel Interference.





37 1



NCCS130

LINEARITY ANALYSIS AND OPTIMIZATION OF 5.5 GHZ INDUCTIVE SOURCE DEGENERATION LOW NOISE AMPLIFIER

Ram Kumar, Pragati Singh Ch. Anandini, and F. A. Talukdar Member IEEE Department of ECE

National Institute of Technology, Silchar [email protected]

Abstract- In this paper we presents an analysis and optimization of linearity of

Cascode Inductive Source Degeneration low noise amplifier, this has done by

using UMC .18um CMOS Technology in cadence spectre tool. In this paper

sensitivity analysis of IIP3 with respect to inductor and MOSFET width is

discussed. With optimized MOSFET width and inductor size we designed the

cascode inductive source degeneration low noise amplifier. The designed LNA

requires only a 1.8 V supply voltage and consumes 10.8 mW DC power. At 5.5

GHz, this LNA has noise figure (NF) of 1.043 dB, with input return loss of -26.65

dB, output return loss of -15.15 dB, gain 14.6 dB, IIP3 -.519 dBm.

Keywords: Cascode amplifiers Inductive Source Degeneration, Third order intercept point (IIP3).


38 1



NCCS131

PERFORMANCE ENHANCEMENT OF LTE HETNET USING EVM BASED CONSTELLATION COMBINER (ECC) IN WARP

*Mugelan R K, *Anusiya M, +Bhagyaveni M A

*,+ Department of Electronics and Communication Engineering, *,+ College of Engineering Guindy, Anna University,

Chennai, Tamil Nadu, India

*[email protected], *[email protected], [email protected]

Abstract— Cooperative communication has been recently applied to LTE networks to enable coverage extension and enhance link reliability through distributed spatial diversity. In this paper, the femto-relay cooperates with the Macro Base Station through the amplify and forward protocol to enable the transmission of data from the Macro Base Station to the Mobile Staion in a real-time indoor environment. This paper aims to improve the error performance of a cooperative relay network by using best constellation combiner. At the destination end the constellations from the direct and relay link are selected based on minimum EVM to achieve improved BER with less computation complexity. The above system with novel combining technique has been tested and analyzed in a real time scenario using Wireless Open Access Research Platform (WARP) test bed.

Keywords—LTE, Amplify and Forward, Relay, EVM, BER, WARP.


39 1



NCCS132

PERFORMANCE ANALYSIS OF 3-PHASE INDUCTION MOTOR:

THROUGH SIMULATION IN SIMULINK AND TMS320C6713

Nutan Lata Nath Pallavi Dutta Shilpi Kumari Urjaswit Lal

Dept. of E.E.E., B.I.T. Mesra, Ranchi

[email protected] [email protected] [email protected] [email protected]

Abstract—An induction motor is the most preferred choice for majority of industries hence it has drawn attention of researchers. A lot of research has been done in this domain which encompasses modelling of the induction motor under healthy conditions [1] as well as under faulty conditions [2] [3]. The authors have discussed different methods of simulating a healthy induction motor in this paper. Also a mathematical model is developed in healthy condition in SIMULINK and the stator current, rotor current, torque and speed variation with respect to time have been observed. The results observed are of both the transient and steady state. The induction motor has also been simulated in the TMS320C6713. Results from both the methods are coherent.

Keywords— d-axis; q-axis; induction motor; rotor current; SIMULINK; stator current,\; TMS320C6713; torque; speed.





40 1



NCCS135

NOVEL SYSTEMATIC OPTIMIZED DESIGN APPROACH FOR

PROCESS VARIATION SENSITIVE OTA IN LOW POWER MSIC DESIGN

R.Benschwartz, Sakthivel P

Department of Electronics and Communication Engineering, Anna University, Chennai, India


Abstract-Continuous scaling in CMOS fabrication makes Mixed Signal Integrated Circuits (MSIC) more vulnerable to process variation. This paper presents a well defined novel design methodology for process variability aware design to improve the reliability, robustness and stability of the circuit. Realistic assessments on device sensitive parameters are made by statistical methodology to accurately quantify the impact of parameters on circuit performance. Based on the proposed optimized design methodology an Operational Transconductance Amplifier (OTA) is designed. The modularity of the methodology can be validated by the output performance obtained from the OTA which is highly stable when subjected to worst case process variation scenario. In the proposed optimization the circuit is strengthened by fixing the optimum aspect ratio without adding any additional compensation devices complicating the circuit resulting in low power consumption of only 0.116mV in standard CMOS 0.18µm technology with 1.8V power supply. Keywords: MSIC, Process Voltage Temperature, Operational Transconductance amplifier, MonteCarlo Simulation.



41 1



NCCS139

A DISTRIBUTED FAULT-TOLERANT MULTIOBJECTIVE CLUSTERING ALGORITHM FOR WIRELESS SENSOR NETWORKS

Nabajyoti Mazumdar, Hari Om

Department of Computer Science & Engineering Indian School of Mines

Dhanbad, India


Abstract— Energy conservation is one of the most important challenges in

wireless sensor networks due to limited power sources of sensor nodes that cannot be recharged or replaced. Clustering has been proven to be energy efficient in WSN since it reduces the number of sensors taking part in long distance communication. In clustering, the sensor nodes decide, which cluster head they will join among several candidates. The selection of Cluster head uses different parameters such as residual energy of cluster head, distance between node and cluster head, etc. A poor selection of cluster head will lead to increased energy consumption in network that will degrade the network lifetime. Furthermore, sensor nodes are likely to fail due to different factors such as limited energy, environment hazards, etc. So, the fault tolerance is another challenge for long run of the WSNs. In this paper, we propose a Distributed Fault-tolerant Multi-objective optimizing Clustering Algorithm (DFMCA). In this algorithm, each node makes its decision based on local information. We also propose a recovery algorithm in case of sudden death of the cluster heads in network. Simulation results show that our algorithm outperforms the existing state-of-the-art algorithms, namely, FTCA and LBCA, in terms of network lifetime.

Keywords— Wireless sensor networks; clustering; network lifetime; energy efficiency.


42 1



NCCS140

COMPARING ENERGY EFFICIENCY OF DF RELAY ASSISTED COOPERATIVE AND NON-COOPERATIVE SHORT RANGE WIRELESS

SYSTEMS

Biswajit Ghosh1, Aniruddha Chandra2, and Ashis Kumar Mal3

1 IT Department, Future Institute of Engineering & Management, Kolkata 700150,

WB, India. 2 Department of Radio Electronics, Brno University of Technology, Czech

Republic. 3 ECE Department, National Institute of Technology, Durgapur 713209, WB,

India.

[email protected],[email protected],[email protected]

Abstract— In this paper we investigate the energy efficiency of cooperative relay schemes for short range wireless systems. A simple three node network topology is assumed which comprises of a source (S) node, a relay (R) node, and a destination (D) node. The relay operates in adaptive decode and forward (DF) mode and assists the direct communication between S and D. The direct signal is combined with the relayed signal following either selection combining (SC) or maximal ratio combining (MRC). The energy efficiencies of both the combining schemes are analyzed in terms of the total energy consumption per bit. The analysis reveals that cooperation may not be always lead to better energy efficiency, especially when the transmission distance is small. The effect of various communication system parameters, such as path loss exponent, spectral efficiency etc., are also examined.

Keywords-Cooperative communication; Energy efficiency; MQAM; Relay placement; Selection combining; Maximal ratio combining


43 1



NCCS141

MODIFIED PSO BASED EQUALIZERS FOR CHANNEL EQUALIZATION

D.C.Diana1, S.P.Joy Vasantha Rani2

Department of Electronics Engineering,

Madras Institute of Technology, Anna University, Chennai, India


Abstract— This paper presents a modified particle swarm optimization (PSO) as an adaptive algorithm to search for the optimum equalizer weights of transversal and decision feedback equalizers. Inertia weight is one of the PSO’s critical parameter which controls the global and local search abilities of PSO. Higher values of inertia weight enhance the global search capabilities of PSO whereas smaller values of inertia weight enhance the local search abilities of PSO with faster convergence. Different approaches are reported in literature to improve the performance of PSO by modifying the inertia weight. This work analyzes the performance of the existing modified PSO algorithms with different time varying inertia weight strategies and proposes two new strategies for channel equalization. Detailed simulations presented in this paper shows the enhanced performance characteristics of the proposed algorithms in transversal and decision feedback models. Also the simulation work analyzes the performance in linear and nonlinear channel conditions.

Keywords— Adaptive Channel Equalization, Particle Swarm Optimization, Inertia weight, Mean Square Error, Decision feedback equalizer.



44 1



NCCS143

INVESTIGATION OF ELECTROSTATIC ACTUATION SCHEME FOR LOW VOLTAGE MEMS SWITCH

Sudhanshu Kumar1, Neela Chattoraj2, Manish K. Sinha1, Niharika Danu2 1Department of Physics,Birla Institute of Technology, Mesra, Ranchi 835215

2Department of Electronics and Communication Engg., BIT Mesra, Ranchi 835215


Abstract—A low voltage MEMS switch based on electrostatic actuation scheme is introduced and investigated thoroughly. Design variables are length, width, thickness of cantilever and location of pull down electrode, for micro actuator. The model obtained is simulated in FEM based software COMSOL multiphysics. In our proposed design, the effect of presence of holes, mechanical stress, Actuation voltage and change in location of pull down electrode has been explained. With the help of structural modification and by varying actuation voltage, the optimized value of 8V is obtained which is desirable for noble performance. The capacitance is varied with the variation of dimensions and gap between two plates of beam structure with applied force, which is the basic principle of electrostatic actuation scheme.

Keywords—MEMS; switch; actuation voltage; pull in electrode; cantilever, COMSOL multiphysics.



45 1



NCCS145

INTEGRATION AND MIGRATION OF HETEROGENEOUS BIOLOGICAL DATA RESOURCES TO CLOUDS

A Chandra Sekhara Rao, Katara Chahan Rashikbhai, Haider Banka

Department of Computer Science and Engineering Indian School of Mines

Dhanbad, India

[email protected]. in, [email protected],

Abstract—The demand for biological databases and their integrations keep on increasing day by day due to its need in the field of bioinformatics for various analysis that helps in making efficient research in the field of bioinformatics. Voluminous data stored in different databases with various data formats requires the attention of integration and also cloud for various reasons. In order to provide biological data resources at one go, integration methods and use of cloud to store the databases is very much required. A new approach has been proposed for integration of different biological databases and migrating them into clouds. Experimental results with XML, FASTA formats shows the significant improvement over traditional approach.

Keywords—Bioinformatics, Heterogeneous database, Data Integration, Web services , Link Updation, Cloud Computing.



46 1



NCCS146

ON ONLINE COUNTING OF CIGARETTE IN PACKETS - AN IMAGE PROCESSING APPROACH

Abahan Sarkar, Sourav Chakrabarty, Ram Kumar , B K Roy

National Institute of Technology, Silchar, India

[email protected].

Abstract—this paper aims at designing an automated system to monitor the production in a Cigarette industry. The objectives of this work are to count the number of Cigarette in each package and compare the results to check if desired number of Cigarettes is present. The whole system is carried on with the help of image processing technique utilizing the LabVIEW platform without disturbing the high speed production line. A National Instrument’s Smart Camera 1744 is the chief hardware component used to capture images of cigarette packets moving on a conveyor belt and process them to fulfill the above objectives.The technique was subjected to on-line testing on 200 cigarette packets belonging to five different brands. The results obtained were found to be acceptable with 98.75 % accuracy.

Index Terms—Automation; Cigarette; FMCG; Image processing; LabVIEW; Online; Smart Camera.

mailto:[email protected].


47 1



NCCS149

FUZZY MIN MAX NEURAL NETWORK BASED INTRUSION DETECTION SYSTEM

Chandrashekhar Azad 1, Vijay Kumar Jha 2

1, 2Department of Computer Science and Engineering, Birla Institute of Technology Mesra, Ranchi-835215(India)

1 [email protected], 2 vkjha@ bitmesra.ac.in

Abstract - In this paper a novel intrusion detection system is proposed which is based on the fuzzy min max neural network. The aim of the proposed intrusion detection system is to protect the end user system from the cope of various types of cyber-attacks. The main hurdles in the today’s intrusion detections system are the nonlinear separability, online adaption, pre-processing of the network logs, attribute selection and the learning of the desired system for the anomalous or the signature detection. The proposed system is evaluated on the KDD CUP99 dataset and the classification accuracy, classification error are used for performance evaluation. The critical experiment on the proposed system gives the superior performance.

Keywords-Anomaly Detection, Misuse Detection, HIDS, NIDS, Fuzzy Min-Max Neural Network.


48 1



NCCS153

IDENTIFICATION AND ANALYSIS OF ESSENTIAL TREMOR USING RS-FMRI DATA BY ICA

S.P.Thaiyalnayaki, O.Uma Maheswari.

Department of ECE,College of Engineering, Guindy, Anna University,Chennai, Tamilnadu, India

[email protected]

Abstract — Localization study to identify potential degeneration in Essential Tremor (ET) is another analysis requirement of neuroimaging. In this study, 3 ET subjects of age group 65 to 70 and 3 healthy subject’s, Resting State functional Magnetic Resonance Imaging (RS-fMRI) are analyzed to infer the activated components using Independent Component Analysis (ICA). RS-fMRI BOLD signal, generated without external stimulus for ET is preprocessed for spatial realignment, slicetime correction, coregistration, normalization and smoothing. Large number of spatial independent components including cerebellum activation, auditory cortex, and visual medial network activations are identified. The number of voxels activated in cerebellum for healthy subjects is less than that identified in ET subjects, which coincides with the subject’s tremor nature and hence utilized for treatment as ET.

Keywords — Essential Tremor, RS-fMRI, ICA, Cerebellum


49 1



NCCS154

EFFECT OF STATIC SYNCHRONOUS SERIES COMPENSATOR ON POWER BALANCING IN WIND FARMS

Abhishek Gandhar, Balwinder Singh, Rintu Khanna

PEC University of Technology, Chandigarh, INDIA

[email protected], balwindersingh@ pec.ac.in, [email protected]

Abstract— Renewable energy sources such as hydro, solar, wind, bio-mass,

geothermal and tidal can be used as an alternative source of power in remote-area applications, also such sources provide a clean and environmental-friendly power. However, the main drawback of using renewable energy sources for these deserted places is the fluctuating nature and that creates problems in matching the load demand. Combinations of renewable energy sources with conventional generators make the solution more viable and affordable. For overcoming the technical and financial contingencies associated with renewable energy sources, proper control of power, coordination of subsystems, energy storage, power quality, are the main challenges. Present paper describes the theory and simulation of SSSC, a flexible Alternating Current Transmission Systems (FACTS) Controller used in the Wind power system. Two groups of wind turbine generator systems are used to design this Wind power system which is producing electricity for isolated locations. In this paper SIM POWER SYSTEM toolbox of MATLAB software is used for system simulation to investigate, the effect of SSSC on the voltage profiles under different loading conditions, and also considered for active and reactive power congestion relief of the Induction machines.

Keywords—FACTS; SSSC; MATLAB; Phase-Locked Loop; STATCOM.



50 1



NCCS157

DESIGN AND ANALYSIS OF FAST CONVOLUTION BASED MULTIRATE FILTER BANKS

K.Mariammal1 , S.P.Joy Vasantha Rani2, D.Asmitha3, Bhuvana.M.K4, Preethi.V.G5

Department of Electronics Engineering MIT Campus, Anna University

Chennai, Tamil Nadu, India

[email protected], [email protected], [email protected],[email protected],[email protected]

Abstract—In this paper, a fast convolution based multirate filter bank design using Row Bypass Multiplier(RBM), Signed Booth Multiplier(SBM), Vedic Multiplier (VM), Carry Look Ahead (CLA) adder and Kogge-Stone Adders (KSA), Han Carlson adder (HCA) and Brent Kung Adder (BKA) are proposed. To perform fast convolution, overlap add and overlap save method is incorporated which inherently uses FFT-IFFT algorithm. The optimization of a filter bank is done by modifying conventional multipliers and adders. The performance measure of a filter bank for RBM, SBM,VM, CLA, KSA,HCA & BKA is done in terms of area, power and delay. Filter bank is designed in MATLAB. Comparing to overlap add, the save method provides good response. Because in overlap add, unwanted transients occurs at the output. So that overlap save based filter bank is implemented using Cadence. The Cadence results show that there is reduction in the area and delay for the VM &HCA approach when compared with the other approaches. In addition, the power of the filter bank is considerably reduced for the VM & BKA approach when compared with other approaches.

Keywords—Filter bank, fast convolution, FFT-IFF, Row Bypass Multiplier,Signed Booth Multiplier,Vedic Multiplier,Carry Look ahead adder, Kogge-Stone adder, Han Carlson Adder and Brent Kung Adder.


51 1



NCCS159

CHARATERISATION OF TFT SENSORS FOR CHEMICAL SENSING APPLICATIONS

Ravishankar Holla, Ananth Noorithaya

Dept. of Electronics & Communication, R.V.C.E. Bangalore, India

[email protected],[email protected]

Abstract— Electronic sensors support activity in healthcare, energy, transport, environmental sustainability and mineral exploration built environment and across the consumer market. Design and integration of technologies aims to develop sensor systems with intelligence and optimised control. The need of the hour is to develop sensors which are accurate, sensitive reliable and at the same time durable, robust and cost-effective. One of the probable solutions to this is the use of Thin Film Transistors (TFTs). TFTs are the fundamental building blocks for state-of-the-art microelectronics; they are flexible, lightweight, shock resistant and relatively inexpensive. The commonly used substrate materials are glass, plastic, etc., since the primary application of TFTs is in liquid crystal displays and flexible electronics. The materials used for active layer in TFTs are amorphous Silicon, Zinc Oxide, Organic Compounds, Polymers, etc. In this work, different materials were tested as active layers, in simulation using SILVACO software, to test suitability for the sensor application. Keywords— Silvaco, TFT, sensors, organic materials, flexible electronics

mailto:[email protected],[email protected]


52 1



NCCS160

IMPLEMENTATION OF BREADTH FIRST SEARCH FOR STORAGE OPTIMIZATION IN RANDOM STORAGE ASSIGNMENT OF

AUTOMATED STORAGE AND RETRIEVAL SYSTEMS

Amiya Sagar Das, Prashant Kumar Dwivedi, Amit Kumar Mondal, Adesh Kumar, R.Manohar Reddy, Roushan Kumar

University of Petroleum and Energy Studies,

Dehradun, India

[email protected], [email protected], [email protected], [email protected], [email protected], [email protected]

Abstract— Automated Storage and Retrieval Systems (ASRS) are generally used in the production and distribution industries for storage as well as retrieval of products. In the present era, it is also used in state of the art applications like automated car parking systems, automated library management system, automated locker system, etc. Breadth First Search (BFS) is a type of un-informed searching technique in Graph Theory. This research paper explains an application of BFS technique for storage optimization of the automated storage and retrieval systems. The implementation of BFS in the random storage assignment is the core area of research. The algorithm searches the nearest empty slot for material storage. The algorithm described in the paper is flexible to change in the order of the rack matrix. To know the status (empty/filled) of the racks, a unique method which tends to exclude the array of sensors which is generally used to note the status has been discussed.

Keywords— automated storage and retrieval systems (ASRS), breadth first search (BFS), random storage assignment, storage optimization, virtual sensors








53 1



NCCS162

ANALYSIS OF OCTAGONAL SHAPE MICROSTRIP PATCH ANTENNA AT 5.70 AND 8.00 GHz

Denesh Kumar Cholkar*, Abhishek Rawat**

Samrat Ashok Technological Institute, Vidisha (MP), India.; Institute of Infrastructure Technology Research and Management, Ahmadabad, India.


Abstract— In recent years, great interest was focused on micro strip antennas for their small volumes, low profiles, good integration, minimum costs and acceptable performance. With the continuous growth of wireless communication service and the constant miniaturization of communication equipment, there are higher and higher interests for the volume of antennas, integration and working band. The Micro strip patch antennas can successfully work on multi band frequency applications, agility, immense band-width and feed line resilience. In this paper we propose design of Octagonal-shape Micro strip patch antenna at dual band. The simulation results confirm good performance of proposed design at dual band (C and X band) 5.70 and 8.0 GHz.

Keywords— Octagonal shape Micro strip patch Antenna, Return loss, Bandwidth, VSWR


54 1



NCCS165

DESIGN OF A HIGH PERFORMANCE CMOS CHARGE PUMP FOR PHASE LOCK LOOP SYNTHESIZERS

Anurag Kumar Paliwal*, Saurabh Sharma* & Adesh Kumar

* Electronics & Communication Department, Meerut Institute Of Technology, Meerut (U.P.) 250001


Abstract— A latest high performance charge pump circuit is designed and realized in 130nm CMOS process. A self biasing current mirror is used to enable the charge pump current to be matched in output voltage range. This technique does not provide perfect current mismatching characteristics but however it is one way to attain nearly perfect source/sinking current matching characteristics regardless of the charge pump output voltages. The average power consumption of the charge pump is around 0.01013mW under locked condition when it is operated under 1V power supply.

Keywords- Charge Pump, Current Mismatch, Jitter noise, Phase Lock Loop, Spur Tones.



55 1



NCCS167

MULTIBAND PLANAR ANTENNA WITH FRACTAL GEOMETRY

1Shashi Bhushan Kumar, 2P K Singhal 1RGPV, Bhopal, India

2MITS, GWALIOR, (MP)


Abstract-This paper presents a Research Issues of designing a multi band

antenna with high gain for different applications like wireless, Wi-Max, defense &

many applications. Proposed antenna was introduced to solve such type of

issues. In this paper Seirpinski’s carpet Fractal antenna of 2nd Iteration was

designed using Ie3D Software and Simulation and measurement results have

been shown and compared. It was designed & fabricated with dielectric

substrate FR4 .For Minimization of losses coaxial feeding technique was used.

Keywords- Fractal Antenna, Return loss, Gain, Coaxial feeding, Multiband Antenna




56 1



NCCS171

EFFICIENT ALGORITHMS FOR REMOVAL OF HIGH DENSITY RANDOM VALUE IMPULSE NOISES IN IMAGES

Neethi Singh, G. Vasugi Priyatharsini, O. Umamaheswari,

Department of Electronics and Communication Engineering,

CEG Anna University, Chennai-25

[email protected]

Abstract — This paper presents a new methods for random value impulsive noise detection in images corrupted by impulse noise. This proposed method consists of two stages: Noise Detection and Filtering. Noise detection of this method employs two conditions proposed by Ramadan, 2014. Two predetermined threshold values are involved to find out whether an image pixel is noisy or not. The pixels determined as noisy in the detection stage are replaced by a weighted median value of uncorrupted pixels in the filtering window and a fuzzy mechanism is applied to restore the images corrupted by impulse noise. Simulation results reveal that the condition based detection with fuzzy switching weighted median filter performs better than the other techniques.

Index Terms—Image filtering, Median Filtering, Fuzzy reasoning, Noise

Adaptive Fuzzy Switching Weighted Median Filter.


57 1



NCCS173

OPTIMIZATION OF 5.5 GHZ INDUCTIVE SOURCE DEGENERATION LNA USING NSGA II

Ram Kumar, Pragati Singh, Abahan Sarkar and F. A. Talukdar Member IEEE Department of ECE, National Institute of Technology, Silchar

Abstract- Genetic Algorithm is the most flexible, efficient and simple optimization technique. In this paper presents a optimization of tradeoff between linearity and noise figure of low noise amplifier of cascode inductive source degeneration amplifier using multiobjective NSGA II algorithm, and this has validate using UMC .18um CMOS Technology in Cadence spectre tool. We got gain 14dB, S11 -16.15 dB, S22 -16.4dB noise figure 1.037dB, IIP3 -.908 dBm with power supply of 1.8V. Keywords: Cascode amplifiers, Low Noise Amplifier (LNA), Noise Figure (NF), Non-dominated Sorting Genetic Algorithm (NSGA).


58 1



NCCS175

RELIABILITY AND ENERGY BENEFIT ANALYSIS OF DISTRIBUTION SYSTEM INCORPORATING WIND TURBINE GENERATOR

Mohini Yadav1, Prem Prakash2 , R.C.Jha3

Dept. Of EEE, BIT Mesra Ranchi

[email protected]

Abstract—Reliability is the main factor which is always considered in the distribution system, whether in terms of economy or in terms of energy benefit received from the entire distribution system. In this paper wind turbine generator used as a renewable source of supply in six bus RBTS system. The paper presents the impact on cost, energy benefit and reliability of distribution system incorporating the DG’s (wind turbine generator). In an era of smart grid, the relevance of this work is quite improved. An enhanced reliability of the distribution system will be a good opportunity for utilities because of reduction in energy losses and higher revenue. It will also reduce the interruption duration and frequency for consumers and leads to their higher satisfaction level in terms of electric power requirement.

Keywords—Wind turbine generator(WTG) , distribution system, Reliability , Roy billiton test System(RBTS), WGICB , WCIEB, SAIFI , SAIDI , ASAI , ASUI.



59 1



NCCS176

DEVELOPMENT OF SMART GRID SYSTEM IN INDIA: A SURVEY

Kovendan.AKP, Sridharan.D,

Dept. of Electronics and Communication Engineering CEG campus, Anna University

Chennai, India


Abstract— The growing population and the rapid increase in GDP have forced a greater increase in the demand of electricity. The most critical infrastructure that consumes more economy for maintenance of a nation is its Electrical grid. These challenges can be avoided by the evolution of Smart Grids. The modern advancement in ICT (Information and Communications Technology) has evolved the growth of Smart Grid Technology. The Infrastructures like Communication and Monitoring plays a key role in Smart grids. This paper aims to provide a study for researchers working in various fields including Wireless communication, Power grid communication and Smart grid about the available state of art. This work will provide a detailed literature survey of available methodologies and also highlights the possible challenges, Research issues and opportunities of Networks in Smart Grids. In monitoring applications there are two main infrastructures namely, communication and sensing infrastructure. This work will concentrate on these architectures that can be applied to Smart Grids.

Index Terms—Smart Grids, Wireless Communication, Remote Monitoring, Information and Communication Technology (ICT), Electrical Grid



60 1



NCCS177

AN EFFICIENT SPECTRUM SENSING IN RELAY BASED COGNITIVE

RADIO USING COMPRESSIVE MEASUREMENTS

Raju Kumar Allam, Kalimuthu K, Kumar R

Department of Electronics and Communication Engineering SRM University Chennai, India

[email protected], [email protected],

[email protected]

Abstract—Cognitive Radio (CR) has intelligent wireless communication system to solve spectral clogging problem and increasing bandwidth utilization for forth coming generation wireless communication applications. Computationally and energy efficient spectrum sensing for detecting spectrum holes in wideband radio spectrum still remains a challenge. The cognitive nodes which are far away from primary user (PU) may not be able to detect the PU due to severe fading in channel. Here we proposed system is used to improve the efficiency of spectrum sensing in cooperative communication system based on cognitive relay using compressive measurement algorithms. Using this proposed method, the bit error rate (BER) reduces due to increase in the probability of detection. Employing more number of relay nodes reduces the sensing time, improves the quality of communication and increases throughput of system at reasonable complexity using compressive signal processing (CSP). Keywords— Cognitive Radio (CR), Compressive Sensing/Sampling (CS), Compressive Sensing Algorithms.




61 1



NCCS179

A COMPACT MONOPOLE SLOT ANTENNA FOR X- BAND SATELLITE COMMUNICATION

Babu Lal Shahu1 , Neela Chattoraj2, Srikanta Pal3, Dileep Kumar Upadhyay4

1Department of Electronics and Communication Engineering, BIT Mesra Deoghar Campus

2,4Department of Electronics and Communication Engineering, BIT Mesra, Ranchi

3Department of Electrical Engineering, Shiv Nadar University, Dadri, Gautam Budh Nagar, U.P. India

[email protected]

Abstract- A compact monopole antenna for X- band satellite communication using coplanar waveguide (CPW) feed is presented. The proposed antenna is designed on RT/duriod 5880 substrate with thickness of 1.57 mm and relative permittivity of 2.2 having loss tangent 0.0009. The proposed antenna has the overall dimension of 19.4 x 16 mm2. The designed antenna is covering the frequency range from 7.24 GHz to 8.6 GHz suitable for X-band military application in satellite communication. The proposed antenna has stable and omnidirectional radiation patterns and peak gain variation of 2.7 to 3.4 dBi within the operating band. Keywords: CPW, Monopole Antenna, irregular slot


62 1



NCCS180

ANALYSIS OF SUB-5NM NOVEL FINFET DEVICE OVER 180NM BULK CMOS DEVICE

Denesh Kumar Sundar1*, Hari Venkateswaran1*, Latha.P1 and

Bhagyaveni.M.A2

1 Department Of ECE, St. Joseph’s College Of Engineering, Anna University, Chennai

2 Department Of ECE, College Of Engineering, Guindy, Anna University, Chennai

[email protected]

Abstract: Degradation of sub-threshold slope, higher off currents and negative

shift in the threshold voltage do not allow the traditional bulk Si-CMOS to be

scaled beyond a process node of sub-20nm technology. Also, process-induced

variation, drain induced barrier lowering and second order effects in bulk-Si

technology limit the scaling of CMOS into sub-32 nm nodes. Effective threshold

voltage control can be established through a new range of novel device

architectures. These architectures aim mostly at changing the physical dimension and orientation of the gate structure around the channel. Among the

likely candidates, FinFETs are the most attractive option because of their good

scalability. Absence of depletion capacitance, improved subthreshold slope and

lower off currents make them competent to be used as future low power

consumption devices. The gradual slope of the DC analysis curve of sub-5nm

FinFET inverters explores the possibilities of operating the Sub-5nm FinFET both

in digital and analog domains. Sub-5nm FinFETs also extend their application to

performance and yield enhancement in amplifiers, digital circuits and memory devices. The Simulation tools utilized were Synopsys TCAD for modeling the

device and cadence virtuoso for other simulations.

Index Terms—FinFET, Sub 5nm, tri-gate device, scaling, low power device, 180nm CMOS.


63 1



NCCS181

IC PACKAGING: 3D IC TECHNOLOGY & METHODS

Adesh Kumar1, Vijay Nath2, Piyush Kuchhal3, S. Choudhury4

1,3,4 Department of Electronics, Instrumentation and Control Engineering,

University of Petroleum and Energy Studies, Dehradun, India 2Dept. of ECE, BIT Mesra Ranchi-835215, Jharkhand, India

[email protected]

Abstract: The research article discusses the flow of product design helpful for semiconductor design companies. IC packaging industry is moving toward the new generation of 3D packaging which imposes new challenges in the industry. 3D IC packaging offers high density, low power dissipation and high performance. Microelectronics industries follow the 3D IC development based on the TSV technology, processing of micro bumps, helpful for interconnecting the stacking chips. The reliability of 3D IC, using TSV interposer in reviewed in detail for Xilinx FPGA environment. Water on Wafer (WoW) methodology for using BCB adhesive bonding followed by low temperature for TSV fabrication is discussed. 3D interconnection technologies possess excellent reliability and applied for 3D integration in real product applications. Cost, supply chains, and heat management are the challenges in 3D integration and Chip-Package Interaction (CPI) is also the reliability issue of 3D IC integration. To reduce the CPI, differential; heating/ cooling chip join method is discussed; effectively reduce fractures in Ultra-Low-k (ULK) Si chips. The new FPGA solutions are detailed with hardware utilization, capabilities and resources with Xilinx 3D IC packages for Virtex Scale +, Virtex Ultra Scale, Kintex Ultra Scale and Virtex -7 family FPGA technologies.

Keywords: - Electromagnetic Inference (EMI), FPGA (Field Programmable

Gate Array), Integrated Chip Package System (ICPS), System in Package (SIP), WoW (Wafer on Wafer), Through- Silicon via (TSV).


64 1



NCCS182

MODELING AND SIMULATION OF THE DYNAMIC RESPONSE OF A GENERIC MECHANICAL LINKAGE FOR CONTROL APPLICATION

UNDER THE CONSIDERATION OF THE NONLINEARITIES IMPOSED BY FRICTION

Jitendra Yadav, Dr. Geeta Agnihotri

Mechanical Engineering Department University of Petroleum and Energy Studies, Dehradun (UK)


Abstract: The present work deals with a generic mechanical linkage that is common to many mechanical systems requiring manual or automated mechanical control. While modeling a system with such control, it is necessary to include the dynamics of the control linkage in the model to obtain realistic dynamic behaviour of the overall system. Presence of inertia and elasticity in the form of a spring makes such system a second order system, with a tendency to undergo oscillatory motion during such controlled motion. Presence of friction further introduces irregularities and nonlinearities in the motion of the target inertia element. Under these conditions, the trajectory of the controlling force has to be optimized to achieve smooth controlled motion. The present paper deals with these issues, by using a pedal operated lever arrangement used in applications requiring controlled release or controlled engagement in mechanical systems. Two basic models of friction are used and compared in the present work, viz., Coulomb model and Lugre model. A sigmoid function based friction model is used for the simulation to make the Coulomb friction model continuous. First the sigmoid function based model is validated with the help of Dahl model results for a spring mass system dragged with constant velocity over a rough surface and then the results simulations for the generic linkage are compared with the Lugre friction model. The dynamic behavior of the system is assessed on the basis of total settling time of the target mass, computation time, time period of oscillation of the target mass, maximum amplitude and amplitude decay. The present study can be useful in design of actuators and mechatronic systems involving similar dynamics.

Keywords: Generic linkage, friction model, sigmoid function, control, simulation



65 1



NCCS183

DESIGN OF A THIRD ORDER SELF BIASED ADAPTIVE BANDWIDTH PLL

J. Dhurga Devi, Dept. of ECE, College of Engineering,

Anna University, Guindy, Chennai 600 025, India.

[email protected]

Abstract— This paper proposes a third order adaptive bandwidth Phase Lock Loop (PLL) for microprocessor clock generation. The PLLs employed in present day microprocessors for clock generation requires performance parameters like jitter, lock time and capture transients to be as low as possible, since the multi core scheme requires fast switching across different pairs of clock frequency and operating voltages. This paper thus proposes to modify the traditional second order self biased adaptive bandwidth PLL architecture to a third order and also a type III scheme. Simulation carried out in UMC’s 0.18μm

CMOS technology shows significant improvement in jitter performance and settling time with negligible capture over/under-shoots. Process corner simulations show that the designed third order PLL is stable and operates over a wide frequency range from 1GHz to 2.72GHz.

Index Terms— Third order PLL, Jitter, Self biased adaptive bandwidth PLL, Microprocessor clock, Capture transient, Acquisition time.



66 1



NCCS186

DESIGN OF ULTRA LOW POWER CLASS E POWER AMPLIFIER

Megha Agarwal1, Vinita Mardi2, Vijay Nath3

VLSI Design Group, Department of Electronics and Communication Engineering, Birla Institute of Technology Mesra, Ranchi


Abstract – This paper is proposed to design an ultra-low class-E Power Amplifier (PAs) circuit to analyze its power gain and output power in PSS (periodic steady state response). A technique is presented to facilitate the control power of the RF PAs (radio frequency power amplifier).The basic circuit of RF PA is designed which has different switching actions as different values of capacitors are taken into account. A driver F stage is added in the basic circuit which increases the switching action considerably. When the voltage is high, current is low and when voltage is low, current is high, thus minimising the power dissipation. The PAE obtained is 78% and power gain is 60dB. Keywords: Power Amplifier, Power Added Efficiency, Power Gain.


67 1



NCCS187

ANALYSIS OF A SELF-COMPENSATING, LOW-NOISE, LOW-POWER PLL CIRCUIT @45NM TECHNOLOGY NODE

Agnish Mal1, Akshat Chitransh2, Harsh Srivastava3, Suraj Kumar Saw4,Vijay Nath5


[email protected], [email protected], [email protected], [email protected], [email protected]

Abstract— This paper presents a novel analysis of a self-compensating, low-noise, low-power PLL circuit design implemented @45 nm technology node. The basic PLL circuit prescribed in literatures comprises of a Phase detector or Comparator followed by a Low Pass Filter and a Voltage Controlled Oscillator. The individual circuit elements have been separately designed and analyzed for achieving optimum performance and combined in cascade to form a feedback network. Simulation results obtained for the individual components have been critically investigated in the later half of the paper, which show considerable improvement in frequency stability and power consumption of the PLL design. Finally conclusions have been drawn based upon the integrated design and stress has been laid upon future scopes of work in this area.

Keywords- PLL, Current-Starved VCO, Low-Pass Filter,



68 1



NCCS191

DESIGN OF 3-BIT LOW POWER FLASH ANALOG TO DIGITAL CONVERTER (ADC) IN VLSI

Nancy Mishra1, Kumari Vijeeta Bandana2, Kumari Swati3, Suraj Kumar Saw4, Vijay Nath5

Department of ECE, VLSI Design Group

Birla Institute of Technology, Mesra, Ranchi, India


2, [email protected]

3,


5

Abstract— The real world signals are in general analog in nature. But they need to be processed and transmitted over large distances for modern uses. And hence comes the significance of digital signal. It has several advantages such as greater noise immunity, low bandwidth, minimal electromagnetic interference, cheaper circuits and so on. So we require Analog to Digital Converters (ADCs) which has now become part and parcel of every electronic circuitry. In this article, a low power and high speed 3-bit flash ADC is proposed. It consists of 23 comparators that provide thermometer coded output which is converted to a digital output by an encoder. It is simulated using cadence virtuoso gpdk045 nm CMOS technology. The op-amp uses a 1.8Volt Vdd and a -1.8Volt Vss and consumes a power of about 0.9mW (as per post layout simulations). The analog output of each comparator is encoded using CMOS logic that makes the circuit faster.

Keywords—Analog Signal, Digital Signal; Noise immunity; Comparators; Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS) technology; encoders



69 1



NCCS192

A 0.75 V UWB LNA FOR 3.1–10.6-GHZ WIRELESS APPLICATIONS

Indranil Chatterjee1, Lakshya Jain2, Avi Jain3, G Karthik4 Suraj Kumar Saw5, Vijay Nath6


[email protected], [email protected], [email protected], [email protected], [email protected]. [email protected]

6

Abstract— In this paper, a low voltage CMOS low noise amplifier (LNA) for ultra wideband wireless application has been presented. A cascade based topology has been proposed to reduce the supply voltage of the proposed LNA. In order to improve the noise figure over the desired band and for input matching a high pass filter is chosen. The proposed LNA performed on a 750 mV supply voltage and the post simulation results provides us a power gain S21 of 28.75 dB with a gain ripple of ± 3.75 dB in the frequency range of 3.1-10.6 GHz. The noise figure is minimum at 5.6 GHz with a value of 2.9 dB and varies maximum up to 4.54 dB, the input return losses goes up to -12.5 dB in the desired band.

Keywords—LNA(low noise amplifier); UWB(ultra wide band); Noise figure; Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS)



70 1



NCCS193

DESIGN AND IMPLEMENTATION OF A REACTION TIMER USING CMOS LOGIC

Arun V.H.P.S.S1, Venkata Ravi Teja reddy.Y 2, Srikar .M.S.P 3, Sai Charan.A4 Suraj Kumar Saw5, Vijay Nath6


[email protected], [email protected], [email protected], [email protected], [email protected], [email protected]

Abstract— This paper presents a Reaction timer, accurate to two decimal places (which is extendable), using three Decade counters. Each Decade counter, in turn uses four Master-Slave JK Flip-Flops that form a combinational circuit. A Delay is also introduced at the input, so that the result is genuine all simulation worked is carried out in cadence virtuoso analog design environment of gpdk045 nm technology with a supply voltage of 1 V.

Keywords—Decade-counter;Master-Slave;JK-FlipFlop; Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS) technology


71 1



NCCS194

DESIGN AND ANALYSIS OF CURRENT STARVED VOLTAGE CONTROLLED OSCILLATOR @ 45NM CMOS TECHNOLOGY

Sharad kumar1, Soumendra Kumar Dash2, Sidhant Sahoo3, Bandi Jagdeeshwar Reddy4, Suraj Kumar Saw5, Vijay Nath6

[email protected],[email protected], [email protected],


Abstract— An oscillator is an electronic device that used for the aim of generating a signal or waveform. Applications vary from clock generation in microprocessors to carrier synthesis in cellular telephones, requiring vastly different oscillators, oscillators’ topologies and performance parameters. VCO can be built using many circuit techniques. This paper deals with the design and implementation of a 7 stage Current Starved voltage controlled oscillators (CSVCO) using 45nm CMOS technology. CMOS circuitry in VLSI dissipates less power when static, and is denser than other implementations having same functionality. A VCO is an oscillator, where the control voltage controls the oscillator output frequency. The simulation of CSVCO is done in Cadence Software.

Keywords—Low power; Phase Noise; Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS) technology




72 1



NCCS195

EVALUATING THE PERFORMANCE OF DYE SENSITIZED SOLAR CELL WITH THE VARIOUS KEY COMPONENTS LIKE ELECTRODES,

DYES & ELECTROLYTES

Rishi Sharma1, Kumar Amit1*, , P. K. Barhai1 and R. L. Boxmann2 Department of Physics,BIT Mesra & School of Electrical Engineering1, Tel Aviv

University, P.O.B. 39040 Tel Aviv 69978, Israel2


Abstract- Dye Sensitized Solar Cells (DSSC) which when compared to other thin film solar cells holds virtues like greater price to performance ratio, low cost of manufacturing, ability to work at wider spectrum & low light and is mechanically robust. DSSCs have been fabricated with different combination of conducting electrodes, dyes and electrolytes. For fabrication of DSSCs, TiO2 has been used as a wide band gap semiconductor. Performance of these cells have been studied. Short circuit current, open circuit voltage, fill factor, and efficiency of these cells have also been reported. It has been observed that these parameters depend on the combination of the electrode, dye and electrolyte. Possibility of graphene as a transparent electrode has also been explored.

Keywords— Dye Sensitized Solar Cells; Tin-doped indium oxide; aluminum doped zinc oxide, graphene


73 1



NCCS196

DESIGN OF RING OSCILLATOR USING PSEUDO, DEPLETION NMOS AND CMOS LOGIC

Rahul Agrawal, Piyush Kumar Singh, Vijay Nath Department of Electronics and Communication Engineering, Birla Institute of

Technology Mesra, Ranchi ‘

[email protected]

Abstract— In this article, design of ring oscillator is provided using Depletion, Pseudo NMOS and CMOS logic. These circuits have variety of applications in microprocessors, telephone switching and wireless communication systems. Due to its implementation in CMOS technology, it provides high performance, low power consumption and compactness in the systems. Here five stages oscillator are designed and its output characteristics are analysed. After analysis it is found that CMOS is more suitable as it consumes less power. Keywords— Ring Oscillator, Inverter, Complementary Metal Oxide Semiconductor FET (CMOS), Time Delay.


74 1



NCCS197

DESIGN OF LOW POWER OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

Namrata Yadav, Sarita Kumari, Subhra Chakraborty and Vijay Nath Department of Electronics and Communication Engineering, Birla Institute of

Technology Mesra, Ranchi


Abstract- This paper is proposed Operational transconductance amplifier based on Recyclic Folded Cascode (RFC) with positive feedback to achieve high DC gain and Unity Gain Bandwidth(UGB). RFC OTAs is implemented using UMC90nm technology and studied through simulation. From the simulation, it is found that the DC gain of RFC OTA is higher by 24 dB. The Slew rate of ERFC OTA is higher by a factor of 1.14, 1.08 compared to RFC. Keywords— Low power OTA; Recyclic Folded Cascode; current mirror; transconductance

mailto:[email protected],%[email protected]


75 1



NCCS198

DESIGN OF COMPARATOR IN SIGMA DELTA ADC USING 45NM CMOS TECHNOLOGY

Varun Kumar1, Krishan Kumar Singh2, Abhishek Pandey3, Vijay Nath4 Department of Electronics and Communication Engineering, Birla Institute of

Technology Mesra, Ranchi

[email protected], [email protected] [email protected], [email protected]

Abstract—An energy efficient comparator circuit for sigma delta ADC has been proposed in this paper. The proposed comparator uses CMOS two stage op amp. The designed op amp shows 89 dB gain, 2.3 GHz UGB, 65o Phase Margin with 1.02 mW power dissipation. Both Op amp and comparator output responses have been extracted from the circuit at ±1V operating voltage. The proposed circuit is simulated in Cadence Analog Design Environment with gpdk045nm library. The circuit has been designed for the simulation result of comparator shows -100mV to 500mV.

Keywords—Low Power (Milli-Watt);High Range. Operational Amplifier, Comparator

mailto:[email protected],%[email protected],%[email protected]



76 1



NCCS199

A 21NW CMOS OPERATIONAL AMPLIFIER FOR BIOMEDICAL APPLICATION

Sarika Tyagi, Swapnil Saurav, Abhishek Pandey, Vijay Nath

Electronics and Communication Engineering Department Birla Institute of Technology, Mesra

Ranchi, Jharkhand, India, Pin-835215

[email protected]

Abstract—In this paper CMOS operational amplifier using a two stage has been enunciated for low power device application by using it in subthreshold region. The proposed Op amp shows high gain as well as moderate UGB using capacitor compensation technique circuit. It is operated on rail to rail power supply of ±500mV. This amplifier is highly useful for biomedical application due to low power consumption. The designed operational amplifier gain is 48dB, bandwidth is 29 KHz and phase margin is 61O, and slew rate is 50.6V/µS with 21 nW power consumption. This c i r c u i t is designed using Cadence analog & digital system design tools of UMC 90nm C M O S technology.

Keywords— CMOS Op-Amp, Phase Margin, Slew Rate, Unity gain Bandwidth.


77 1



NCCS200

A 1.45 MW CMOS 4 BIT MULTIPLIER CIRCUIT

Mohd. Javed Khan1, Arsalan Nabi Siddiqui2, Suraj Kumar Saw3, Vijay Nath4

Department of Electronics and Communication Engineering, Birla Institute of Technology Mesra, Ranchi

mjkec28iiem@gmail1,[email protected],[email protected], [email protected]

Abstract—In this paper an ultra-low power CMOS 4 bit multiplier circuit has been proposed. This CMOS multiplier is applicable in electronics industry especially digital signal processing (DSP), image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. Multipliers of various bit-widths are frequently required in VLSI from processors to application specific integrated circuits (ASICs). Keywords—Multiplier, CMOS design style, Ultra low power, Transmission Gate (TG).


78 1



NCCS201

PREDICTION DEPTH AVARAGE VELOCITY AND BOUNDARY SHEAR STRESS DISTRIBUTION IN A SINGLE STAGE CHANNEL BY

LATERAL DISTRIBUTION METHOD

Bhabani Shankar Das1, Kishanjit K. Khatua2, Kamalini Devi3

1,2,3 Department of Civil Engineering, N.I.T. Rourkela, India


Abstract - This paper examines the use of LDM (Lateral Distribution Method) in the computation of depth averaged velocity and boundary shear stress in the single stage channel (simple channel). Generally in the non-monsoon time the river flows within the bank that means the water flows within the river only. We consider a trapezoidal channel of four different depths for the present analysis. To find the depth averaged velocity and the boundary shear stress is always a challenge for water resource engineer. The efficiency of the model mainly depend upon three parameter 1) surface parameter like manning’s n, chezy’s c, Darcy’s f, 2) geometrical parameter like area, hydraulic radius and 3) hydraulic parameter friction slope. In this research work the LDM equation is discretized by Finite difference scheme and for solving those equations, MATLAB tool is used. CES (Conveyance and Afflux Estimation System) is commercial software which is used for the computing depth averaged velocity and boundary shear stress in open channel flow. In this paper, the details mathematical solution of LDM by finite difference method is presented for the simple channel case. The results of depth averaged velocity and boundary shear stress obtained from LDM approach is validated well with the experimental data sets and this LDM approach is compared with the numerical software CES and gives satisfactory results for simple channel.

Keywords—Depth averaged velocity, boundary shear stress, LDM, CES, MATLAB





79 1



NCCS202

FLOW COMPUTATION IN SYMMETRIC AND ASYMMETRIC COMPOUND CHANNELS USING CONVEYANCE ESTIMATION

SYSTEM

Kamalini Devi 1, Kishanjit K. Khatua2, Jnana Ranjan Khuntia3

1,2,3 Department of Civil Engineering, N.I.T. Rourkela, India

[email protected], [email protected], - [email protected]

Abstract - In over bank flow, there is a strong interaction between the main channel and floodplain flows. So the discharge at different interfaces of the compound sections varies greatly. There are many reports found in literature related to compound channel with symmetrical flood plains and very few are found for asymmetrical cases. In a symmetrical compound channel the momentum transfer occurs uniformly from both sides of the channel to the flood plains. But in case of a asymmetrical compound channel, there is a stronger interaction between the flow main channel and flood plains than the symmetrical case. Many researchers have studied and modeled in predicting the flow variables for the symmetrical compound channel. In this paper, the application and suitability of using the standard software CES for predicting the flow is described. The approaches were also applied to a number of experimental data sets and the results were compared well. Three different division methods have been used for predicting discharge in four different channel cross sections with varied geometric dimensions. The divisions are generally based on location of vertical, horizontal and inclined interfaces of the channel. CES software tool is used for simulating the flow variables and the applicability of the software CES to such channels is discussed. The results from three division methods and the CES have been compared to their corresponding experimental values using error analysis.

Keywords- compound channel, symmetric, width ratio, relative depth, interface plains, overbank flow





80 1



NCCS203

EFFECT OF TEMPERATURE ON DARK CURRENT IN QWIP FOR UNMANNED AERIAL VEHICLES

Vishal Kumar1, Surbhi Sharma2, R.K. Lal3

1,2 3Department of Electronics and Communication Engineering, Birla Institute of Technology Mesra, Ranchi India

[email protected]

Abstract—This paper deals with results of optimizing the structure and temperature effects leading to dark current mitigation in Quantum Well Infrared Photodetector (QWIP) using mathematical modeling. The quantum wells are formed by sandwiching a small bandgap material between large bandgap materials. Results show that the fine tuning of aluminium mole fraction and well width helps in achieving high responsivity for the both near & far IR wavelength. A comparative study at different temperature was carried out for detectivity of the QWIP. The modeled QWIP detector consists of GaAs quantum wells and AlxGa (1-x)As barriers. The temperature causing band splitting and reduction of dark current is observed in MQW structure. This type of QW finds application in Broadband sensors used in Unmanned Aerial Vehicles (UAV).

Index Terms— Quantum Well Infrared Photodetector QWIP, reduction of dark current, temperature effect, optical efficiency, quantum confinement, mini-bands.



81 1



NCCS204

DESIGN OF CIRCULAR DISC MONOPOLE ANTENNA FOR UWB APPLICATION

Md Maqubool Hosain1, Sumana Kumari2 and Anjini Kumar Tiwary3 1,2 3Department of Electronics and Communication Engineering,

Birla Institute of Technology Mesra, Ranchi India

[email protected], sumana_keya@ rediffmail.com and [email protected]

Abstract—A novel design of circular disc monopole antenna is proposed for ultra wideband (UWB) applications. This antenna is printed on a dielectric substrate and fed by a 50 ohm CPW on the same side of the substrate. A stub is introduced across the feed line for improving the performances. In addition, the bandwidth is enhanced using modified ground plane. The simulated result shows that the antenna can yield an impedance bandwidth of 2.58-12GHz with reflection coefficient less than -10dB and voltage standing wave ratio (VSWR) is less than 2 and the peak antenna gain is up to 2.5 dBi. A good agreement is achieved between the simulation and the experiment.

Keywords— Ultra wideband (UWB); Circular disc monopole; CPW-fed; printed antennas; Stub; Bandwidth enhancement.

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