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Code No: A0601J AWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

M.Tech I Semester Regular Examinations March 2010DIGITAL SYSTEM DESIGN

(COMMON TO DIGITAL SYSTEMS & COMPUTER ELECTRONICS, DIGITALELECTRONICS & COMMUNICATION SYSTEMS, VLSI SYSTEM DESIGN)

Time: 3hours Max.Marks:60

Answer any five questionsAll questions carry equal marks- - -

1. a) Draw an ASM chart to design a sequence detector which can detect an inputsequence in non overlapping strings of three inputs each and produces a 1 outputcoincident with the last input of the string if and only if the string consisted ofeither two or three 1s.eg: If input sequence is 010101 110, the required output sequence is 000001001.Use SR flip flop in your realization.

b) Explain the ASM design blocks.

2. The cell output of a typical cell of an iterative network is equal to 1 if and only if

the input pattern of the preceding cells consists of groups of 0s and 1s, such thateach group contains an odd number of members. Construct a cell table, realize thetypical cell using AND, OR, NOT logic.

3. a) In the gate network shown, only wires m, n, p and q may become either SA0 orSA1. Construct a fault table and find a minimal cover of the table and use it todetermine a minimal fault detection experiment.

b) Show that2

( )i j i j i j

df d f df df

d xx dxdx dx dx= .

4. a) Find all the tests to detect h SA0 and k SA1 faults by applying path sensitizationtechnique to the given circuit below.

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b) Explain Kohavis algorithm for the given sum of product function to be realizedusing AND-OR logic.

( , , , ) BC AC BDf A B C D A + += .

5. a) It is necessary to determine the final state of the machine shown below when theinitial state is unknown and only output sequences from the machine areavailable to the experiments. Derive the procedure to determine the final state of

the machine.PS NS,2

x =0 x =1A B,0 C,0B A,0 D,1C D,1 B,0D A,1 D,1

b) Explain the properties of a successor tree.

6. a) Explain about the fault model of PLA, with an example and derive the test vector

set for the example.b) Explain the EPC theorem that is used in IISC algorithm to minimize the function

to be implemented on PLA.

7. Apply COMPACT algorithm to fold the PLA column wise for the given SSRtable for columns.

Column SSRA 3,6,8B 1,2,4,5,9,11C 1,3,6,7,9,10D 2,5,7,8,12

E 1,3,6,11F 4,6,7,8,10G 1,3,5,7,9H 6,8,12

8. a) Design a flow table for a fundamental mode sequential circuit with two inputs, x1and x2 and one output z. z=1 if both equal to 0, but only if x1 becomes 0 before x2.

b) For the given reduced flow table, find an assignment which contains no criticalraces and requires a minimum of secondary variables.

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