1.Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

7/23/2019 1.Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

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Aging-Aware Reliable Multiplier Design

WithAdaptive Hold Logic

Abstract

Digital multipliers are among the most critical arithmetic functional units.

The overall performance of these systems depends on the throughput of the

multiplier. Meanwhile, the negative bias temperature instability eect occurs

when a pMOS transistor is under negative bias (V gs !V dd", increasing the

threshold voltage of the pMOS transistor, and reducing multiplier speed. #similar phenomenon, positive bias temperature instability, occurs when an

nMOS transistor is under positive bias. $oth eects degrade transistor speed,

and in the long term, the system may fail due to timing violations. Therefore,

it is important to design reliable high%performance multipliers. &n this paper,

we propose an aging%aware multiplier design with anovel adaptive hold logic

(#'" circuit. The multiplier is able to provide higher throughput through the

variable latency and can ad)ust the #' circuit to mitigate performance

degradation that is due to the aging eect. Moreover, the proposed

architecture can be applied to a column% or row%bypassing multiplier. The

e*perimental results show that our proposed architecture with+ -+ and /

-/ column%bypassing multipliers can attain up to /.001 and 2./01

performance improvement, respectively, compared with +-+ and /-/

3*ed%latency column%bypassing multipliers. 4urthermore, our proposed

architecture with + - + and / - / row%bypassing multipliers can achieve

up to 05.+21 and 6.751 performance improvement as compared with

+-+ and / - / 3*ed%latency row%bypassing multipliers.

4urther Details 8ontact9 # :inay 6557, 5022//++/Email: infota!eo"pro#ects$com % www$ta!eo"pro#ects$com



Index Terms—#daptive hold logic (#'", negative bias temperature

instability (;$T&", positive bias temperature instability (<$T&", reliable

multiplier, variable latency.

Existing Method:

Digital multipliers are among the most critical arithmetic functional units in many

applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The

throughput of these applications depends on multipliers, and if the multipliers are too slow, the

performance of entire circuits will be reduced. Furthermore, negative bias temperature instability

(NBTI occurs when a p!"# transistor is under negative bias (V gs $ %V dd. In this situation, the

interaction between inversion layer holes and hydrogen&passivated #i atoms brea's the Si='

bond generated during the oidation process, generating ) or )* molecules. +hen these

molecules diffuse away, interface traps are left. The accumulated interface traps between silicon

and the gate oide interface result in increased threshold voltage (V th, reducing the circuit

switching speed. +hen the biased voltage is removed, the reverse reaction occurs, reducing the

NBTI effect. )owever, the reverse reaction does not eliminate all the interface traps generated

during the stress phase, and V th is increased in the long term. )ence, it is important to design a

reliable high&performance multiplier.

Proposed Method:

traditional method to mitigate the aging effect is overdesignincluding such things as

guard&banding andgate oversi-ing however, this approach can be very pessimisticand area and

power inefficient. To avoid this problem,many NBTI&aware methodologies have been

proposed.n NBTI&aware technology mapping techni/ue was proposedto guarantee the




performance of the circuit during itslifetime.n NBTI&aware sleep transistor was designedto

reduce the aging effects on 0!"# sleep&transistors, and thelifetime stability of the power&gated

circuits under consideration was improved. also proposed an ;$T& optimi>ation

method thatconsidered path sensiti>ation . Dynamicvoltage scaling and

body%basing techni?ues were proposed toreduce power or e*tend circuit life.

These techni?ues, however,re?uire circuit modi3cation or do not provide

optimi>ation ofspeci3c circuits.

System Configuration:-

In the hardware part a normal computer where 1ilin I#2 34.5 software can be easily

operated is re/uired, i.e., with a minimum system configuration

HARDWARE REQ!REME"#

Pro$essor - Pentium %!!!

Speed - &'& (H)

RAM - & (* +min,

Hard Dis - ./ (*

01oppy Dri2e - &'.. M*

3ey *oard - Standard Windo4s 3ey5oard

Mouse - #4o or #hree *utton Mouse

Monitor - S6(A




S70#WARE REQ!REME"#S

7perating System :Windo4s898;<///=PWindo4s>

0ront End : Mode1sim ?'@ for De5ugging and =i1inx &.'@ for

Synthesis and Hard Ware !mp1ementation

#his soft4ares 4here 6eri1og sour$e $ode $an 5e used for design

imp1ementation'


1.Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

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