Department of Electrical and Computer Engineering,University of Calgary

DEFERRED ENEL415JANUARY 2000 3 HOURS

NAME:- ID#:-

PLEASE WRITE CLEARLY. USE AN HB GRADE OR SOFTER (DARKER) PENCIL! WHAT I CAN=T READ WILL MARKED WRONG.

CLOSED BOOK EXAMDO NOT BRING ANY UNAUTHORIZED MATERIAL INTO THE

EXAM ROOM

The student is provided copies of the 68000 reference charts, PI/T and SDS reference sheets as part of the exam handout.

NO CALCULATORS ARE ALLOWED IN THIS EXAM

Attempt all THREE questions from SECTION Aand ANY TWO questions from SECTION B.

All questions are approximated weighted equally in terms of marks, but not difficulty

On the attached Performance Analysis sheet, estimate your performance on each question for bonus marks. Maximum bonus of 5 marks

The attached Performance Analysis sheet shows the topics covered in each question. Use this information to plan which questions you should answer to maximize your mark during this exam.

A hint of the time to spend on each part of a question is given by the relative number of marks associated with that question part. Answer the questions in the space provided on the exam sheet. The space and marks allocated are an indication of the depth of the answer expected.

Make sure that you provide appropriate documentation of code and answers as marks are allocated for this documentation. Follow standard AC/C++@ conventions and recommended safe practices in your coding.

Many of the concepts in this course are subjective – meaning that there may be more than one valid answer. Make sure that you support your answer. If the question says – which instruction is better MOVEQ.L or MOVE.L in this situation, then answering MOVEQ will give you no marks, even if true. Support why that answer is true, preferably with examples in point form

As an engineer at work, you will be expected to answer questions by coming quickly to the point. The same is true in this exam. Many students spend an unnecessary amount of time writing an extremely lengthy answer when a short answer, preferable in point form, is what is required.

If the question says –

Provide a short answer in no more than 2 -- 3 lines

then follow the instructions! Think about the answer rather than using a shot-gun approach and just writing down EVERYTHING you know. For questions like this. only the first 2 -- 3 lines of your answer will be marked and the remainder ignored. (If your writing is neat, you’ll probably get away with an extra line.)

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Q1. Answer the following question based on the screen dump (FIGURE 1) to be found on EXTRA PAGE 2 of the attached sheets. A student debugging some code during an ENEL415 Laboratory using the SDS environment generated this screen dump.

Example Answer. Suppose the screen dump represents the values to which the memory and register values of a 68K processor have been set BEFORE the instruction MOVEQ.L #-4, D0 is executed. What will be the changes to the register values as the result of executing the MOVEQ.L #-4, D0 instruction?

D0 = 0xFFFFFFFC PC = 0x50022 SR register N=1, V=? C=? Z=0

A) Suppose the screen dump now represents the values to which the memory and register values of a 68K processor have been set BEFORE the instruction MOVE.W 0x60000, D1 is executed. What will be the changes to the register values as the result of executing the MOVE.W 0x60000, D1 instruction?

2.0 marks

B) Suppose the screen dump now represents the values to which the memory and register values of a 68K processor have been set BEFORE the instruction MOVE.W #0x60000, D2 is executed. What will be the changes to the register values as the result of executing the MOVE.W #0x60000, D2 instruction?

2.0 marks

C) Suppose the screen dump now represents the values to which the memory and register values of a 68K processor have been set BEFORE the instruction MOVE.L 0x60000, D3 is executed. What will be the changes to the register values as the result of executing the MOVE.L 0x60000, D3 instruction?

2.0 marks

D) Suppose the screen dump now represents the values to which the memory and register values of a 68K processor have been set BEFORE the instruction LEA (4, SP), A0 is executed. What will be the changes to the register values as the result of executing the LEA (4, SP), A0 instruction?

2.0 marks

E) Suppose the screen dump now represents the values to which the memory and register values of a 68K processor have been set BEFORE the instructions

MOVE.L D3, A3 MOVE.L D3, (A3)+ MOVE.L A3, D3

are executed. What will be the changes to the register values as the result of executing these instructions?.

3.0 marks

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In this second part of question 1, the questions suppose that the screen dump now represents the values to which the memory and register values of a 68K processor have been set BEFORE the first instruction in the subroutine

void ActivateLights(char *pt, short int whichcorner, short int whichlight) has been executed.

G) What value has been passed to the subroutine as the parameter short int whichcorner? 1 mark

H) What value has been placed on the stack as the parameter short int whichlight? 1 mark

I) When this subroutine has been completed and exits (via an RTS instruction), at what memory location will the program continue?

1.5 marks

J) Suppose the first instruction of the subroutine has been written asMOVE.W (INPAR2, SP), D4

What value will be placed in register D4 after this instruction has been executed if the student has set the constant INPAR2 to the value8? Explain, in 3 or 4 lines, why this will not be the correct value for the 2nd parameter passed to the subroutine void ActivateLights(char *pt, short int whichcorner, short int whichlight)

2.5 marks

G) Suppose that the first instruction of the subroutine isMOVE.L #0x4000, D5

Explain, in 4 or 5 lines, why it is possible that the program MAY crash, even if the value stored in register D5 is not used anywhere in the subroutine? Under what circumstances will the program not crash? If the student needed to use register D5 during the subroutine, what should the student have done? Provide the necessary code

3 marks

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Q2 A) The MIPS processor has 30 address lines. Just what would the PARTIAL DECODE LOGIC look like to activate the chip select line (CS*) for a PI/T with a base address of 0x17FFF700 when attached to the MIPS processor

address bus. HINT: Consider that the PI/T here has the same register configuration as those in the laboratory so you will need the information associated with PITNAMES.H (see EXTRA PAGE 2). Assume you have 32-input AND gate and as many 1-input inverters as necessary to build the DECODE LOGIC.

3 marks

In this class you were instructed by Skylar in some of the basic differences between using the MIPS RISC processor and the 68K CISC processor. This part of the exam will cover those differences.

B) What would be the 68K instruction sequence equivalent to the MIPS instruction ADD $t0, $t0, $t1 (t0 = t1 + t0)? 1 mark

C) Would the single instruction from Part B run faster on an 8 MHz 68K processor or on an 8 MHz MIPS processor? Explain your reasoning in 1 or 2 lines.

2 marks

D) Would your answer to Part C change if there were 4 or 5 consecutive instructions equivalent to the ADD $t0, $t0, $t1 format rather than just 1 instruction? Explain your reasoning in 1 or 2 lines.

1 mark

E) In the class notes I gave to Skylar, I incorrectly said that the equivalent 68K instruction sequence to the MIPS instruction ADD $t2, $t1, $t0 would be

ADD.L D0, D1MOVE.L D1, D2

In fact there are some very nasty hidden program bugs in that simple 68K code sequence if you follow the standard SDS register conventions. What are these hidden bugs? (1.5 marks each bug for a maximum of 3 marks).

3 marks

F) What is the function of the Link Register on the MIPS processor? What part(s) of a 68K microprocessor system will play the same role as the Link Register on the MIPS processor?

1 mark

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G) What is meant by a Low level Register Transfer Language (RTL) description of an instruction? Answer in 1 or 2 lines

1.5 marks

H) FOR A MIPS processor, what will be the instruction phase before the DECODE phase 1 mark

I) Provide the low level RTL description of the MIPS instruction ADD $t0, $t1, $t2. Assume an internal processor architecture equivalent to that on the Motorola 68000 2.5 marks

Consider the following 68K instruction sequence that moves a value from one memory location to another.MOVE.L 0x6800, 0x6810

J) This 68K instruction would have to be translated into a number of MIPS processor instructions because the MIPS processor is said to have a LOAD and STORE architecture. What does LOAD and STORE architecture mean?

2 marks

K) What would be the equivalent MIPS code sequence to the code sequence MOVE.L 0x6800, (A0). 3 marks

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Q3

A) Consider the code segment above written by a student supposedly to handle the ISR component of Laboratory 5. Consider the instructions starting at memory locations 0x1048 and 0x104A. Complete the table below to show the timing of these instructions on a non-pipelined 68K processor, WITHOUT prefetch, when the memory fetches are 3 times as long as any internal operations of the processor.

4 marks

FETCH DECODE EXECUTE WRITEBACK

B) Consider the code segment above written by a student supposedly to handle the ISR component of Laboratory 5. Consider the instructions starting at memory locations 0x1048 and 0x104A. Complete the table below to show the timing of these instructions on a non-pipelined 68K processor, WITH prefetch, when the memory fetches are 3 times as long as any internal operations of the processor.

4 marks

FETCH DECODE EXECUTE WRITEBACK

C) Why would you suspect that this code was meant to be from an interrupt service routine, and why would you suspect that the code would cause the students program to crash?

2 marks

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If you answer Question 4 you are going to be asked to make use of 2 interrupt service routines activated through the H2 and H4 lines of a PI/T (Parallel Interface and Timer) with a base address of 0x41B000. Every time the H2 line is activated a level 3 interrupt is produced and the “C-callable” interrupt service routine void RedSensor_ISR(void) is activated. Every time the H4 line is activated a level 5 interrupt is produced and the “C-callable” interrupt service routine void ClockSignal_ISR(void) is activated.

F) Write the 68K assembly code for the “C callable” subroutine void SetInterruptVectors(void) that will set the level 3 and level 5 interrupt vectors so that the correct interrupt service routines will be called when the H2 and H4 interrupt lines are activated.

4 marks

HINT: In Q1 you ignored any changes of the SR register. Can you now?

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C) Write the 68K assembly code for the “C-callable” subroutine void ActivatePITwithInterrupts(long int activate) that will Set up all the pins on PORTA for non-latched input and PORTB for single-buffered (latched) output Set up pins H2 and H4 for edge triggered interrupts for a low to high transition Activate the H2 and H4 interrupts if the high bit (bit 31) of the parameter activate is set. PI/T Register name and bit information is given on EXTRA PAGES 2, 3 and 4 of the attached sheets

6 marks

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SECTION BATTEMPT ANY 3 QUESTIONS FROM THIS SECTION

THE QUESTIONS IN THIS SECTION ARE INTENDED TO BE MORE DIFFICULT THAN THOSE FROM SECTION A

These are open-ended Design questions and you may be required to make some educated, engineering relevant, design decisions. Since these are open-ended questions then make sure that you don’t spend an unreasonable

amount of time answering the questions.

Q4) Consider Figure 2 on EXTRA PAGE 4. This figure shows the control mechanism for a candy maker. In England, a favourite candy (sweet) is HUNDREDs and THOUSANDs. This is a very tiny candy almost the size of dust – typically coloured RED, BLUE and GREEN -- which are collected into a small plastic bag.

You are provided with the following information

You are to make use of a PI/T with a base address of 0x41B000. The CLOCK logic signal is connected to the H4 line and has to be made to cause an interrupt each time a HIGH to

LOW transition occurs The RED SENSOR signal is connected to the H2 line and has to be made to cause an interrupt each time a HIGH

to LOW transition occurs You are provided (no need to write) with a working version of the “C” callable code void SetInterruptVectors(void)

which sets the exception vector table so that a H2 interrupt will call void Clock void RedSensor_ISR(void) and the H4 interrupt will call void ClockSignal_ISR(void). See Question 3 for more details The ClockSignal_ISR routine simply increments the global “C” semaphore (variable) clockcount (see below) The RedSensor_ISR routine checks the clockcount variable and sets the PORT B pin(s) as follows

Below a count of 100, set the SYSTEM_TOOFAST pin (pin 0) Between (and including) a count of 100 and 255, set the SYSTEM_OKAY pin (pin 1). If the count is above 200, set the GETTING_SLOW pin (pin 2). Above a count of 255, set the SYSTEM_SLOW pin (pin 3) and clear the GETTING_SLOW signal After setting the PORTB pins, clear the clockcount variable so that another counting session can occur.

You are provided (no need to write) with a working version of the “C-callable” code void ActivatePITwithInterrupts(long int activate) which sets up the PI/T registers for handling the required interrupts. See Question 3 for more details.

During this question your job is to DESIGN, DOCUMENT and DEVELOP a program using a combination of “C/C++” and 68K assembly code to test this control equipment to ensure that the maximum amount of time between the dropping of a red candy piece is less than 255 clock ticks but more than 100 clock ticks.

A) Translate the following “C/C++” main() routine which sets up the interrupts and then waits in an infinite loop 4 marks

// extern short int clockcount;

// void main(void) {

// SetInterruptVectors();

// ActivatePITwithInterrupts(0);

// clockcount = 0;

// ActivatePITwithInterrupts(0x8000000);

// for ( ; ; ) /* do nothing loop */ ;// } PAGE 8 OF 15

B) Translate the following “C/C++ code” into SDS compatible 68K assembly language code. Assume that the

interrupt signal does not need acknowledging. 4 marks

// short int clockcount;

// #pragma interrupt();

// void ClockSignal_ISR(void) {

// clockcount++;

// }

C) Write the SDS compatible 68K assembly language code for the ISR routine (void) RedSensor_ISR(void). Assume that the interrupt signal does not need acknowledging.

12 marks

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Q5 A) In Laboratory 3, the concept of examining a bit in a device register using WAITS, POLLING and INTERRUPTS was introduced. In this question you are going to demonstrate your knowledge of the differences and relative advantages between waiting and polling for a bit to be ready.

Setting the scene. A PI/T has been initialized and is ready for use with the PORTA pins ready for input. Assume that you are provided (you don’t need to write) with a subroutine char ReadPIT(void) which returns a value from the PORTA pins. Inside the routine ReadPIT() the pin voltages are automatically reset to zero after the value from the PIT pins has been read. The subroutine void Pin7Stuff(void) must be activated when PIN7 becomes set. The subroutine void Pin0Stuff(void) must be activated when PIN0 becomes set.

A) Using the routines described above, write the “C-code” that demonstrates “waiting” for pins 0 and 7 to become set before calling the necessary routines Pin0Stuff() and Pin7Stuff(). Now translate into 68K assembly code

4 marks

B) Using the routines described above write the “C-code” that demonstrates “polling” for pins 0 and 7 to become set before calling the necessary routines Pin0Stuff() and Pin7Stuff(). Now translate that code into SDS compatible 68K-assembly code. Explain how the “C” differs from the Waiting Code you wrote in part A)

6 marks

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Setting the scene. One thing that was missing from Laboratory 3 was a method of handling a “Police Car” or “Ambulance” coming up to the traffic lights under “emergency” conditions. This situation would trigger an interrupt service routine (ISR) void HandleEmergency_ISR(void) which would turn all the lights to RED. In this question you are asked to write such an interrupt service routine Assume that the interrupt vector has already been set and that the interrupts are already activated. Assume that the traffic lights have already been RESET and are in use. There is no need to remember the current state of the lights – meaning turn every light RED regardless You are provided with the subroutine void ActivateLights(char *pt, short int whichcorner, short int whichlights)

from Laboratory 3. Information on the light and corner definitions are available in a file “traffdev.h”. See EXTRA PAGE 5 HINT: Rather than writing the same code again and again, when you get to the third and fourth corner simply state

– code is equivalent to the previous code sections

D) You will need to use a pointer inside the ISR. In 1 or 2 lines explain why must you hard code this information rather than making using of an interrupt service routine of the form void HandleEmergency_ISR(char *pt)?

2 marks

E) On the right hand side of the page write the “C” code for the ISR void HandleEmergency_ISR(void). Now translate that code into SDS compatible 68K-assembly code. HINT: My “C” code answer contains about 10 lines of code.

8 marks

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Q6) Don’t you just hate it when you have done research beyond the course content because that area interested you you have heavily reviewed one area you thought the instructor kept on deliberately emphasizing

and then the examiner does not ask any questions in that area! As promised, here is a chance to overcome that problem.

Make up a question related to this course AND answer it. (20 marks)

TO RECEIVE FULL MARKS the question should satisfy the following criteria Be at a difficulty level appropriate for a final exam question in the 3rd year of an Electrical and Computer

Engineering program. Quick test -- Would it be suitable for next year’s final? The question should NOT be equivalent to any exam question already asked in this course or the current exam. Questions and answers that are a simple regurgitation of a concept handled in class will receive a D grade

(around 6 -- 8 marks). Questions and answers that give a new insight into a concept handled in class will receive a C or a B grade (11 – 14 marks). Questions that, under different circumstances, would present A CHALLENGE FOR YOU to answer in either Section A or Section B of a final exam will receive B or A grade (14 and up), if answered correctly. A good mark on this question would be 15 or 16 marks out of 20

Students who have spend time ahead of the exam planning questions that lead to answers that are clear and concise are more likely to receive higher marks. This means I don’t like marking long-winded answers that look like they have been thought up on the spur of the moment. Please bring the questions and answers into the exam in your head as no additional materials are allowed in this exam!

Marking exams is normally as much fun as watching paint dry. Questions that entertain me and leave me thinking – that’s clever and well thought out – or leave me wanting to boast to other instructors about what you suggested -- are more likely to receive higher marks.

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EXTRA PAGE ---- IN-CASE YOU NEED IT FOR A LONG ANSWER

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Performance Analysis Sheet – Maximum Bonus Marks 5%

FINAL EXAM FOR DEFERRED FINAL ENEL415, JANUARY 2000

NAME:- ID#:-

Good software engineers keep track of their progress and can estimate their success. In the table below, indicate questions attempted and your estimate of how well you have answered the question.

For each estimate that matches the mark you actually receive, you will receive a bonus mark to make up for the time lost answering this section -- Maximum bonus 5 marks

MARK RANGES ARE A > 15 > B > 13 > C > 11 > D > 8 > FMAXIMUM

MARK YOUR ESTIMATE OF YOUR PERFORMANCE

ATTEMPT ALL QUESTIONS FROM SECTION A

SECTION A Q1 20 Circle your expected mark on this questionA > 15 > B > 13 > C > 11 > D > 8 > F

General KnowledgeInstructions and Stack Operations

SECTION A Q2 20Circle your expected mark on this question

A > 15 > B > 13 > C > 11 > D > 8 > F General Knowledge and MIPS

SECTION A Q3 20 Circle your expected mark on this questionA > 15 > B > 13 > C > 11 > D > 8 > F

Basic ISR and PIT operations

ATTEMPT ANY TWO QUESTIONS FROM SECTION B – IF YOU ATTEMPT THREE, THE THIRD WILL BE IGNORED SECTION B QUESTIONS ARE INTENDED TO BE SIGNIFICANTLY MORE DIFFICULT THAN SECTION A QUESTIONS

SECTION B Q4 20 Circle your expected mark on this questionA > 15 > B > 13 > C > 11 > D > 8 > F

ISR and PIT operations (Labs. 4/5)“C/C++” and 68K knowledge

SECTION B Q5 20Circle your expected mark on this questionA > 15 > B > 13 > C > 11 > D > 8 > F Concepts from Labs 3 and 5

SECTION B Q6 20 Circle your expected mark on this questionA > 15 > B > 13 > C > 11 > D > 8 > F Write your own question

YOUR ESTIMATE OF YOUR FINAL MARK -- OUT OF 100

Process management component of the exam1 Mark bonus if prediction of mark on a question is accurate to +-1 (estimates of unanswered questions excluded)2 Mark bonus if prediction of final mark on quiz is accurate to +-3

Maximum of 5 Bonus marks

To give you an idea of what I would consider the relative difficulties of the questions here are my expected Class Averages if everybody in the class attempted a particular question.SECTION A Q1 -- B / B+ Q2 – C/ C+ Q3 – C+ / B-SECTION B Q4 -- C-/ C Q6 – C+ / B- Q7 – C+ / B-

Planned exam mark average in the range 68% -- 70% (C+ / B-). Add to this the Bonus marks gained (average 3) for knowing what questions you did well and what questions you did poorly will give you 71% -- 73% (B- / B / B+)

Question 4 is actually straight forward, but most students will not tackle the question carefully enoughEXTRA PAGE 1 of 5

Figure 1 – needed for Section A Question 1

Here are the PI/T register names needed in questions 3 and 4

// pitnames.h

// The following are the definition for major register offsets MC68230 PIT// We are using label names from Clements// Offsets are different as lowest line on board is A4 and on Clements A1#define PGCR 0x0000 // Port general control register R/W#define PSRR 0x0010 // Port service request register R/W#define PADDR 0x0020 // Port A data direction register R/W#define PBDDR 0x0030 // Port B data direction register R/W#define PCDDR 0x0040 // Port C data direction register R/W#define PIVR 0x0050 // Port interrupt vector register R/W#define PACR 0x0060 // Port A control register R/W#define PBCR 0x0070 // Port B control register R/W

#define PADR 0x0080 // Port A data register R/W#define PBDR 0x0090 // Port B data register R/W#define PAAR 0x00A0 // Port A alternate register R#define PBAR 0x00B0 // Port B alternate register R#define PCCR 0x00C0 // Port C control register R/W// Can't use PSR as "as68000" claims that it is reserved word.#define PIT_PSR 0x00D0 // Port Status register R/W

EXTRA PAGE 2 OF 5

Figure 2 -- PI/T Register Information

Table 1A -- PACR information (PBCR equivalent)

Table 1B -- Submode 1X information

EXTRA PAGE 3 OF 5

Table 1C -- PGCR register information

Figure 2 – needed for Question 4

In this question, the CLOCK line is hooked up to the H4 line of the PI/T and is to be used to cause an interrupt each time the clock line goes from HI to LOW.

The red sensor line is hooked up to the H2 line of the PI/T and is used to cause an interrupt each time the red sensor line goes from HI to LOW.

The clock interrupt will occur about 2000 – 5000 times more often than the red sensor interrupt

EXTRA PAGE 4 OF 5