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Transcript of 19 FPGA
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19 FPGAPage 1
ECEn 224 © 2003-2008BYU
Field Programmable Gate Array
FPGA
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ECEn 224 © 2003-2008BYU
Using ROM as Combinational Logic
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 01 1 1 1
B
CA
C
F
8 x 1ROM(LUT)
A
B
C
F
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ECEn 224 © 2003-2008BYU
Mapping Larger Functions To ROMsA B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 00 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
B
C
D
F
LUT(B+C)
LUT
(CD)
B
C
D
LUTA’f1 + Af2
A
f1
f2
Very similar to how we decomposed functions toimplement with MUX blocks…
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ROM vs. LUT
• A ROM can be used as a lookup table (LUT)
• An FPGA contains many, many such LUTs– Possibly hundreds of thousands
• A 3LUT has 3 inputs and 1 output• A 4LUT has 4 inputs and 1 output
• 4LUTs are the most common…
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3LUT #1
Mapping a Gate Network to 3LUTs
3LUT #2
3LUT #3
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4LUT #1
Mapping Same Network to 4LUTs
4LUT #2
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ECEn 224 © 2003-2008BYU
Mapping Equations to LUTs
• How many 4LUTs do the following functions
require?F = aF = abcd
F = a’b’c’d + a’bcd’ + a’b’c’d’ + a’b’cdF = a + b + c + dF = (a +b + c + d)(a’ + b’ + c’ + d’)
• Each equation requires a single 4LUT!Number of LUTs isn’t a function of equation complexity,
but a function of number of unique inputs
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FPGAs – What Are They?
I/O Buffers
I/O Buffers
I / O B u f f e r s
I / O B u f f e r s
Programmable wiring areas
Programmable Logic Elements(LEs)
An FPGA is a Programmable Logic Device (PLD)It can be programmed to perform any function desired.
I/O Buffers communicatebetween FPGA andthe outside world
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Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inA
inB
inC
inD
out
clk
16
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Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inA
inB
inC
inD
out
clk
16
Black dots indicate programming bits(configuration bits)
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ECEn 224 © 2003-2008BYU
Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inA
inB
inC
inD
out
clk
16
On power up, configuration bits are loaded into FPGAThis customizes its operation (LUT function, MUX selection)
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ECEn 224 © 2003-2008BYU
Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inA
inB
inC
inD
out
clk
16
Typically, configuration bits are not changed during circuit operation(but, some FPGA’s are dynamically reconfigurable )
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One Configuration
4LUT
0
1
0
1
D Q
inA
inB
inC
inD
inE
outR = reg(inB(inC+inD))
clk16
fn=inB(inC+inD)
=1
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Yet Another Configuration
4LUT
0
1
0
1
D Q
inA
inB
inC
inD
inE
outR = reg(inC’)
outC = inC’
clk16
fn=inC’
=1
=1
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ECEn 224 © 2003-2008BYU
An FPGA Architecture (Island Style)
R o w w
i r e
s
Column WiresLogic Elements
Each LE is configured to do a function
Wire intersections are programmed to either connect or not
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Programmable Interconnect Junction
Row wire
Column wire
=1 ON
OFF =0
Connected
Unconnected
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Example Problem
ZD0-D5 ND5 Z’
N’P
• Generate the N, Z, P status flags for a 6-bit
microprocessor
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Example Problem
ZD0-D5 ND5 Z’
N’P
• Generate the N, Z, P status flags for a 6-bit
microprocessor
Will require 2 4LUTsCan be done with
wiring only orwith 1 4LUT
Will require 1 4LUT
N
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6
11
7
12
8
13
9
14
10
15
1 2 3 4 5D0D1
D2
D3D4D5
Z
P
N
LUT #1: F1 = D0’• D1’• D2’• D3’ LUT #8: F3 = D5 N outputLUT #7: F2 = F1•D4’•D5’ Z output LUT #9: F4 = Z’ • N’ P output
N
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6
11
7
12
8
13
9
14
10
15
1 2 3 4 5D0D1
D2
D3D4D5
P
N
LUT #1: F1 = D0’• D1’• D2’• D3’ LUT #8: F3 = D5 N outputLUT #7: F2 = F1•D4’•D5’ Z output LUT #9: F4 = Z’ • N’ P output
Z
N
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6
11
7
12
8
13
9
14
10
15
1 2 3 4 5D0D1
D2
D3D4D5
P
N
LUT #1: F1 = D0’• D1’• D2’• D3’ LUT #8: F3 = D5 N outputLUT #7: F2 = F1•D4’•D5’ Z output LUT #9: F4 = Z’ • N’ P output
Z
N
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6
11
7
12
8
13
9
14
10
15
1 2 3 4 5D0D1
D2
D3D4D5
P
N
LUT #1: F1 = D0’• D1’• D2’• D3’ LUT #8: F3 = D5 N outputLUT #7: F2 = F1•D4’•D5’ Z output LUT #9: F4 = Z’ • N’ P output
Z
N
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6
11
7
12
8
13
9
14
10
15
1 2 3 4 5D0D1
D2
D3D4D5
P
LUT #1: F1 = D0’• D1’• D2’• D3’ LUT #8: F3 = D5 N outputLUT #7: F2 = F1•D4’•D5’ Z output LUT #9: F4 = Z’ • N’ P output
Z
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Configuring an FPGA
• Most FPGAs have a configuration input pin
– Configuration bits are shifted into FPGA usingthis pin, one bit per cycle
– Configuration bits in FPGA linked into a long
shift register (SIPO)
• Examples on following slides are conceptual
– Commercial devices slightly different
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Structure of a 3LUT
ConfigurationStorage
Bits(Flip Flops)
LUT Output
LUT Inputs
b0
b1b2
b3
b4
b5b6
b7
3
It’s just an 8:1 MUX
LUT inputs select which config
bit is sent to LUT output
Programming LUT functionsetting configuration bits
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How are the Configuration Bit
Flip Flops Loaded?
D Q B70
1
CCLKCONFIG
D Q B60
1
CCLKCONFIG
…
…A serial-in/parallel-out(SIPO) shift register
These are the configuration bitswhich the LUT selects from
f h bl
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Configuring the Programmable
Interconnect
Row wire
Column wire
Configuration bit
b
Also arranged in aSIPO shift register
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Additional FPGA Features
Found in commercial FPGAs
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Configurable Input/Output
• I/O blocks allow internal FPGA signals to connect to external pins• Configurable I/O block features:
– Can be configured as inputs or outputs– Electrostatic discharge (ESD) protection– Input signal conditioning (voltage levels, …)– Output drive
• Fast, slow
• Strong, weak• Tri-state– Handles a variety of electrical standards
• LVTTL• LVCMOS
• PCI• LVDS• …
• I/O blocks are configured when the rest of the chip is configured
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Configuration Storage
• Actual configuration storage is not flip flops
– Many use SRAM memory cells• Different technologies
– Program once
• Fuse, anti-fuse configuration– Program multiple times
• SRAM-based configuration
• Some chips can be partially reconfigured ,even while rest of chip is running
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Programmable Interconnections
• Expensive to put programmable connections at
every wire junction– Commercial parts use partially populated junctions
– Little or no loss of routing flexibility
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Hierarchical Routing
• Collection of short, medium, and long wires
– Both rows and columns• Signals use wires that go distance needed
• CAD tools make determinations
• Like alleys, streets, expressways in a city– Longer distance more limited access points
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Clustered LE’s
• Cluster: >= 1 LE
– Example: Cluster of 4– Dedicated wires within groups of 4 LE’s
• Closely related to hierarchical routing
• Higher performance• Different vendors different clustering
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Embedded Function Units
• Place the following into the FPGA fabric:
MultipliersMemories (Block RAM)I/O interfaces (e.g. gigabit serial links or
Ethernet PHY/MAC)CPU’s (PowerPC, ARM, …)
• Result: higher speed, higher density, lowerpower designs
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FPGAs Compared To OtherTechnologies
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Performance vs. Flexibility
F l e x i b i
l i t y
Performance
ASICs
CPUs & DSPs
FPGAs
Goal: the performance of ASIC’s with theflexibility of programmable processors.
ASIC = Application SpecificIntegrated Circuit
FPGAs vs CPUs
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FPGAs vs. CPUs
Flexibility• Any function can be programmed to run on a CPU
– Programming is relatively simple to do
• Any function can also be configured onto an FPGA– Design is much more difficult and time consuming since
it’s a digital logic design
– “Hardware is harder than software”• Both CPUs and FPGAs can be reprogrammed
(reconfigured) in the field
• The winner: CPUs
FPGAs vs CPUs
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FPGAs vs. CPUs
Performance• 10+ years of research 10x-100x performance
advantage for FPGAs!
• Custom hardware– No fetch, decode, or memory access overhead– Significant parallelism (e.g., pipelining)
• Case in point: 1998 SONAR beamformer on an FPGA– BYU Configurable Computing Lab research– 2 x 109 FLOP/sec sustained – 10x-80x faster than comparable CPU technology
• The winner: FPGAs
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FPGAs vs ASICs
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FPGAs vs. ASICs
Performance• Both ASICs and FPGAs are custom hardware designs• FPGA configurability comes at great cost
– FPGA density is much lower than that of an ASIC– Low density means logic must be physically spread out
• Result:– FPGAs are slower, physically larger, and more power
hungry than a custom ASIC chip– For some/many applications FPGAs may…
• …be too slow• ...not hold enough logic
• …be too power hungry
• The winner: ASICs
FPGAs vs ASICs
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FPGAs vs. ASICs
Cost• Once the design is complete:
– FPGAs can be purchased off-the-shelf and programmed
in seconds• Negligible up-front costs• Inexpensive for small volume• Per part cost is high
– ASICs require time-consuming, expensivemanufacturing process• Fabrication facility (> $1 billion)• Significant up-front costs• Expensive for small volume• Per part cost is very low, when volume is high
• The winner: Depends on volume and application!
FPGA ASIC P d ti C t E l
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FPGA vs. ASIC Production Cost Example
• FPGA– Non-recurring
engineering (NRE)costs = $0– Per-part cost = $20
(prices vary from a
few $’s to $1000’s)
– Cost to produce 100 =$2K
– Cost to produce 106 =$20M
• ASIC– NRE costs = $5M
– Per-part cost = $1
– Cost to produce 100 =$5M + $100 ≈ $5M
– Cost to produce 106 =$5M + $1M = $6M
Volume produced makes a big difference!
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FPGA ASIC S
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FPGAs vs. ASICs - Summary
• Two very different technologies– Flexibility: FPGA wins
– Performance: ASIC wins– Risk: ?– Cost: ?
• Complex Decision– Only partially based on technical issues– Significant business issues
• Cost• Risk• Time-to-market• Market characteristics (elasticity, price sensitivity, …)
D si n f FPGAs
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Design for FPGAs
1. Draw schematics or write HDL
2. CAD tool maps design to LUTs + FFs
3. CAD tool generates bitstream
4. Load bitstream to configure the FPGA
Design for ASICs
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Design for ASICs
1. Draw schematics or write HDL
2. CAD tool maps design to physical siliconlayout
3. Send layout data to silicon fab
4. Finished chip does intended function
• Step 1 fairly similar for FPGAs and ASICs– Major differences in later steps
For More Information
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For More Information
• FPGA companies’ WWW sites tend to havelots of information– Catering to a wide range of customers
• Novice to expert
• Low volume to high volume– Data sheets
– Application notes
– Success stories– CAD tools