16 Bit Micro Processor

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TRAINIG REPORT

ON

SIMULATION OF 16 BIT MICROPROCESSOR

USING VHDL

Submitted in partial fulfillment of the

Requirements for the award of the degree

Of

BACHOLOR OF TECHNOLOGY

IN

ELECTRONICS & COMMUNICATION ENGINEERING

OF

U.P. Technical University , Lucknow

BY

Abhinav Khandelwal

DEPARTMANT OF ELECTRONICS & COMMUNCATION

ENGINEERING

G.L.A. Institute of Technology & Management,Mathura-281001

June, 2010


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ACKNOWLEDGEMENTS

It is my pleasure to acknowledge the assistance of a number of people

without whose help this project would not have been possible.

First and foremost, I would like to express our gratitude to Mr. VIKAS

KALRA my project guide, for providing invaluable encouragement,

guidance and assistance.

I would like to thank the computer center staff for the operation

extended to me throughout the project. After doing this project I can

confidently say that this experience has not only enriched me with

technical knowledge but also has unparsed the maturity of thought and

vision. The attributes required being a successful professional.

-------ABHINAV KHANDELWAL


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Dedi ed to My

Beloved Parents for

Giving me the Precious

Gift of

Education


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CETPA Profile

CETPA is the mission, which is working for the promotion of computer

education and technology in India and abroad. We are the group of

professionals who are united together and working for the promotion of

technology. The acronym of CETPA is COMPUTER EDUCATION AND

TECHNOLOGY PROMOTION ASSOCIATION. CETPA provide open

platform for the development of the various computer software. We are the

part of Linux Promotion Organization. And also we conduct Training

Programs for professionals and engineering students. Recently we have raised

our new branch CETPA INFOTECH PVT. LTD. at Greater Noida, which is

working towards the development of software, high level applications and

embedded system products in conjunction with our premier goal, that ispromotion of technology such as .NET, VHDL, Embedded System, Adv.

Embedded System, Catia, Matlab, Java, J2EE, J2ME, Autocad, C & C++,

Software Testing, Linux, Unix and many more. Our vision is to be world

class service providers and offering training in almost every field of

engineering to build bright careers of bright brains. CETPA is dedicated for

innovation with contribution, trust, respect, teamwork and uncompromising

integrity. We also thrive on speed, focus, and accountability. Every day, at all

levels, our endeavor is to create an environment where each individual is

included and valued.

CETPABecause Knowledge Matters ISO 9001: 2000

Certified


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Abstract

VHDL is a programming language that allows one to model and develop

complex digital systems in a dynamic environment. VHDL is an acronym for

very high-speed integrated circuit hardware description language. It is a

general-purpose hardware description language that is specifically designed to

describe the organization and function of digital hardware system, circuit

boards & components at many level of abstraction ranging from simple gate

to complete digital electronics systems. VHDL model is a textual description

of a hardware design or a piece of design that, when simulated mimics the

design behavior. The requirement for the language were first generated in

1980, under the Very High Speed Integrated Circuit (VHSIC) project of US

government, to enhance the electronic design process, technology, and procurement, spawning development of many advanced integrated circui t

process technologies.

16 bit microprocessor:

The processor contains a number of basic pieces. There is a register array of

8 16 bit register , an ALU . a shifter, a program counter , an instruction

register , a comparator, an address register and control unit. All of these units

communicate through a common 16 bit tri state data base.


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INDEX

y VHDL DESIGN FLOW .08

y INITIAL DESIGN ENTRY.10

y WHAT IS VHDL?10

y HISTORY.10

y CAPABALITIES OF VHDL11

y ADVANTAGES OF VHDL OVER PROCEDURAL LANGUAGES13

y THE VHDL DESIGN HIERARCHY...13

y ENTITY DECLARATION....15

y ARCHITECTURE BODY....16

y DATA FLOW STYLE ..16

y BEHAVIORAL STYLE ...17

y STRUCTURAL STYLE17

y CONSTANTS. ..18

y CONTANTS DECLARATION....18y VARIABLES 18

y BASIC TERMINOLOGY ....19

y ENTITY DECLARATION...19

y ARCHITECTURE DECLARATION...20

y CONFIGURATION DECLARATION....21

y PACKAGE DECLARATION..21

y PACKAGE BODY...21

y DESIGN DESCRIPTION METHODS22a. STRUCTURAL STYLE OF MODELLING..22

b. DATA FLOW STYLE OF MODELLING.....23

c. BEHAVIORAL STYLE OF MODELLING..24d. MIXED STYLE OF MODELLING...25

y DATA TYPES...26

y FPGA.37

y 16 BIT MICROPROCESSOR.39

y CPU DESIGN...39

y SYSTEM OPERATIONS AND INTERACTION BETWEEN DIFFERENTUNITS...39

y INSTRUCTIONS.41

y SAMPLE INSTRUCTION REPRESTION.....41

y OPCODE TABLE42

y

TOP LEVEL DESIGN.421. CPU LIBRARY...43

y SYNTHESIS....431. CPU..442. ALU..463. COMP...464. SHIFT UNIT.465. REG.....466. REG ARRAY..46


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7. CONTROL UNIT..50

y WAVEFORMS FOR ALL COMPONENTS.55

y CONCLUSION..57

y FUTURE PROSPECTS..58

y REFERENCES...58


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VHDL DE IGN FL

Fig. Design flow of an Integrated Circuit

Initial Design Entry

Logic Optimization

Technology Mapping

Programming Unit

Placement

Routing

Configured FPGA


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The starting point of design process is the initiallogic entry of the circuit that

is to be implemented. The step typically involves drawing a schematic capture

program, entering a VHDL description, or specifying Boolean expressions.

Regardless of the initial design entry, the circuit description is usuallytranslated into a standard form such as Boolean expressions. The Boolean

expressions are then processed by a logic optimization tools which

manipulate the expressions. The goal is to modify these expressions to

optimize the area or speed of the final circuit .A combination of both area and

delay requirements may also be considered. This optimization usually

performs the equivalent of an algebraic minimization of the Boolean

expressions and it is appropriate when implementing a logic circuit in any

medium, not just FPGAs.

The optimized Boolean expression must next be transformed into a circuit of

FPGA logic blocks. A technology-mapping program does this. The mapper

may attempt to minimize the total number of blocks required, which is known

as area optimization. Alternatively, the objective may be to minimize the

number of stages of logic blocks in time-critical paths, which is called delay

optimization.

Having mapped the circuit into logic blocks, it is necessary to decide where to

place each block in the FPGAs array. A placementprogram is used to solve

this problem. Typical placement algorithm attempt to minimize the total

length of interconnect required for the resulting placement.

The final step in the CAD system is performed by the routing software,

which assigns the FPGA wire segment and chooses programmable switches

to establish the required connection among the logic blocks .The routing

software must ensure that 100 percent of the required connections are formed,

otherwise the circuit cannot be realized in a single FPGA. Moreover it is often

necessary to do the routing such that the propagation delays in time-critical

connections are minimized.

Upon successful completion of the placement and routing steps, the CADsystems output is fed to a programming unit, which configures the final

FPGA chip.

The entire process of implementing a circuit in an FPGA can take from a few

minutes to about an hour, depending on which FPGA is being used.


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INITIAL DE IGNENT

As integrated circuit technology has improved to allow more and more

components on a chip, digital systems have continued to grow in complexity.

As digital systems have become more complex, detailed design of the systems

at the gate and flop-flop level has become very tedious and time consuming.

For this reason, use of hardware languages in the digital design process

continues to grow importance. A hardware description language allows a

digital system to be designed and debugged at a higher level bef ore

conversion to the gate and flip flop level. Use of synthesis computer aided

design tools to do this conversion is becoming more widespread. This is

analogous to writing software programs in high-level languages such as C and

then using a compiler to convert the programs to machine language. The two

most popular hardware description languages are VHDL and Verilog.

WHATIS VHDL?

VHDL is an acronym for very high-speed integrated circuit hardware

description language. It is a general-purpose hardware description language

that is specifically designed to describe the organization and function of

digital hardware system, circuit boards & components at many level of

abstraction ranging from simple gate to complete digital electronics systems.

VHDL model is a textual description of a hardware design or a piece ofdesign that, when simulated mimics the design behavior.

HIST

The requirement for the language were first generated in 1980, under the Very

High Speed Integrated Circuit (VHSIC) project of US government, to

enhance the electronic design process, technology, and procurement,

spawning development of many advanced integrated circuit process

technologies. In this program, a number of US companies were involved in

the design of VHSIC chip for the Department of Defense (DOD), USA. Atthat time, most of the companies were using different HDL to describe and

developed their ICs. As a result different vender could not effectively

exchange design with one another. Thus a need for a standardized HDL for

the design, documentation and verification of digital system was generated. A

team of three of companies, IBM, TI & INTERMETRICS, developed a


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version of language. In 1986, VHDL was proposed as an IEEE standard. It

went through a number of revisions and changes until it was adopted as the

IEEE 1076 standard in December 1987.

CAPABILITES OF VHDL

The following are the major capabilities that VHDL provide along with the

feature that differentiate it from other Hardware Description languages.

1. The language can be used as an exchange medium between chip vender

and CAD tool users. Different chip venders can provide VHDL description of

their components to system designers. CAD tool users can use it to capture

the behavior of the design at a high level of abstrac tion for functional

simulation.

2. The language can also be used as a communication medium between

different CAD and CAM tools. For example a schematic capture program

may be used to generate a VHDL description for the design, which can be

used as an input to a simulation program.

3. The language supports hierarchy i.e. a digital system can be modeled as a

set of interconnected sub-components.

4. The language is not technology specific, but is capable of supporting

different technologies. It can support various hardware technologies: for

example - new logic types and new components may be defined; technology

specific attributes can be used. By being technology independent the same

model can be synthesized into different vendor libraries.

5. It supports both synchronous and asynchronous timing models.

6. It is an IEEE and ANSI STANDARD; therefore, models described in this

language are portable.


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7. The language supports three basic different description styles: structural,

data flow and behavioral. A design may be described in any combination of

these three descriptive styles.

8. It supports a wide range of abstraction level ranging from behavioral

description to very precise gate level descriptions. It does not however

support modeling at or below the transistor level. It allows a design to be

captured at a mixed level using a single coherent language.

9. Arbitrary large design can be modeled using the language, and there are no

limitations imposed by the language on the size of a design.

10. The language has element that make large -scale modeling easier, for

example component, functions, procedure, and packages.

11. Nominal propagation delays, min-max delay, setup and holding time and

spike detection can all be very naturally done in this language .

12. A model can, not only describe the functionality of a design but also the

information about the design itself in terms of user defined attributes such as

total area and speed.

13. A common language can be used to describe library components from

different vendors. Tools that understand VHDL models will have no difficulty

in reading models from a variety of venders since the languages is a standard.

14. Models written in this language can be verified by simulation, since

precise simulation semantics are defined for language construct.

15. The capability of defining new data types provides the power of describeand simulate a new design technique at a very high level of abstraction

without any concern the implementation details.

16.The language is publicly available and human readable.


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ADVANTAGES OF VHDL OVE PROCEDURAL

LANGUAGES

Main difference between VHDL and other programming languages like

C/C++ are

a) VHDL is a parallel language, while C/C++ are sequential languages. Each

statement occurring in VHDL is executed concurrently, while in C/C++ each

statement is executed sequentially and at its own turn. In VHDL explicit

constructs exist for explicit sequential steps.

b) VHDL is a strongly typed language. It doesnt allow any mismatching of

types, though type conversion is permitted.

c) VHDL allows use of explicit time delay, which isnt applicable in

procedural languages. In procedural languages the right hand side value is

assigned to the left hand side value as soon as the statement is executed. In

VHDL there is an advantage that the computed value can be assigned to a

signal after any time delay.

d) VHDL model cannot be implemented in real time application directly like

other procedural languages. It is simulated and synthesized using in bui lt

system clock.

THE VHDL DESIGN HIERARCHY

Any hardware design can be described in terms of its operation at different

levels of abstraction, from system through to logic gate. At each level of this

hierarchy the overall inputs and outputs remain the same but the functionality

of distinct sections become clearer. When the local inputs and outputs and the

function of a block are sufficiently defined, the hardware can be designed.

VHDL is capable of describing a well-defined hardware block at any level ofabstraction. A design entity is the VHDL representation of such a block and

can be considered to be at the top of the design hierarchy. Within the design

entity, the function of the hardware is often further decomposed by using

external and internal blocks.


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External blocks are other design entities that have been previously complied

and stored in a library. These types of blocks are generally referred to as

components. Each component can further extend the hierarchy by also using

external and internal blocks to describe its own function. The present designentity can also be thought of as external block.

Internal blocks are self-contained functional units that have explicitly defined

input and output signals. They therefore represent the next level down in the

hierarchy. Again, an internal block may contain external or other internal

blocks. The Block statement is used to create an internal block.

A design entity contains an entity declaration and an architecture body. Figure

below shows the organization of the VHDL design hierarchy and illustrates

the main elements of an architecture body. The port connections, enable

information to be passed between blocks and, at the top level, allow the

design entity to communicate with the external environment. A design entity

may contain any or all of the elements shown, in the diagram. It will always

have an entity declaration and architecture body at the top level.

DESINING ENTITY

Entity declaration

Architecture body

Component ConcurrentStatements

Component

Internal block

Internal

block


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EXTERNAL BLOCK

INTERNAL

BLOCK

Fig. Hierarchical organization of a VHDL design

ENTITY DECLARATION

The entity declaration is the interface between the external environment, such

as a top-level schematic, and the design. It is at the top of the design three for

every external block. Hence, it will usually contain a description of the inputs

to and outputs from the block in the form of a port statement. An entity

declaration without a port statement does not have any external connections.

The Generic statement can be used within the entity declaration to pass

timing, control or environmental data into the design unit. A component

declaration may also have a Generic statement. This information is useful

when simulating a design, but when synthesizing most of it is irrelevant.

Hence, the Generic statement usually only supports the declaration of integer

generics, which have a constant value and can therefore be substituted into theassociated design unit at compile time.

The syntax for entity declaration is as follows

Entity entity name is

[port (interface-signal-declaration);]

end [entity] [entity-name];

Architecture body

Entity declaration

component Concurrentstatements

component

Internalblock

Internalblock

Block statement

component

component

Concurrent

statement

Internal

block

Internalblock


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ARCHITECTUREBODY

The architecture body is used to specify the relationship between the inputs

and outputs declared in the entity. It therefore describes the actual function of

the hardware. Although each entity must be unique, several architectures can

be associated with one entity. This allows the function of a block to the

changed without changing its external structure.

The architecture body contains any number of concurrent statements

components and internal blocks are also of this type. These statements can be

considered to be executing asynchronously and completely independently of

each other. It is therefore crucial to understand how the relationships between

different concurrent statements are going to affect not only the behavior but

also the logical structure of the hardware that synthesis will produce.

Additionally, certain concurrent statements may contain a number of

sequentially executing statements. Such flexibility allows the architecture

body to be constructed using three possible language styles. Choosing a

particular approach does not limit the design to that one style. In fact, many

functional descriptions can be implemented in more than one style. In general,

a combination of two or all three styles is often required to obtain the most

compact and clear VHDL code.

DATAFLOW STYLE

Dataflow style architecture models the hardware in terms of the movement of

data Over continuous time between combinational logic components such as

adders, decoders and primitive logic gates. It describes the register-transfer

level behavior of a circuit. The language topics that are most relevant to the

dataflow style of architecture include the following:

Operators-logical, relational and mathematical;

Operator overloading;Concurrent assignment statements.

This style is not appropriate for the modeling of sequential logic. Instead, and

as its name suggests, it is best applied in the modeling of data driven elements

such as an arithmetic logic unit (ALU)


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BEHAVIORALSTYLE

The behavioral style architecture contains concurrent statem ents with sections

of sequential statements that describe the outputs of the circuit at a discrete

moment in time given particular inputs. While similar language constructs are

often found in dataflow and behavioral style architectures, only the latter

explicitly exhibit the notions of time and control. This style describes the

function of the circuit at the algorithmic level.

The aspects of VHDL that are most relevant to behavioral style architectures

include the following :

-Process statements and sensitivity lists;

-Sequential statements;

-Variables.

This architectural style is used to describe both sequential and combinational

circuits. Hence, it is a valuable design approach for finite state machines

(FSMs) or any control logic.

STRUCTURALSTYLE

A structural style architecture describes the circuit primarily in terms of

components. These may be drawn from libraries supplied by ASIC vendors,

modules that are purposely produced for this design or general, user definedmodules that are stored in a library created for a previous design. The choice

of whether to use vendor specific or generic/user-defined components is an

issue. An appropriate balance must be struck between the efficiency of the

optimization and technology mapping processes and the futu re flexibility of

the design.

The architecture body specific which components are contained in a design

and how they are interconnected. The main VHDL topics associated with

structural style architectures include the following:

Component declarations and instantiations;

Port mapping and signal interface lists;

Signals (for interconnection).


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A structural architecture is often used at the higher levels of a design to

enable a clear distinction to be made between the various functional units and

enable a hierarchical approach to be adopted in the design process.

CONSTANTS

A constant is an object with a static value of a given type. Once the value has

been assigned to a constant it cannot be changed. How a constant is

represented in the synthesized hardware will be determined by how it is used.

It will, of course, be encoded as a binary value when implemented in

hardware, but may be declared as any synthesize able type.

CONSTANT DECLARATION:

Constant identifier {, identifier}: subtype_ indication [: = static _

expression];-

Subtype_ indication: = type_ name | subtype_ nam e [constraint]

VARIABLES

A variable is an object of any synthesizes able type that can be used as

temporary storage within a VHDL description. Depending on where it is

declared, a variable can be shared between different concurrently executingstatements in architecture or can be local to one

.

The value stored in a variable can be freely read or updated, and as with other

programming languages, any modification is effective immediately.

A variable that is local to a process will be discarded and its value lost once

the execution of the process is completed. When the process is restarted the

variable will be declared again. It is useful for simulation to assign an intial

value to a variable when it is declared. If one is not assigned, a default valuewill be given. Such information is meaningless when design is synthesized

and will therefore be ignored. However, ensuring that variable and signals are

correctly initialized is an important issue when designing VHDL for

synthesis. Failure to assign a value to a variable before it is read will produce

unwanted feedback in a design. Refer to chapter 5 for further elaboration on


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this point.A value is assigned to a variable by using the variable assignment

symbol: =. Shared variables must be used with caution to ensure that

multiple assignments to the same variable in different processes are correctly

synchronized. There must be no possibility that two processes could beupdating the same variable concurrently. This can lead to a design with

unpredictable (non-deterministic) simulation and synthesis results.

Variable_ declaration: : =[Shared] variable identifier {, identifier} : subtype_

indication [: = expression];

BASICTERMONOLOGY

VHDL is a hardware description language that can be used to model a digital

system. The system can be as simple as a logic gate or as complex as a

complete electronic system .A hardware abstraction of this digital system is

called an ENTITY.

To describe entity, VHDL provides five different types of constructs, called

design units, they are:

1. Entity Declaration

2. Architecture declaration

3. Configuration declaration4. Package declaration

5. Package body

An entity is modeled using an entity declaration an at one architecture body .

The ENTITY declaration describes the external view of entity ; for exam .

The input and output signal names. The architecture body contains the

internal description of the entity. Each style of representative can be specified

in a different architectural body or mixed with I a single architecture body.

ENTITIESVHDL designs consists of entity & architecture pair ,which describes the

design I/O or interface &the architecture describes the content of design.

Together, entity & architecture pairs can be used as a complete designs

descriptions or as components in a hierarchical design or both . The syntax for

an entity declaration is as follows:


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Entity entity name is

[port (interface-signal-declaration);]

end [entity] [entity-name];The words entity ,is , port ,in ,ont& end are reserved words , which have

especial meaning to the VHDL complier . The items enclosed in optional. The

interfacesignal declaration has the following from

List-of-interface-signal: mode type [:=initial-value]

Modes are of following types

a) in mode: for input signals .

b) out mode : for output signals.

c) Inout mode: for bi-directional signals.

ARCHITECTURES

This part is to describe the internal details & the following function of the

hardware . The internal details can be in the form of interconnected

componets that represents structure of the entity , or as a set of concurrent or

sequential statements that represent the behavior of the entity . Each style of

representation can be specified in a different architectural body or mixed with

in a single architecture body.

en -

Associated with each entity is one or more architecture declaration of the

form

Architecture architecture-name ofentity-name is[declaration ]

begin

architecture body

end[architecture ][ architecture-name];

EntityArchitecture

EntityArchitectureModule1

EntityArchitectureModule2

EntityArchitectureModule n


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VHDL can be firmly abstracted in a few statement , which are capable of

describing a system internally , this are:

Process statement: This is basically meant for describing the behavior of a

system .Process itself is a concurrent but its body is executed sequentially . Itconsists of a sensitivity list &whenever one of the signals in the sensitivity list

changes , the sequential statements in the process body are executed I

sequence one time.

a) Concurrent statement: It is a brief process statement .If the behavior

is very simple then we can describe it in one stateme nt. These

statements are carried out at the same simulation time concurrently.

b) Conditional signal assignment: Some of the models described in the

VHDL are required to assign different values based on some

conditions .The uses the conditional statement.

c) Component instantiation: VHDL allows the use of a particular

model as a component directly to the system.

d) Case statement: Use to selects for execution one of several

alternative sequences of statements; the alternative is chosen based on

the value of the associated expression.

CON

FIGURAT

ION

A CONFIGURATION declaration is used to create a configuration for an

entity . It specifies the binding of one architecture body to other entities .

An entity may have any number of different configurations.

PACKAGE

A PACKAGE declaration encapsulates a set of related declaration , such

as type declaration , sub type declarations & subprogram declaration ,

which can be shared across two or more design units . A package body

contains the definitions of subprogram declared in a packagedeclarations.

Storage classes:

The storage classes in VHDL are-


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a) Signals : signals are the basic & most widely used storage classes in

VHDL. These are the type of storage elements through which all the

input & output takes place . The time at which the value changes in

them can be easily traced ,since the use the drivers , which records thetransactions.

b) Variables: Variable is used to store the temporary values &hold the

value only till the process is being used .The variables can only be u sed

in process is being used .The variables can only be used in progresses

&functions.

c) Constants : Constants are the storage elements , which acquire a

particular valve &their value cannot be changed during the execution.

DESIGN DESCRIPTION METHODS:

VHDL provides a textual method of describing a hardware design in

place of a schematic representation. The internal detail of an entity are

specified by an architectural body using any of the following modeling

styles :

1. As a set of interconnected components (to represents

structure).2. As a set of concurrent assignments statements (to represent

data-flow).

3. As a set of sequential assignment statements (to represents

behavior).

4. As any combination of above three.

STRUCTURALSTYLE OF MODELING :

In the structural style of modeling, an entity is described as a set of

interconnected components. Such a model for the HALF_ADDER entity isdescribed in an architecture body as shown below :

Architecture HA_ STRUCTURE of HALF ADDER is

component XOR2

Port (x,y : in bit ; z : out bit);

end component;


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component AND2

port (x, y: inbit ;z out bit);

end component;

beginX1 :XOR2 port map (A,B, SUM);

A1: AND2 port map (A,B,CARRY);

End HA_STRUCTURE;

The name of the architecture body is HA_STURCETURE . The enti ty

declaration for HALF_ADDER specifies the interface for this architecture

body the architecture body is composed of two parts: the declarative part and

the statement part. Two component declaration is present in the declarative

part of the architecture body. This declaration specifies the interface of the

component that is used in the architecture body. The components XOR2 and

AND2 may either be predefined components in libraries or if they do not

exist, they may later be bound to other component in a li brary. The declared

component is instantiated the statement part of the architecture body using

component instantiation statement. X` and A1 is the component label for this

component instantiation. The first component instantiation statement labeled

X1, shows the signal A and B (the input port of the HALF_ADDER) are

connected to the X and Y input port of he XOR2 component, while the output

port Z of this component is connected to output port SUM of the

HALF_ADDER entity.

Similarly in the second component instantiation statement signal A and B are

connected to port L and M of the AND2 component, while the port n is

connected to the carry port of the HALF_ADDER. The signals in the port

map of the component instantiation and the port signal in the component

declaration are associated by position (called positional association). The

structural representation for the HALF_ADDER does not say anything aboutits functionality.

DATA FLOW STYLE OF MODELLING:

In this style of modeling the flow of data through the ent ity is expressed

primarily using concurrent signal assignment statement. The structure of the


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entity is not explicitly specified in this modeling style, but in can be implicitly

deduced. Consider the following alternate architecture body for the

HALF_ADDER entity that uses this style.

Architecture HA CONCURRENT of HALF ADDER is

Begin

Sum


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Architectural DEC SEQUENTIAL of DECODER 2 X 4 is

Begin

process (A,B,ENABLE)

variable ABAR, BBAR :bit;begin

ABAR : =not A;

BBAR := not B;

if ENABLE = 1 then

Z (3) < = not (A and B);

Z (2) < = not (A and BBAR);

Z (1) < = not (ABAR AND B);

else Z < = 1111,

end if;

end process; end DEC SEQUENTIAL ;

A process statement also has a declarative part and statement part. The

statements appearing with in the statement part are sequential statement that is

executed sequentially. The list of signal specified within the parenthesis after

the word process constitutes a sensitivity list, which is invoked whenever

there is an event on any signal in this list.

The variable declaration declares two variables ABAR and BBAR. A variable

is different from a signal in that it is always assigned a value instantaneously

and the assignment operator used is the : = compound symbol; contrast with a

signal that is assigned a value always after a certain delay, and the

assignment operator used to assign a value to the signal is < = compound

signal. Variable declared with in a clause re confined in their scope to that

process: variable declared outside of a process or sub program are called

shared variables. Note that signal cannot be declared within a process.

MIXED STYLE OF MODELLING:

It is possible to mix the three modeling style that we have shown so far in a

signal architecture body. That is, within an architecture body, we could

component instantiation statement (that represents structure). Concurrent

signal assignment statement (that represent flow), and process statements


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(that represents behavior). Here is an example of a mixed style model for the

1-BIT FULL ADDER:

Entity FULL ADDER isport ( A, B, CIN : in bit; SUM, CAROUT : out bit);

generic (del :time = 10ns);

end FULL ADDER;

architecture FA MIXWD of FULL ADDER is

component XOR2

port(P1,P2 : in bit :PZ : out bit);

end component ;

signal S 1: bit;

begin

x1 : XOR2 port map (A, B,S1): - -structure

process (A,B,CIN) -- behavior

variable T1, T2, T3:BIT ;

begin

T1 = A and B

T2 : = B and CIN;

T3 : = A and CIN ;

CAROUT < = T1 or T2 ORT3

end process;

SUM < = S1 xor CIN;

end FA MIXED;

The full adder is implemented using one component instantiation statement,

one process statement, and one concurrent signal assignment statement. All of

these statements are concurrent assignment statements therefore their order

appearance within the architecture body is not important. S1 is a signal locally

declared within the architecture body and is used to pass the value from theout of the component x1 to the expression for signal SUM.

DATA TYPES

Each data object has a type associated with it. The t ype defines the set of

values that the object can have and the set of operations that are allowed on it.


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The notion oftype is key to VHDL since it is a strongly typed language that

requires each object to be of a certain type. In general one is not allowe d to

assign a value of one type to an object of another data type (e.g. assigning an

integer to a bit type is not allowed). There are four classes of data types:scalar, composite, access and file types. The scalar types represent a single

value and are ordered so that relational operations can be performed on them.

The scalar type includes integer, real, and enumerated types of Boolean and

Character. Examples of these will be given further on.

a. Data Types defined in the Standard Package

VHDL has several predefined types in the standardpackage as shown in thetable below. To use this package one has to include the following clause:

Types defined in the Package Standard of the stdLibrary

Type Range of values Example

Bit 0, 1 signal A: bit :=1;

bit_vector an array with each element

of type bit

signal INBUS: bit_vector(7

downto 0);

Boolean FALSE, TRUE variable TEST: Boolean:=FALSE

Character any legal VHDL character

(see package standard);

printable characters must

be placed between single

quotes (e.g. #)

variable VAL: character

:=$;

file_open_kind* read_mode, write_mode,

append_mode

file_open_status* open_ok, status_error,

name_error, mode_error

Integer range is implementation

dependent but includes at

least (231 1) to +(231

1)

constant CONST1: integer

:=129;


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Natural integer starting with 0 up

to the max specified in the

implementation

variable VAR1: natural :=2;

Positive integer starting from 1 upthe max specified in the

implementation

variable VAR2: positive :=2;

real* floating point number in

the range of 1.0 x 1038

to

+1.0x 1038 (can be

implementation dependent.

Not supported by the

Foundation synthesis

program.

variable VAR3: real

:=+64.2E12;

severity_level note, warning, error,

failure

String array of which each

element is of the type

character

variable VAR4: string(1 to

12):= @$#ABC*()_%Z ;

time* an integer number of

which the range is

implementation defined;units can be expressed in

sec, ms, us, ns, ps, fs, min

and hr. . Not supported by

the Foundation synthesis

program

variable DELAY: time :=5

ns;

* Not supported by the Foundation synthesis program

b. User-defined Types

One can introduce new types by using the type declaration, which names the

type and specifies its value range. The syntax is

type identifieris type_definition;


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Here are a few examples of type definitions,

Integer types

type small_intis range 0 to 1024;type my_word_length is range 31 downto 0;

subtype data_word is my_word_length range 7 downto 0;

A subtype is a subset of a previously defined type. The last example above

illustrates the use of subtypes. It defines a type called data_word that is a

sybtype of my_word_length of which the range is restricted from 7 to 0.

Another example of a subtype is,

subtype int_small is integerrange -1024 to +1024;

Floating-point types

type cmos_level is range 0.0 to 3.3;

type pmos_level is range -5.0 to 0.0;

type probability is range 0.0 to 1.0;

subtype cmos_low_V is cmos_level range 0.0 to +1.8;

Note that floating point data types are not supported by the Xilinx Foundation

synthesis program.

Physical types

The physical type definition includes a units identifier as follows,

type conductance is range 0 to 2E-9

unitsmho;

mmho = 1E-3 mho;

umho = 1E-6 mho;

nmho = 1E-9 mho;

pmho = 1E-12 mho;

end units conductance;


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Here are some object declarations that use the above types,

variable BUS_WIDTH: small_int :=24;signal DATA_BUS: my_word_length;

variable VAR1: cmos_level range 0.0 to 2.5;

constant LINE_COND: conductance:= 125 umho;

Notice that a space must be left before the unit name.

The physical data types are not supported by the Xilinx Foundation Express

synthesis program.

In order to use our own types, we need either to include the type definition

inside an architecture body or to declare the type in a package. The latter can

be done as follows for a package called my_types.

package my_types is

type small_intis range 0 to 1024;

type my_word_length is range 31 downto 0;

subtype data_word is my_word_length isrange 7 downto 0;

type cmos_level is range 0.0 to 3.3;

type conductance is range 0 to 2E-9

units

mho;

mmho = 1E-3 mho;

umho = 1E-6 mho;

nmho = 1E-9 mho;

pmho = 1E-12 mho;

end units conductance;end package my_types;

c. Enumerated Types


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An enumerated type consists of lists of character literals or identifiers. The

enumerated type can be very handy when writing models at an abstract level.

The syntax for an enumerated type is,

typetype_nameis (identifier listor character literal);

Here are some examples,

type my_3values is (0, 1, Z);

type PC_OPER is (load, store, add, sub, div, mult, shiftl, shiftr);

type hex_digit is (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,

E, F);

type state_type is (S0, S1, S2, S3);

Examples of objects that use the above types:

signal SIG1: my_3values;

variable ALU_OP: pc_oper;

variable first_digit: hex_digit :=0;

signal STATE: state_type :=S2;

If one does not initialize the signal, the default initialization is the leftmost

element of the list.

Enumerated types have to be defined in the architecture body or inside a

package as shown in the section above.

An example of an enumerated type that has been defined in the

std_logic_1164 package is the std_ulogic type, defined as follows

type STD_ULOGIC is (

U, -- uninitialized

X, -- forcing unknown

0, -- forcing 0

1, -- forcing 1

Z, -- high impedance


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W, -- weak unknown

L, -- weak 0

H. -- weak 1

-); -- dont care

In order to use this type one has to include the clause before each entity

declaration.

library ieee; use ieee.std_logic_1164. all;

It is possible that multiple drivers are driving a signal. In that case there could

be a conflict and the output signal would be undetermined. For instance, the

outputs of an AND gate and NOT gate are connected together into the output

net OUT1. In order to resolve the value of the output, one can call up a

resolution function. These are usually a user-written function that will resolve

the signal. If the signal is of the type std_ulogic and has multiple drivers, one

needs to use a resolution function. The std_logic_1164 package has such a

resolution function, called RESOLVED predefined. One can then use the

following declaration for signal OUT1

signal OUT1: resolved: std_ulogic;

If there is contention, the RESOLVED function will be used to intermediate

the conflict and determine the value of the signal. Alternatively, one can

declare the signal directly as a std_logic type since the subtype std_logic has

been defined in the std_logic_1164 package.

signal OUT1: std_logic;

d.Composite Types: Array and Record

Composite data objects consist of a collection of related data elements in the

form of an array orrecord. Before we can use such objects one has to declare

the composite type first.


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Array Type

An array type is declared as follows:

typearray_nameis array (indexingscheme)ofelement_type;

type MY_WORD is array (15 downto 0) ofstd_logic;

type YOUR_WORD is array (0 to 15) ofstd_logic;

type VARis array (0 to 7) ofinteger;

type STD_LOGIC_1Dis array (std_ulogic) ofstd_logic;

In the first two examples above we have defined a one-dimensional array of

elements of the type std_logic indexed from 15 down to 0, and 0 up to 15,

respectively. The last example defines a one-dimensional array of the type

std_logic elements that uses the type std_ulogic to define the index constraint.

Thus this array looks as follows:

Index: U X 0 1 Z W L H -

Element:

We can now declare objects of these data types. Some examples are given

signal MEM_ADDR: MY_WORD;

signal DATA_WORD: YOUR_WORD := B1101100101010110;

constant SETTING: VAR := (2,4,6,8,10,12,14,16);

In the first example, the signal MEM_ADDR is an array of 16 bits, initialized

to all 0s. To access individual elements of an array we specify the index. For

example, MEM_ACCR(15) accesses the left most bit of the array, while

DATA_WORD(15) accesses the right most bit of the array with value 0. Toaccess a subrange, one specifies the index range, MEM_ADDR(15 downto 8)

or DATA_WORD(0 to 7).

Multidimensional arrays can be declared as well by using a similar syntax as

above,


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type MY_MATRIX3X2 is array (1 to 3, 1 to 2) ofnatural;

type YOUR_MATRIX4X2 is array (1 to 4, 1 to 2) ofinteger;

type STD_LOGIC_2Dis array (std_ulogic, std_ulogic) ofstd_logic;

variable DATA_ARR: MY_MATRIX :=((0,2), (1,3), (4,6), (5,7));

The variable array DATA_ARR will then be initialized to,

0 2

1 3

4 6

5 7

To access an element one specifies the index, e.g. DATA_ARR(3,1) returns

the value 4.

The last example defines a 9x9 array or table with an index the elements of

the std_ulogic type.

Sometimes it is more convenient not to specify the dimension of the array

when the array type is declared. This is called an unconstrained array type.

The syntax for the array declaration is,

typearray_nameis array (typerange ) ofelement_type;

Some examples are

type MATRIX is array (integerrange ) of integer;

type VECTOR_INT is array (natural range ) of integer;

type VECTOR2 is array (natural range , natural range ) of

std_logic;

The range is now specified when one declares the array object,

variable MATRIX8: MATRIX (2 downto -8) := (3, 5, 1, 4, 7, 9, 12,

14, 20, 18);


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variable ARRAY3x2: VECTOR2 (1 to 4, 1 to 3)) := ((1,0), (0,-

), (1, Z));

Record TypeA second composite type is the records type. A record consists of multiple

elements that may be of different types. The syntax for a record type is the

following:

typenameis

record

identifier :subtype_indication;

:

identifier :subtype_indication;

end record;

As an example,

type MY_MODULE is

record

RISE_TIME :time;

FALL_TIME : time;

SIZE : integerrange 0 to 200;

DATA : bit_vector (15 downto 0);

end record;

signal A, B: MY_MODULE;

To access values or assign values to records, one can use one of the following

methods:

A.RISE_TIME


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e. Type Conversions

Since VHDL is a strongly typed language one cannot assign a value of one

data type to a signal of a different data type. In general, it is preferred to the

same data types for the signals in a design, such as std_logic (instead of a mix

of std_logic and bit types). Sometimes one cannot avoid using different types.

To allow assigning data between objects of different types, one needs to

convert one type to the other. Fortunately there are functions available in

several packages in the ieee library, such as the std_logic_1164 and the

std_logic_arith packages. As an example, the std_logic_1164 package allows

the following conversions:

Conversions supported by std_logic_1164 package

Conversion Function

std_ulogic to bit to_bit(expression)

std_logic_vector to bit_vector to_bitvector(expression)

std_ulogic_vector to bit_vector to_bitvector(expression)

bit to std_ulogic To_StdULogic(expression)

bit_vector to std_logic_vector To_StdLogicVector(expression)

bit_vector to std_ulogic_vector To_StdUlogicVector(expression)std_ulogic to std_logic_vector To_StdLogicVector(expression)

std_logic to std_ulogic_vector To_StdUlogicVector(expression)

The IEEE std_logic_unsigned and the IEEE std_logic_arith packages allow

additional conversions such as from an integer to std_logic_vector and vice

versa.

An example follows.

entity QUAD_NAND2 is

port (A, B: in bit_vector(3 downto 0);

out4: out std_logic_vector (3 downto 0));

end QUAD_NAND2;


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architecture behavioral_2 ofQUAD_NAND2 is

begin

out4


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Each of these techni es, however, requires extensive manufacturing effort,

taking sever al months from beginning to end. This results in a high cost until

large volumes are produced.

In electronics industry itis vitalto reach the marketin shortest possible timeand also itis importantthatthe financial riskincurred in the development of

the new product be limited.

Field-Programmable Gate arrays (FPGAs) have emerged as the ultimate

solution to these problems because they provide instant manufacturing and

low cost prototypes.


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16BIT MICROPROCESSOR

CPU Design

The example is a small 16 bit microprocessor. The processor contains a

number of basic pieces. There is a register array of 8 16 bit register , an ALU .

a shifter, a program counter , an instruction register , a comparator, an address

register and control unit. All of these units communicate through a common

16 bit tri state data base.

SYSTEM OPERATIONS AND INTERACTIONBETWEEN

DIFFERE

NT U

NITS

The top level design consist of the processor block and a m emory block

communicating through a bi-directional database, an address bus, and a few

control lines. The processor fetches instructions from the external memory

and executes these instructions to run a program. These instructions are stored

in the instruction register and decoded by the control unit.the control unit

causes the appropriate signal interaction to make the processor unit execute

the instruction.

If the instruction is an add of two registers, the control unit would cause thefirst register value to be written to register OpReg for temporary storage. The

second register value would then be placed on the data bus. The ALU would

be placed in add mode and the result would be stored in register OutReg.

Register OutReg would store the resulting value until it is copied to the final

destination.

When executing an instruction, a number of steps take place. The program

counter holds the address in memory of the current instruction. After an

instruction has finished execution, the program counter is adv anced to where

the next instruction is located. If the processor is executing a linear stream of

instructions, this is the next instruction. If a branch was taken, the program

counter is loaded with the next instruction location directly.


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Instrreg InstrselOpreg Opregsel

Compsel

Comparator

Progcounter Progsel ALU Alusel compout

Shiftsel

Shifter

Outreg Outsel

Register Regsel

(0 to 7) CONTROL

Addresreg Addrsel

Addr(15:0) Data(15:0) Clock Ready R/W VMA Reset

value to the address register, which outputs the new address on the address

bus.At the same time, the control unit sets the R/W (read write signals) to a

0 value for a read operation and sets signal VMA (Valid Memory Addre

-ss)to a 1, signaling the memory that the address is now valid. The

memory decodes the address and places the memory data on the data bus.

When the data has been placed the data bus, the memory has set the

READY signal to a 1 value indicating that the memory data is ready for

consumption.

The control unit causes the memory data to be written into the instruction

register. The control unit now has access to the instruction and decodes the

instruction. The decoded instruction executes, and process starts over again.


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INSTRUCTIONS

Instructions can be divided into a number of different types as follows:

Load these instructions load register values from other registers,

memory locations, or with immediate values given in the instruction.

Store -- these instructions store register values to memory location.

Branch -- these instructions cause the processor to go another location

in the instruction stream. Some branch instructions test values before

branching; others branch without testing.

ALU -- these instructions perform arithmetic and logical operations

such as ADD,SUBTRACT,OR,AND and NOT.

Shift-- these instructions use the shift unit to perform shift operations

on the data passed to it.

SAMPLEINSTRUCTION REPRESENTATION

All instruction contain the opcode in five most significant bits of the

instruction. Instruction are of two types

1. single word instructions

2. double word instruction

Single word instructions contain two 3 bit register fields in the lower 6 bitsof instruction some instruction such as increment ( INC) only use one of

the field but the other instruction such as MOV(move) use both register

fields.

Opcode Src Dst

15 14 13 12 11 5 4 3 2 1 0

In double word instructions, the firsrt word contains the immediate instruction

location or data value to be loaded. For instance a LoadI(Load immediate)instruction will look like this.

Opcode Dst

0 0 1 0 0 0 0 1


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LoadI

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 10 0 1 5

OPCODETABLE

OPCODE INSTRUCTION NOTE

00000 NOP No operation

00001 LOAD Load register

00010 STORE Store register00011 MOVE Move value to register

00100 LOADI Load register with

immediate value

00101 BRANCHI Branch to immediate

address

00110 INC Increment

00111 DEC Decrement

01000 AND AND two register

01001 OR OR two register01010 XOR XOR two register

01011 NOT NOT a register

01100 ADD Add two register

01101 SUB Subtract two register

01110 ZERO Zero a register

01111 SHL Shift left

10000 SHR Shift right

10001 ROTR Rotate right

10010 ROTL Rotate left

CPU TOP- LEVEL DESIGN

The next few sections contain the VHDL description for each of the CPU

components.


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< CPU_LIB>

library ieee;

use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;

package cpu_lib is

type t_shift is (shftpass,shl,shr,rotl,rotr);

subtype t_alu is unsigned(3 downto 0);

constant alupass : unsigned(3 downto 0):="0000";

constant andop : unsigned(3 downto 0):="0001";

constant orop : unsigned(3 downto 0):="0010";

constant notop : unsigned(3 downto 0):="0011";

constant xorop : unsigned(3 downto 0):="0100";

constant plus : unsigned(3 downto 0):="0101";

constant alusub : unsigned(3 downto 0):="0110";

constant inc : unsigned(3 downto 0):="0111";

constant dec : unsigned(3 downto 0):="1000";

constant zero : unsigned(3 downto 0):="1001";

type t_comp is(eq,neq,gt,lt,gte,lte);

subtype t_reg is std_logic_vector(2 downto 0);

type state is (reset1,reset2,reset3,reset4,reset5,reset6,

execute,nop,load,store,move,load2,load3,

load4,store2,store3,store4,move2,move3,

move4,incpc,incpc2,incpc3,incpc4,incpc5,

incpc6,loadpc,loadpc2,loadpc3,loadpc4,

bgti2,bgti3,bgti4,bgti5,bgti6,bgti7,bgti8,

bgti9,bgti10,brai2,brai3,brai4,brai5,brai6,

loadi2,loadi3,loadi4,loadi5,loadi6,inc2,

inc3,inc4);

subtype bit16 is std_logic_vector(15 downto 0);end cpu_lib;

CPU :SYNTHESIS DESCRIPTION

In this section we further refine the CPU description and examine the RTL

description of the CPU. The CPU is described by a number of lower-level

components that are instantiated to form the CPU design.


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At the top of the CPU design is an architecture that instantiates all of the

lower-level components to form the CPU.

library ieee;

use ieee.std_logic_1164.all;

use work.cpu_lib.all;

entity cpu is

port(clock,reset,ready: in std_logic;

addr: out bit16;

rw,vma : out std_logic;

data: inout bit16);end cpu;

architecture rtl of cpu is

component regarray

port (data: in bit16;

sel: in t_reg;

en,clk: in std_logic;

q: out bit16);

end component;

component reg

port(a: in bit16;

clk: in std_logic;

q: out bit16);

end component;

component trireg

port(a: in bit16;clk,en: in std_logic;

q: out bit16 );

end component;

component control


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port(clock,reset: in std_logic;

instrreg: in bit16 ;

compout,ready: in std_logic;

progcntrwr,progcntrrd,addrRegWr,outRegWr,outRegRd: out std_logic;shiftsel: out t_shift;

alusel: out t_alu;

compsel : out t_comp;

opRegRd,opRegWr,instrWr: out std_logic;

regsel:out t_reg;

regRd,regWr,rw,vma: out std_logic);

end component;

component alu

port(a,b: in bit16;

sel :in t_alu;

c: out bit16);

end component;

component shift

port(a: in bit16;

sel : in t_shift;

y: out bit16);

end component;

component comp

port(a,b : in bit16;

sel: in t_comp;

compout: out std_logic);

end component;

signal opdata,aluout,shiftout,instrregout: bit16;

signal regsel : t_reg;

signal regRd,regwr,opregrd,opregwr,outregrd,outregwr,addrregwr,

instrregwr,progcntrrd,progcntrwr,compout: std_logic;

signal alusel: t_alu;

signal shiftsel : t_shift;


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signal compsel : t_comp;

begin

ra1: regarray port map(data,regsel,regrd,regwr,data);

opreg: trireg port map(data,opregrd,opregwr,opdata);alu1: alu port map(data,opdata,alusel,aluout);

shift1 : shift port map(aluout,shiftsel,shiftout);

outreg: trireg port map(shiftout,outregrd,outregwr,data);

addrreg : reg port map(data,addrregwr,addr);

progcntr: trireg port map(data, progcntrrd,progcntrwr,data);

comp1 : comp port map (opdata,data,compsel,compout);

instr1: reg port map(data,instrregwr,instrregout);

con1: control port map(clock,reset,instrregout,compout,ready,

progcntrwr,progcntrrd,addrRegWr,outRegWr,outRegRd,shiftsel,

alusel,compsel,opRegRd,opRegWr,instrregWr,regsel,regRd,

regWr,rw,vma);

end rtl;

library

ieee;use

ieee.std_logic

_1164.all;

use

work.cpu_lib.

all;

use

ieee.std_logic_unsigned.all;

entity alu is

port (a,b: in

bit16;

sel :in

library

ieee;

use

ieee.std_lo

gic_1164.al

l;

use

ieee.std_lo

gic_arith.all;

use

work.cpu_l

ib.all;

entity comp

library ieee;

use

ieee.std_logi

c_1164.all;

use

work.cpu_li

b.all;

entity reg2 is

port(a: inbit16;

clk: in

std_logic;

q: out

bit16);

library

IEEE;

use

IEEE.std_l

ogic_1164.

all;

use

work.cpu_lib.all;

entity

regarray1 is

port(data:

in bit16;

library ieee;

use

ieee.std_logic_116

4.all;

use

work.cpu_lib.all;

entity shift is

port(a: in bit16;

sel: in t_shift;y: out bit16);

end shift;

architecture rtl of

shift is

begin


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t_alu;

c: out

bit16);

end alu;architecture

rtl of alu is

begin

aluproc:

process(a,b,se

l)

begin

case sel is

when

alupass =>

c

c

c

cc

c

if a=b

then

compout


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48

after 1 ns;

when

alusub =>

c

c

c

c

c


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compout

if a


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50

process;

end rtl;

y

NULL;end case;

end if;

end

process;

end

regarray_ar

ch;

STAGE-01 STAGE-02 STAGE-03

library ieee;

use ieee.std_logic_1164.all;

use work.cpu_lib.all;

entity control2 is

port(clock,reset: in

std_logic;

instrreg: in bit16 ;

compout,ready: in

std_logic;

progcntrwr,progcntrrd,addr

RegWr,addrregrd,outRegWr

,outRegRd: out std_logic;

shiftsel: out t_shift;

alusel: out t_alu;

next_state

vma


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compsel : out t_comp;

opRegRd,opRegWr,instrWr:

out std_logic;regsel:out t_reg;

regRd,regWr,rw,vma:

out std_logic);

end control2;

architecture rtl of control2 is

signal

current_state,next_state :

state;

begin

nxtstateproc:

process(current_state)

begin

progcntrwr


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shiftsel


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--load

regsel


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downto 3);

regrd


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55

WAVEFORMS FOR ALL COMPONENTS

ALU

COMPARATOR

CONTROL UNIT


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REGARRAY

SHIFT UNIT

REGISTER


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TRIREG

CPU

CONCLUSION

Each & every component is simulated individually, also cpu is simulated

using components. All the components and cpu shows good results.

Waveforms are shown in the report, which shows correct results.


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FUTURE PROSPECTS

Results VHDL One of the biggest job providing sector today, have a very

bright future in the coming time,but as the time is passing some other

languages are making control over designing, as for example Verilog

HDL Verilog HDLis a little bit better in processing speed than VHDL

But on the other hand VHDL is also better in some fields like, all the

three styles of modeling(Data flow, Behavioral, Structural) in VHDL can

be mixed together in the same program i e. VHDLis more user friendly

than Verilog HDL.

But today all over world mainly VHDLis used for chip designing at low

level. Till now there are number of drawbacks in VHDL. As main

drawback of VHDLis that, there are a number of features in VHDL, that

can be simulated but not synthesized. As, final shape to VHDL was given

by IEEE, hence IEEE is working on it continuously and trying to make

available simulation features to synthesis also.

So if talk about future prospectus of VHDL, it depends on success of

IEEE. IfIEEE got able to implement such features that there remain no

differences between simulation & synthesis with higher processing speed

and designing up to more lower level of abstraction, on that day VHDLmay take hold over all other HDL,s.

References

1. M. Mano and C. Kime, Logic and Computer Design Fundamentals, 2 nd

Edition, Prentice Hall, Upper Saddle River, 2001.

2. S. Yalamanchili, VHDL Starters Guide, Prentice Hall, Upper Saddle

River, 1998.

3. J. Bhasker, VHDL Primer, 3 rd Edition, Prentice Hall, Upper SaddleRiver, 1998.

4. Douglas L. Perry, VHDL Programming by Examples, 4th

Edition,

TMH.

5. C. H. Roth, Digital System Design using VHDL, PWS Publishing

Company, New York, 1998.


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