15EI205L -ANALOG AND DIGITAL INTEGRATED … · INTEGRATED CIRCUITS LAB ORATORY MANUAL ... OF THE...

1

15EI205L-ANALOG AND DIGITAL

INTEGRATED CIRCUITS LABORATORY

MANUAL

Department of Electronics and Instrumentation

Engineering

Faculty of Engineering and Technology

Department of Electronics and Instrumentation Engineering

SRM University, SRM Nagar

Kattankulathur – 603203

Kancheepuram District

Tamil Nadu

2

CONTENTS

S.No. Page No.

1 Mark Assessment details 3

2 General Instructions for Laboratory classes 4

3 Syllabus 5

4 Introduction to the laboratory 7

5 List of Experiments

5.1 Implementation and testing of code converters. 8

5.2 Implementation and testing of multiplexers &demultiplexer 18

5.3 Implementation of 4-Bit shift registers using flip flops 22

5.4 Implementation and testing of counters using flip flops 28

5.5 Design and implementation of 3-bit synchronous up/down counter 32

5.6 Verification of Mathematical Applications of OP-AMP 35

5.7 Verification of Characteristics of μA741 42

5.8 Design and testing of first order Low Pass and High Pass Active filters 45

5.9 Design and testing of Phase shift Oscillators and Wein bridge

oscillators

53

5.10 Design and testing of Monostable and Astable Multivibrator using

NE555 TIMER

60

3

1. MARK ASSESSMENT DETAILS ALLOTMENT OF MARKS:

Internal assessment = 60 marks

Practical examination = 40 marks

---------------------

Total = 100 marks

----------------------

INTERNAL ASSESSMENT (60 MARKS)

Split up of internal marks

Record 5 marks

Model exam 10 marks

Quiz/Viva 5 marks

Experiments 40 marks

Total 60 marks

PRACTICAL EXAMINATION (40MARKS)

Split up of practical examination marks

Aim and

Procedure 25 marks

Circuit Diagram 30 marks

Tabulation 30 marks

Result 05 marks

Viva voce 10 marks

Total 100 marks

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2. GENERAL INSTRUCTIONS FOR LABORATORY CLASSES

1. Enter the Lab with CLOSED TOE SHOES.

2. Students should wear lab coat.

3. The HAIR should be protected, let it not be loose.

4. TOOLS, APPARATUS and COMPONENT sets are to be returned before leaving the lab.

5. HEADINGS and DETAILS should be neatly written

i. Aim of the experiment

ii. Apparatus / Tools / Instruments

required

iii. Theory

iv. Procedure / Algorithm / Program

v. Model Calculations/ Design

calculations

vi. Block Diagram / Flow charts/ Circuit

diagram

vii. Tabulations/ Waveforms/ Graph

viii. Result / discussions .

6. Experiment number and date should be written in the appropriate place.

7. After completing the experiment, the answer to pre lab viva-voce questions should be neatly

written in the workbook.

8. Be REGULAR, SYSTEMATIC, PATIENT, ANDSTEADY.

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3. SYLLABUS

15EI205L Analog and Digital Integrated Circuits Laboratory

L T P C

0 0 2 1

Co-requisite: 15EI205

Prerequisite: 15EI201

Data Book /

Codes/Standards NIL

Course Category P PROFESSIONAL CORE ELECTRONICS ENGINEERING

Course designed by Department of Electronics and Instrumentation Engineering

Approval 32nd

Academic Council Meeting held on 23rd

July, 2016

PURPOSE To study various Analog, digital & Linear Integrated Circuits used in Simple System Configuration.

INSTRUCTIONAL OBJECTIVES STUDENT OUTCOMES

At the end of the course, student will be able to

1. Enable the students to understand the various types of combinational circuits a

2. Understand the various types of sequential circuits b

3. Study the Operational amplifier characteristics and applications b

4. Design and verify waveform generator circuits and filter circuits a e

Sl.

No. Description of experiments

Contact

hours

C-D-

I-O IOs Reference

1. Implementation and testing of code converters. 3 C 1 1

2. Implementation and testing of multiplexers &demultiplexer 3 D 2 1

3. Implementation of 4-Bit shift registers using flip flops 3 D 1 1

4. Implementation and testing of counters using flip flops 3 C 4 1,2

5.

Design and implementation of 3-bit synchronous up/down

counter 3 C, D 4 1,2

6

Sl.

No. Description of experiments

Contact

hours

C-D-

I-O IOs Reference

6. Verification of Mathematical Applications of OP-AMP 3 C,I,O 1 1,2

7. Verification of Characteristics of μA741 3 C,I,O 1,4 1,2

8.

Design and testing of first order Low Pass and High Pass Active

filters 3 D,I,O 2 1,2

9.

Design and testing of Phase shift Oscillators and Wein bridge

oscillators 3 D,I,O 2,3 1,2

10.

Design and testing of Monostable and Astable Multivibrator

using NE555 TIMER 3 D 4 1,2

Total contact hours

30

LEARNING RESOURCES

Sl.

No. REFERENCES

1. Laboratory Manual

2. Roy Choudhury. D and Shail. B. Jain, “Linear Integrated Circuits”, New Age International 4th

Edition,

2011.

3. Gayakwad. R.A, “Op-amps & Linear Integrated Circuits”, Pearson education, 4th

Edition, 2015.

Course nature Practical

Assessment Method (Weightage 100%)

In-

semester

Assessment

tool Experiments Record

MCQ/Quiz/Viva

Voce

Model

examination Total

Weightage 40% 5% 5% 10% 60%

End semester examination Weightage : 40%

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4. INTRODUCTION TO THE LABORATORY

The Linear and Digital Integrated circuits course has been taught as a required course for

electronics and instrumentation engineering students since the program‟s inception. The Linear

Integrated Circuits course introduces the concept and application of operational amplifiers.

Without a sufficient amount of laboratory experiments, students are left with rather vague

concepts regardless of the instructor‟s effectiveness. Laboratory assignments clarify textbook

formulas and examples, as well as help to close the gap between theory and real-life problems.

An efficient laboratory experiment should:

a) clearly relate to textbook materials,

b) relate to real life situations,

c) challenge students‟ ability to design and test, and

d) encourage the student to analyze the design and draw conclusion.

With these considerations in mind a laboratory workbook has been developed for the linear and

digital Integrated Circuits course.

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Exercise Number:1

Title of the Experiment: IMPLEMENTATION AND TESTING OF CODE

CONVERTORS

Binary to BCD Convertor

OBJECTIVE (AIM) OF THE EXPERIMENT

To convert binary input to corresponding BCD code.

FACILITIES REQUIRED AND PROCEDURE

a) FACILITIES REQUIRED TO DO THE EXPERIMENT:

S.NO APPARATUS SPECIFICATION QUANTITY

1. Digital Trainer Kit - 1

2. IC7432 OR 1

3. IC7404 NOT 4

4. IC7408 AND 3

b) THEORY:

The convertors are used for string to value conversions or translation to or from

supported data types at design time and at run time. The conversion of the signals or the

groups of signals in one code into corresponding signals or group of signals in another

code. The process of converting a code of some predetermined bit structure such as 5 and

7. The bits for characters to another code with same or the different number of bits per

character for the interval. The conversion of the signals or else the group of signals in

another code. The code conversion is known as the process by which the code of some

predetermined bits structure. The bits per characters to another code with same or

different numbers of bits per a character interval.

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c) PROCEDURE:

1. Check the gates in the circuit with the help of truth table.

2. Give the connections as per the circuit diagram.

3. Give input and verify the output.

d) CIRCUIT DIAGRAM:

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BINARY TO BCD TRUTH TABLE

K-Map Simplification:

A1 = AB‟C‟D‟ + ABC‟D‟ + AB‟CD‟ + ABCD‟ + AB‟C‟D + ABC‟D + AB‟CD + ABCD

C’D’ C’D CD CD’

A’B’ 0 0 0 0

A’B 0 0 0 0

AB 1 1 1 1

AB' 1 1 1 1

∴A 1 = A

B1 = A‟BC‟D‟ + ABC‟D‟ + A‟BCD‟ + ABCD‟ + A‟B‟CD + AB‟CD

11


A’B’ 0 0 1 0

A’B 1 0 0 1

AB 1 0 0 1

AB' 0 0 1 0

∴B1= BD‟ + B‟CD

C1 = A‟B‟CD‟ + AB‟C‟D + A‟BCD‟ + ABCD‟ + A‟BCD + ABCD


A’B’ 0 0 0 1

A’B 0 0 1 1

AB 0 0 1 1

AB' 0 0 0 1

∴C1= BC + CD‟

D1 = A‟B‟C‟D + AB‟C‟D


A’B’ 0 1 0 0

A’B 0 0 0 0

AB 0 0 0 0

AB' 0 1 0 0

12

S = A‟BC‟D + ABC‟D + A‟B‟CD + AB‟CD + A‟BCD + ABCD


A’B’ 0 0 1 0

A’B 0 1 1 0

AB 0 1 1 0

AB' 0 0 1 0

∴S = BD + CD

BCD to Binary


To design BCD to Binary convertor using basic logic gates and verify it.


e) FACILITIES REQUIRED TO DO THE EXPERIMENT:



2. IC7408 AND 1

3. IC7432 OR 1

4. IC7486 XOR 1

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Procedure:

1. Check the gate with the truth table.

2. Make the connections as per the circuit diagram.

3. Give input and verify the output.

BCD TO BINARY LOGIC DIAGRAM

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BCD TO BINARY TRUTH TABLE

K-Map simplification:

A1=

E=

0

C’D’

C’

D CD CD’

A’B’ 0 1 1 0

A’B 0 1 1 0

AB X X X X

AB' 0 1 X X

E=

1

C’D’ C’

CD CD’

15

D

A’B’ 0 1 1 0

A’B 0 1 X X

AB X X X X

AB' X X X X

B1=

E=

0

C’D’ C’

D CD CD’

A’B’ 0 0 1 1

A’B 0 0 1 1

AB X X X X

AB' 0

0

X

X

E=

1

C’D’ C’

D CD CD’

A’B’ 1 1 0 0

A’B 1 1 X X

AB X X X X

AB' X X X X

C1=

16

E=0


A’B’ 0 0 0 0

A’B 1 1 1 1

AB X X X X

AB' 0 0 0 0

E=1


A’B’ 0 0 1 1

A’B 1 1 X X

AB X X X X

AB' 0 0 X X

D1=

E=0


A’B’ 0 0 0 0

A’B 0 0 0 0

AB X X X X

AB' 1 1 X X

E=1


A’B’ 1 1 1 1

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A’B 1 1 X X

AB X X X X

AB' X X X X

Result:

Thus the code convertors: Binary-BCD & BCD-Binary were tested and verified.

Pre lab Questions:

1. Explain on the term „code conversion‟.

2. Tabulate equivalent Gray code for decimal 0-9.

3. Tabulate equivalent Binary code for decimal 0-9.

Post lab Questions:

1. Identify the advantage of using Gray code in K Map.

2. Among AND, OR, NAND and EX-OR- which is the suitable gate for comparing two

bits.

3. Concert the following decimal numbers to Gray code

40, 65 and 73.

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Exercise Number: 2

Title of the Experiment: IMPLEMENTATION & TESTING OF MULTIPLEXER AND

DE-MULTIPLEXER


To construct multiplexer and de-multiplexer circuits and verify the truth table.





2. IC7411 3 input AND 2

3. IC7404 NOT 1

4. IC7432 OR 1

5 Patch Cords - -

b) THEORY:

Multiplexer: It is a digital switch. It allows digital information from several sources to berouted into a single output lone. The base multiplier has several data input and a single output line. The selection of a particular input line is controlled by a set of select lines.

De-Multiplexer: It is a circuit that receives information in one of the 2npossible outputlines.

The selection of specific output line is controlled by values of the n selection lines.

c) PROCEDURE:

1. Construct the gates according to the circuit diagram. 2. Activate the gate and power supply.

3. Give the input and note the corresponding output. 4. Enter the output for various combinations.

5. Verify the output.

6. Repeat the procedure for the next circuit.

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d) CIRCUIT DIAGRAM:

MULTIPLEXER

TRUTH TABLE

S0 S1 OUTPUT

0 0 I0

0 1 I1

1 0 I2

1 1 I3

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DEMULTIPLEXER

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Result:

Thus the implementation of MUX and De-MUX was successfully verified

Pre lab Questions:

1. Illustrate the block diagram of Multiplexer.

2. Illustrate the block diagram of De-Multiplexer.

3. Multiplexer is also called a data selector. Justify?

4. Implement a 4:1 using only 2:1 MUX.

5. Implement a 2-input NAND function using suitable multiplexer.

Post lab Questions:

1. Draw the logic diagram of 4:1 MUX using NOR gates.

2. Draw the block diagram of 1x4 DeMUX using 1x2 DeMUX. Draw its truth table.

3. Implement a Full Adder using two 8-to-1 MUX.

4. Implement a Full Adder using two 4-to-1 MUX and one inverter.

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Exercise Number: 3

Title of the Experiment: IMPLEMENTATION OF 4-BIT SHIFT REGISTERS USING

FLIP FLOPS


To convert a shift (both SIS0 and SIP0) and check its operations and verify the truth table.





2. IC7474 D Flip Flop 1

b) THEORY:

The binary information in a register can be moved from one stage to another stage within the register (or) into cut off register upon application of clock pulse. This type of movement on shifting is essential for operation used in micro-processor. This gives into rise of group of register called the shift register.

c) PROCEDURE:

1. Connect the circuit as shown.

2. Connect circuit clock into place in the trainer kit. 3. Connect clock pulse to any of the input and keep them at HIGH.

4. Give power and check for pulse.

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d) CIRCUIT DIAGRAM:

SERIES INPUT PARALLEL OUTPUT

CLOCK PULSE

24

TRUTH TABLE

CLK NO. I/P Q1 Q2 Q3

1 1 1 0 0

2 0 0 1 0

3 0 0 0 1

4 0 0 0 0

5 0 0 0 0

6 1 1 0 0

7 1 1 1 0

8 1 1 1 1

9 1 1 1 1

10 1 1 1 1

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SERIES INPUT SERIES OUTPUT

CLOCK PULSE

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TRUTH TABLE

CLK QA QB

1 1 0

2 0 0

3 0 1

4 0 0

5 0 0

6 1 0

7 1 0

8 1 1

9 1 1

10 0 1

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Result:

Thus the shift registers were implemented using D Flip Flop and verified using truth tables.

Pre lab Questions:

1. What is a latch?

2. Differentiate between Flip flop and a Latch.

3. What does a clock pulse signify in a Flip flop

4. Explain: Positive edge triggered, negative edge triggered and level triggered- clocking

operations.

Post lab Questions:

1. List the applications of Flip flop‟s

2. What is the Difference between Combinational circuits and Flip-flop

3. Which logic gate is used as a two-bit adder?

4. Define shift register counters.

5. What is the use of Preset input?

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Exercise Number: 4

Title of the Experiment: IMPLEMENTATION AND TESTING OF COUNTERS USING FLIP

FLOPS


To design a 4-bit ripple counter using flip flops and to test the same using truth table.




1. Digital IC trainer kit -- 1

2. IC7473 JK Flip Flop

2

3. Patch Cords - Req.

THEORY:

A register that goes through a sequence of stages upon applications of a clock pulse is called a counter. The binary counter which consists of a flip-flop can count upon n-flip-flops which can count binary 0 to 2

n-1. A counter that follows the binary sequence is called binary

counter.

b) Procedure:

1. Connections are made as per the circuit diagram.

2. Apply clock pulse to first flip flop. 3. Verify the output using the truth table.

4. Give the input.

5. Verify using the truth table.

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c) CIRCUIT DIAGRAM

RIPPLE COUNTER

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TRUTH TABLE

CLK QD QC QB QA

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

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Result:

Thus a 4-bit ripple counter using JK Flip Flop was verified using truth table.

Prelab Questions:

1. Explain the working of a counter

2. Justify the name „ripple counter‟.

3. How many flip flops should be used in 2-bit and 4-bit counter.

Post lab Questions:

1. List the applications of counters.

2. Design a 3-bit ripple counter.

3. Give the transition table and excitation table for JK Flip Flop.

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Exercise Number: 5

Title of the Experiment: DESIGN AND IMPLEMENTATION OF -3 BIT

SYNCHRONOUS UP/DOWN COUNTER


To design and implement a 3 bit synchronous up/down counter using JK flip flop

.




1. Digital IC trainer kit -- 1

2. JK flip flop IC 7473

3

3. Connecting wires - Req.

THEORY:

In synchronous counters, the clock inputs of all the flip-flops are connected together and

are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in

parallel).

A synchronous 3-bit up/down counter built from JK flip flops. Depending on the logic

value on the Up/Down input, the counter will increment or decrement its value on the

falling edge of the clock signal.

b) PROCEDURE:

1. Place the IC on the IC trainer kit.

2. Connect Vcc and ground to the respective pins of IC trainer kit.

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3. Connect the inputs to the inputs switches provided in the IC trainer kit.

4. Connect the outputs to the switches of O/P LED‟.

5. Apply various combinations of inputs according to the truth table and observe

conditions of LED‟.

c) CIRCUIT DIAGRAM:

Truth Table:

UP/DOWN

CLK

Q2

Q1

Q0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

0 1 1 1 0

0 1 1 0 1

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0 1 1 0 0

0 1 0 1 1

0 1 0 1 0

0 1 0 0 1

0 1 0 0 0

Result:

Thus the 3 bit synchronous up/down counter using JK flip flop was successfully

implemented and truth table was verified.

Prelab Questions:

1. List the different types of counters?

2. Define the propagation delay in ripple counter?

3. List out applications of counters

4. How many flip flops are required to construct a decade counter

5. How many Flip-Flops are required for mod–16 counter?

Post lab Questions:

1. Explain the modulus of a counter?

2. Compare Synchronous and Asynchronous counters

3. Explain the working of 4 bit ripple counter with truth table and timing diagram

4. Explain the Synchronous decade counter

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Exercise Number: 6

Title of the Experiment: VERIFICATION OF MATHEMATICAL APPLICATIONS OF AN

OP-AMP


To study the following applications of OP-AMP

(i) Adder (ii) Subtractor (iii) Differentiator (iv) Integrator




1. OPAMP IC741 1

2. Resistors 1kΩ, 2kΩ Each 3

10kΩ

3. Capacitors 0.1µF 3

4. RPS 0-30V 1

5 CRO 1MHz 1

6 Function Generator - 1

7 Connecting wires - Req.

b) THEORY:

ADDER

OP-AMP may be used to design a circuit where output is the sum of several input signals.

Such a circuit is called summing amplifier.

Vout = Rf/Ri (V1+V2)

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SUBTRACTOR

A basic differential amplifier can be used as a subtractor. If all resistors are equal in value

then the output voltage can be derived by using

Vout = Rf/Ri (V1-V2)

DIFFERENTIATOR

One of the simplest circuits of OP-AMP that contains capacitor is the differentiating

amplifier. As the name suggests the circuit performs the mathematical operation of

differentiator, it connects an input square wave form to spikes.

Vout = Rf C1(dv/dt)

INTEGRATOR

This is a circuit that performs the operation of integration because it produces the output

voltage proportional to integral of input voltage.

Vout = (-1/Rf)C1 [ fVi(t)dt + Vo(D) ]

c) PROCEDURE:

Hook up the circuit as shown in the circuit diagram.

Switch on the power supply.

Connect the function generator to the input of the circuit.

Observe the output waveform in CRO.

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d) CIRCUIT DIAGRAM:

Adder Circuit:

Subtractor Circuit:

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Integrator Circuit:

Model Graph:

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Differentiator circuit:

Model Graph:

e) TABULATION:

Adder:

V1

V2

V0

Theoretical Practical

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Subtractor:

V1

V2

V0

Theoretical Practical

Integrator:

Input:

Time/Division

(s)

No. of

divisions

Time

Per.(s)

Frequency

F=1/T

Amplitud

e/Divisio

n

(V)

No. of

Divisions

Amplitu

de

(V)

Output:

Time/Division

(s)

No. of

divisions

Time

Per.(s)

Frequency

F=1/T

Amplitud

e/Divisio

n

(V)

No. of

Divisions

Amplitu

de

(V)

Differentiator

Input:

Time/Division No. of

divisions

Time Frequency Amplitud

e/Divisio

No. of

Divisions

Amplitu

de

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(s) Per.(s) F=1/T n

(V)

(V)

Output:

Time/Division

(s)

No. of

divisions

Time

Per.(s)

Frequency

F=1/T

Amplitud

e/Divisio

n

(V)

No. of

Divisions

Amplitu

de

(V)

Result:

Thus the applications of an Operational Amplifiers as an Adder, Sub tractor,

Differentiator, and Integrator was successfully studied and verified.

Pre lab Questions:

1. Define integrator?

2. Define differentiator?

3. What are the limitations of an ordinary differentiator?

4. What are the limitations of an ideal integrator?

5. What are the initial conditions of a loss integrator?

Post lab Questions:

1. Explain how the practical differentiator will overcome the limitations?

2. What are the differences between integrator and differentiator?

3. State the applications of integrator and differentiator?

4. Explain why integrators are preferred in analog computers than differentiators?

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Exercise Number: 7

Title of the Experiment: VERIFICATION OF THE CHARACTERISTICS OF ΜA741


To study and verify the characteristics of an operational amplifier.




1. OPAMP IC741 1

2. Resistors 1kΩ, 2kΩ Each 3

10kΩ

3. Capacitors 0.1µF 3

4. RPS 0-30V 1

5 CRO 1MHz 1

6 Function Generator - 1

7 Connecting wires - Req.

b) THEORY:

Operational amplifiers (OP-AMP) has 2 input terminals and one output terminal. The negative

and positive symbols at the input refer to inverting and non inverting terminals respectively. The

simplest way to use an OP-AMP in the open loop mode where the signals V1, V2 are applied at

non-inverting and inverting input terminal respectively. Since the infinite the output voltage Vo

is either at it‟s positive saturation voltage. The output assumes one of the possible outputs

positive +Vsat or –Vsat and the amplifiers at a switch only this has a limited application as

voltage compensation.

43

c) PROCEDURE:

Input Offset Voltage:

1. Circuit connections are made as per the circuit diagram.

2. The output is measured on a CRO.

3. Input voltage is calculated using V=Vo(R1/R2)

Bandwidth:

1. Circuit connections are made as per the circuit diagram.

2. Increasing the frequency till output voltage reduces 2.7 times the original value this

gives the bandwidth

Slew Rate:

1. Circuit connections are made and square wave input is given and output is observed

in CRO.

2. The peak to peak voltage and time taken by output to switch from maximum is

measured

Slew Rate = (∆V/∆t)

CMRR:

1. Circuit connections are made

2. Sinusoidal input is given and output is seen from CRO

Acm= Common mode gain = (Vo/Vin)

Ad = Differential mode gain = (R2/R1)

CMRR = 20 lag (Ad/Ac)

Pin Diagram:

d) CIRCUIT DIAGRAM:

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Result:

Thus the characteristics of an Operational Amplifier was successfully studied and

verified.

Pre lab Questions:

1. What are the ideal characteristics of an Op-amp?

2. Define Slew rate?

3. Define CMRR?

4. What are the value of PSRR and CMRR for ideal op-amp ?

5. What is the temperature range of IC741?

Post lab Questions:

1. Draw the pin diagram of Op-Amp?

2. What are the differences between common mode and differential mode?

3. If V0 = Vin sin ωt Write the expression for slew rate (SR) ?

4. What is virtual ground?

5. What are the non-ideal D.C characteristics of an Op-Amp?

6. Define input bias current, thermal drift and input offset voltage?

45

Exercise Number: 8

Title of the Experiment: DESIGN AND TESTING OF FIRST ORDER LOW PASS

FILTER AND HIGH PASS ACTIVE FILTERS


To Design and study the characteristics of first order low pass and high pass filter.



S.No Apparatus Quantity

1 Op-Amp 1

2 Resistors 3

3 Capacitors 1

4 Bread Board 1

5 DSO 1

6 Function Generator 1

7 Connecting Probes 2

8 Connecting Wires As required

b) THEORY:

Low Pass Filter:

This first-order low pass active filter, consists simply of a passive RC filter stage providing a low

frequency path to the input of a non-inverting operational amplifier. The amplifier is configured

as a voltage-follower (Buffer) giving it a DC gain of one, Av = +1 or unity gain as opposed to

the previous passive RC filter which has a DC gain of less than unity.

46

The frequency response of the circuit will be the same as that for the passive RC filter, except

that the amplitude of the output is increased by the pass band gain, AF of the amplifier. For a

non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a

function of the feedback resistor ( R2 ) divided by its corresponding input resistor ( R1 ) value

and is given as:

Therefore, the gain of an active low pass filter as a function of frequency will be:

Gain of a first-order low pass filter

Where:

AF = the pass band gain of the filter, (1 + R2/R1)

ƒ = the frequency of the input signal in Hertz, (Hz)

ƒc = the cut-off frequency in Hertz, (Hz)

Thus, the operation of a low pass active filter can be verified from the frequency gain equation

above as:

1. At very low frequencies, ƒ < ƒc

2. At the cut-off frequency, ƒ = ƒc

3. At very high frequencies, ƒ > ƒc

Thus, the Active Low Pass Filter has a constant gain AF from 0Hz to the high frequency cut-off

point, ƒC. At ƒC the gain is 0.707AF, and after ƒC it decreases at a constant rate as the frequency

increases. That is, when the frequency is increased tenfold (one decade), the voltage gain is

divided by 10.

In other words, the gain decreases 20dB (= 20log 10) each time the frequency is increased by 10.

When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally

expressed in decibels or dB as a function of the voltage gain, and this is defined as:

Magnitude of Voltage Gain in (dB)

47

High Pass Filter:

A first-order (single-pole) Active High Pass Filter as its name implies, attenuates low

frequencies and passes high frequency signals. It consists simply of a passive filter section

followed by a non-inverting operational amplifier. The frequency response of the circuit is the

same as that of the passive filter, except that the amplitude of the signal is increased by the gain

of the amplifier and for a non-inverting amplifier the value of the pass band voltage gain is given

as 1 + R2/R1, the same as for the low pass filter circuit.

For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a

function of the feedback resistor ( R2 ) divided by its corresponding input resistor ( R1 ) value

and is given as:

Gain for an Active High Pass Filter

Where

AF = the Pass band Gain of the filter, ( 1 + R2/R1 )

ƒ = the Frequency of the Input Signal in Hertz, (Hz)

ƒc = the Cut-off Frequency in Hertz, (Hz)

Just like the low pass filter, the operation of a high pass active filter can be verified from the

frequency gain equation above as:

1. At very low frequencies, ƒ < ƒc

2. At the cut-off frequency, ƒ = ƒc

3. At very high frequencies, ƒ > ƒc

48

Then, the Active High Pass Filter has a gain AF that increases from 0Hz to the low frequency

cut-off point, ƒC at 20dB/decade as the frequency increases. At ƒC the gain is 0.707AF, and

after ƒC all frequencies are pass band frequencies so the filter has a constant gain AF with the

highest frequency being determined by the closed loop bandwidth of the op-amp.

When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally

expressed in decibels or dB as a function of the voltage gain, and this is defined as:

Magnitude of Voltage Gain in (dB)

For a first-order filter the frequency response curve of the filter increases by 20dB/decade or

6dB/octave up to the determined cut-off frequency point which is always at -3dB below the

maximum gain value. As with the previous filter circuits, the lower cut-off or corner frequency

( ƒc ) can be found by using the same formula:

The corresponding phase angle or phase shift of the output signal is the same as that given for the

passive RC filter and leads that of the input signal. It is equal to +45o at the cut-off

frequency ƒc value and is given as:

c) PROCEDURE:

1. Connect the circuit as shown in the figure

2. Give an input signal Vi of 1-V (p-p) and measure the output voltage for different

frequencies.

3. Plot frequency response 20 log (V0 / Vi) Vs input frequency and find the 3db

frequency.

4. Determine the cut-off frequency.

49

d) CIRCUIT DIAGRAM:

Low Pass Filter

High Pass Filter

50

e) Tabulation:

Low Pass

F(Hz) Output Voltage (V) Gain in dB

High Pass

F(Hz) Output Voltage (V) Gain in dB

51

Model Graph:

Low Pass Filter

High Pass Filter

52

Result:

The first order low pass filter and high pass filter was designed and tested and its output was

successfully verified.

Prelab Questions:

1. Define filter.

2. Define low pass filter and high pass filter.

3. What are advantages of active filter over passive filter?

Post lab Questions:

5. write down the transfer function of a first order butterworth normalised low pass filter

and high pass filter.

6. Design a Low Pass Filter for frequency 1kHz.

7. Design a High Pass Filter for frequency 1kHz.

53

Exercise Number: 9

Title of the Experiment: DESIGN AND TESTING OF PHASE SHIFT OSCILLATORS AND

WEIN BRIDGE OSCILLATORS.


To design, construct and test the RC Phase shift Oscillator and Wein Bridge Oscillator.




1 Op-Amp 1

2 Dual Power Supply 1

3 Resistors 6

4 Capacitors 3

5 CRO 1

6 Bread Board 1

7 Connecting Probes 2

8 Connecting Wires As Required

b) THEORY:

As oscillator is basically a feedback circuit where a fraction Vf of the output voltage V0 of an

amplifier is fed back to the input in the same phase.

For sustained oscillation, Aβ = 1. That is the magnitude condition IAβI = 1 and the phase

condition

Phase Shift Oscillator

54

The op-amp produces a phase shift of 1800 as it is used in inverting mode. An additional phase

shift of 1800 is provided by the feedback RC network. The transfer function of the RC network

can be easily calculated as,

02 2 2 3 3 3

1

6 5 11

fV

V

sRC s R C s R C

Letting s j ,

2 3

1 1 1

1

1 5 6f f f

jf f f

Where 1

1

2f

RC

For 1A , should be real. So the imaginary terms must be equal to zero, that is

3

1 16 0f f

f f

(Or)

1 6f

f

The frequency of the oscillation f0 is given by

0

1

6(2 )f

RC

1

1

29

10

fR R

R R

Wein Bridge Oscillator:

Another commonly used audio frequency oscillator is Wein bridge oscillator. The feedback

signal in this circuit is connected to the (+) input terminal so that the op-amp is working as a

non-inverting amplifier. Therefore, the feedback network need not provide any phase shift. The

55

circuit can be viewed as a wein bridge with sries RC network in one arm and a parallel RC

network in the adjoining arm. Resistors R1 and Rf are connected in the remaining two arms. The

condition of zero phase shift around the circuit is achieved by balancing the bridge.

From the feedback network, the feedback factor is

23 ( 1/ )

R

R j R C C

For 1A , must be real and imaginary part must be zero.

0

1

1

2

RC

fRC

At 0f , 1

3 . therefore, for sustained oscillation, the amplifier must have a gain of precisely 3.

However, from practical point of view, A may be slightly less or greater than 3.

For 3A , the oscillation either die down or fail to start when power is first applied.

For 3A , the oscillations will be growing.

c) PROCEDURE:

RC Phase Shift Oscillator:

1. Design the circuit for given f0 and calculate the resistor values R1, R2 and Rf


3. Switch on the power supply and observe the waveform

4. Note down the amplitude and time period

5. Plot the wave forms on the graph sheet.

Wein Bridge Oscillator:

1. Design the circuit for given f0 and calculate the resistor values R, C, Rf and R1


3. Switch on the power supply and observe the waveform

4. Note down the amplitude and time period

5. Plot the wave forms on the graph sheet.

56

d) CIRCUIT DIAGRAM:

RC Phase Shift Oscillator

Wein Bridge Oscillator

57

Model Graph:

e) TABULATION:

RC Phase Shift Oscillator

Input Output

Amplitude Time Period Frequency Amplitude Time Period Frequency

58

Wein Bridge Oscillator

Input Output

Amplitude Time Period Frequency Amplitude Time Period Frequency

Result:

Thus, the RC Phase shift oscillator and Wein Bridge Oscillator are designed and tested

Pre lab Questions:

6. Define Oscillator.

7. List different types of oscillators.

8. Draw basic oscillator feedback circuit.

Post lab Questions:

1. Explain how clipping is eliminated in wein bridge oscillator.

2. Draw the basic characteristics of a feedback oscillator.

59

3. What is the frequency range of LC Oscillator.

4. For sustained oscillations, what is the gain of the RC phase shift oscillator.

60

Exercise Number: 10 (a)

Title of the Experiment: Design and testing of Astable Multivibrator using NE555 Timer


To design and test the monostable and astablemultivibrator using 555 Timer.





2 CRO 1

3 Dual RPS 1

4 IC 555 Timer 1

5 Bread Board 1

6 Resistors 2

7 Capacitors 2

8 Connecting wires and Probes As Required

b) THEORY:

An astablemultivibrator, often called a free-running multivibrator, is a rectangular-wave

generating circuit. This circuit do not require an external trigger to change the state of the

output. The time during which the output is either high or low is determined by two resistors and

a capacitor, which are connected externally to the 555 timer. The time during which the

capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by,

tc = 0.69 (R1 + R2) C

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Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the

time the output is low and is given by, td = 0.69 (R2) C

Thus the total time period of the output waveform is, T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astablemultivibrator. The duty

cycle is the ratio of the time tc during which the output is high to the total time period T. It is

generally expressed in percentage.

In equation form,

% duty cycle = [ R2 / (R1 + 2 R2)] x 100% or td / tc x 100%

PIN DIAGRAM:

c) PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + 5V supply is given to the + Vcc terminal of the timer IC.

3. At pin 3 the output waveform is observed with the help of a CRO

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4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage

waveforms are plotted in a graph sheet.

d) CIRCUIT DIAGRAM:

DESIGN:

Given f= 11.11 KHz and duty cycle = 23%

Therefore, Total time period, T = 1/f = 90 x 10-6 s

We know, duty cycle = td / T

23 / 100 = td / 90 x 10-6 , td = 0.23 x 90 x 10-6

Therefore, td = 20.7 x 10-6 s

C

0.01μF

63

and tc = T – td = 90 x 10-6 - 20.7 x 10-6 = 69.3 x 10-6 s

We also know for an astablemultivibrator

td = 0.69 (R2) C

Assume C = 0.01 x 10-6

F,

R2 = td /(0.69 x C) = 20.7 x 10-6 / (0.69 x 0.01 x 10-6)

Therefore, R2 = 3KΩ

tc = 0.69 (R1 + R2) C

R1 = (tc / (0.69 x C)) – R2

R1 = (69.3 x 10-6 / (0.69 x 0.01 x 10-6)) - 3000

Therefore, R1 = 7 KΩ ≈ 6.8 KΩ ≈ 7.5 KΩ

MODEL GRAPH:

e) Tabular Column:

S.No Amplitude Time Period

tc td

64

1 Output Voltage, V0

2 Capacitor Voltage, Vc

Result:

The design of the Astablemultivibrator circuit was done and the output voltage

andcapacitor voltage waveforms were obtained.

Pre-Lab QUESTIONS:

1. Define Offset voltage.

2. Define duty cycle.

3. Mention the applications of IC555.

4. Give the methods for obtaining symmetrical square wave.

5. What is the other name for monostable multivibrator?

Post-Lab Questions

1. Explain the operation of IC555 in astablemode..

2. Why negative pulse is used as trigger?

65

Exercise Number: 10 (b)

Title of the Experiment: Design and testing of Monostable Multivibrator using NE555

Timer


To design a monostable multivibrator for the given specifications using 555 Timer IC.





2 CRO 1

3 Dual RPS 1

4 IC 555 Timer 1

5 Bread Board 1

6 Resistors 2

7 Capacitors 2

8 Connecting wires and Probes As Required

b) THEORY:

A monostable multivibrator often called a one-shot multivibrator is a pulse generating

circuit in which the duration of the pulse is determined by the RC network connected

externallyto the 555 timer. In a stable or stand-by state the output of the circuit is approximately

zero or atlogic low level. When an external trigger pulse is applied, the output is forced to go

high(approx. Vcc). The time during which the output remains high is given by,tp = 1.1 R1 C

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At the end of the timing interval, the output automatically reverts back to its logic low

state. The output stays low until a trigger pulse is applied again. Then the cycle repeats.

Thus the monostable state has only one stable state hence the name monostable.

PIN DIAGRAM:

c) PROCEDURE:

1. Connections are given as per the circuit diagram.

2. + 5V supply is given to the + Vcc terminal of the timer IC.

3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC

4. At pin 3 the output waveform is observed with the help of a CRO

5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage

waveforms are plotted in a graph sheet.

d) CIRCUIT DIAGRAM:

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DESIGN:

Given tp = 0.1ms, tp = 1.1 R1 C

Assume C = 0.01 x 10-6 F,

Therefore, R1 = 9.09 KΩ ≈ 9.1 KΩ ≈ 10 KΩ

MODEL GRAPH:

C

0.01μF

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e) Tabular Column:

S.No Amplitude Time Period

tc td

1 Output Voltage, V0

2 Capacitor Voltage, Vc

Result:

The design of the Monostable multivibrator circuit was done and the input and

outputwaveforms were obtained.

Pre-Lab QUESTIONS:

1. Explain the operation of IC555 in monostable mode.

2. What is the charging time for capacitor in monostable mode?

3. What are the modes of operation of 555 timers?

69

Post-Lab Questions

1. Give the comparison between combinational circuits and sequential circuits.

2. What do you mean by present state?

3. Give the applications of 555 timers IC

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