#147 MAPLD 2005Mark A. Johnson1 Design of a Reusable SpaceWire Link Interface for Space Avionics and...

#147 MAPLD 2005Mark A. Johnson 1

Design of a ReusableSpaceWire Link Interface for

Space Avionics and Instrumentation

Mark A. JohnsonSenior Research Engineer

Southwest Research InstituteSan Antonio, Texas

(210) [email protected]


Space LAN Background

• Spacecraft Local Area Networks (LANs)– Not a new concept. MIL-STD-1553B is a common

spacecraft data network that is used throughout the spacecraft community

– Recent interest in high performance LANS is fueled by the promise of:

• Enabling technology for distributed data collection and processing (I.e. multi-instrument clusters or “Sensor webs”)

• Reduced I&T time and cost

• Leverages off of developments and successes in commercial industry


SpaceWire Overview

• What is SpaceWire?– High performance serial bus supporting rates between 2Mbps and

400Mbps– Based on IEEE 1355-1995, coupled with LVDS physical interface– European Space Agency Standard - ECSS-E-50-12A– Layered Protocol (Physical, Signal, Character, Exchange, Packet,

Network)• Goals of Spacewire

– Provide a unified high speed data handling infrastructure that will meet the needs of future, high bandwidth space missions

– Reduce system integration costs– Promote compatibility between instruments and subsystems– Encourage design reuse across missions


SwRI SpaceWire IR&D Program

• Major goals of SwRI SpaceWire IR&D program.– Develop a re-usable HDL (Verilog or VHDL) based SpaceWire Link

Interface Core• Motivating factor is to provide a low-power, reusable, and portable logic

core that can be easily incorporated into FPGA designs without requiring separate SpaceWire interface IC’s.

– Optimized for size and board area constrained electronics (i.e. miniaturized science instruments, Command and Data Handling systems, etc.)


Physical Layer

Data LinkLayer

Network Layer

TransportLayer

Session Layer

PresentationLayer

ApplicationLayer

Physical Level

CharacterLevel

ExchangeLevel

Packet Level

Network Level

ISO OSI Layer Model SpaceWire Layer Model

NetworkAccess Layer

Internet Layer

TransportLayer

ApplicationLayer

TCP / IP Model

SwRI SpaceWire IR&D Program

• Major Goals of IR&D Program - Continued– Provide a test bed to evaluate the applicability of Internet Protocol (IP)

to the SpaceWire Serial Bus Protocol.


Spacewire Technical Overview

• Spacewire standard defines a multi-level interface– Physical level

• Connectors, cables, board impedances, etc.

– Signal level• Electrical characteristics, signal levels, timing

– Character level• Defines how data and control characters are encoded

– Exchange level (or link level)• Defines the way the Spacewire link operates. Covers initialization, normal operation,

error handling

– Packet level• Defines the way data is encapsulated in packets for transfer

– Network Level• Defines the structure and operation of a Spacewire network, including routing,

architecture, etc.


• Spacewire link comprises 2 pairs of differential signals– Transmit Data / Strobe– Receive Data / Strobe

• Spacewire uses Data-Strobe (DS) encoding– Encodes transmit clock with data into Data and Strobe– Clock is recovered by XORing the Data and Strobe together– Provides skew tolerance of almost 1 full bit time

Spacewire Technical OverviewSignal Level


Spacewire Technical OverviewCharacter Level

• Based on IEEE 1355-1995, with extensions to support Time Code broadcast.– Two Types of Spacewire “characters”:

Data & Control.– Data characters are 8 bits with data /

control flag = 0.– Control characters have data / control flag

= 1. Used for link flow control and to signal the occurrence of errors.

– All characters contain a parity bit that ensures odd parity over.

– Null control character is sent whenever a link is not sending data or control tokens to keep the link active and support disconnect detection.


• Character Types:– Null = Esc / FCT: 8 bits

• Used in initialization / fill

– Flow Control Token (FCT): 4 bits

• Indicates to receiving node that 8 more bytes may be transmitted

– End of Packet (EOP): 4 bits• Signifies end of normal packet

– Error End of Packet (EEP): 4 bits

• Signifies end of packet w/ error(s)

– Data: 10 bits

– Time Code = Esc / Data: 14 bits

Spacewire Technical OverviewCharacter Level

Parity Calculation and Coverage


Spacewire Technical OverviewExchange / Link Level

• Exchange Level (or Link Level) is responsible for making a connection across a link and for managing the flow of data across the link.

• Exchange Level comprises 5 major processes– Initialization– Flow Control– Detection of Disconnect Errors– Detection of Parity Errors– Link Error Recovery

Link Interface Block Diagram


Nominal Link Operation State Diagram

Spacewire Technical OverviewExchange / Link Level

Link Error Handling State Diagram


SpaceWire Link Interface Module (SLIM)

• cPCI SpaceWire Link Interface • Proof of concept module

developed as part of this IR&D for the test, verification, and operational experience with the SpaceWire protocol

• Provides:– Single Channel, full-duplex

SpaceWire Link Interface– Fully Compliant

CompactPCI target interface– 3U cPCI form-factor


SLIM Overview

• SpaceWire Link is implemented in a single Actel FPGA– Actel 54SX72A

• SEQ: 32.31%• COMB: 30.04%• In-house developed cPCI Core• Coded in Verilog

– 4 stacked 16x9 Rx FIFOs

– 4 stacked 16x9 Tx FIFOs

– LVDS receiver

– LVDS driver

– All components chosen to have direct flight equivalent replacements.

33MHz, 32bit cPCI Bus

Spacewire Link Core

InterruptProcessing

LogicSwRI cPCI Target Core

cPCI / Spacewire LinkFPGA

8FIFO Controller

and Read / WriteLogic

32

16K x 9FIFO

96

16K x 9FIFO

16K x 9FIFO

16K x 9FIFO

16K x 9FIFO

96

16K x 9FIFO

16K x 9FIFO

16K x 9FIFO


• Two Tiered Verification Approach– Simulation Test Bench– Laboratory Testing

Design Verification and Validation


Simulations

• Simulation test bench created from board schematic– Pre-layout RTL FPGA– Post-layout back-annotated FPGA– Model of companion SpaceWire block– FIFO models w/ timing checks– cPCI processor model w/ timing checks


• SpaceWire Model provides:– Transmit:

• Normal sequences of all types (control & data)• Error sequences

– Receive:• Reports control & data received• Reports link error sequences received

– Loop-back mode: Tx wired to Rx• Reports control & data transmitted• Reports link error sequences transmitted

SimulationsSpaceWire Model


• cPCI Model provides:– Writes– Reads w/ data compare checks– Loop reads for specific data patterns– I/O timing checks

SimulationscPCI Model


Laboratory Prototype Testing

• Test set configuration– 4-Links SpaceWire card

for SpaceWire • interface compatibility

testing

– COTS Single Board Computer (SBC)

• Command, Control, Stimulus

– VMETRO cPCI bus Protocol Analyzer

• Monitoring of cPCI bus for PCI protocol violations

– Agilent Logic Analyzer • Detailed timing

verification


Laboratory Prototype Testing

• Laboratory Testing Results– Link Operating Frequency – 2Mbps up to 30Mbps

– Successfully verified full SpaceWire Link operation • Link Initialization, FCTs, restart, error handling, timing, variable length

packet transmission and reception, time code operation

– Successfully verified full cPCI target compliance

#147 MAPLD 2005Mark A. Johnson1 Design of a Reusable SpaceWire Link Interface for Space Avionics and...

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