135995051-Giao-Trinh-Thá»±c-Hanh-DE2

7/22/2019 135995051-Giao-Trinh-Thc-Hanh-DE2

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NI DUNG

Chng 1. Kit DE2 Development and Education Board ................... 201.1 Tng quan vKit DE2.................................................................. 201.2 c im ca kit DE2 .................................................................. 201.3 Ti liu htr............................................................................... 261.4 ng dng trong ging dy v hc tp: .......................................... 271.5 ng dng trong nghin cu v thit k......................................... 271.6 Mt sng dng minh ha ........................................................... 27

1.6.1 ng dng trong truyn hnh ............................................... 271.6.2 ng dng giao tip USB .................................................... 281.6.3 ng dng to bi ht karaoke v my nghe nhc ................ 29

Chng 2. Hng dn sdng Kit DE2 .............................................. 312.1 Kim tra Kit DE2 ......................................................................... 312.2 Hng dn ci t USB-Blaster Driver ........................................ 322.3 Thit lp cu hnh ban u v thay i cu hnh mi cho Cyclon II

FPGA ....................................................................................... 362.3.1 Thit lp cu hnh ban u cho FPGA thng qua vic np cu hnh

cho bnhEPPROM EPCS16 bng AS mode: .................. 392.4 Smch v hot ng ca cc linh kin trn Kit DE2 ............. 40

2.4.1 Switches (cng tc) v Button (nt nhn) ........................... 402.4.2 Leds................................................................................ 432.4.3 LED hin thby on ........................................................ 452.4.4 LED hin thLCD .............................................................. 48


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2.4.5 Ng vo xung Clock ........................................................... 612.4.6 Expansion Header (Jac cm mrng) ................................ 622.4.7 VGA ............................................................................... 662.4.8 Audio CODEC 24-bit ......................................................... 712.4.9 Cng ni tip RS-232 ......................................................... 722.4.10Cng ni tip PS/2 ............................................................. 732.4.11Mch iu khin mng Fast Ethernet .................................. 74

2.4.12TV Decoder ........................................................................ 76

2.4.13TV Encoder ........................................................................ 782.4.14USB Host and Device ........................................................ 792.4.15Cng hng ngoi ................................................................ 812.4.16BnhSDRAM/SRAM/Flash ........................................... 82

Chng 3. Hng dn ci t v sdng phn mm Control Panel iukhin kit DE2 ....................................................................................... 893.1 Hng dn ci t Control Panel iu khin Kit DE2................... 893.2 Tng quan vcu trc v hot ng ca Control Panel ................ 923.3 Hng dn sdng Control Panel ................................................ 95

3.3.1 iu khin LEDs, LEDs by on, LCD ............................ 953.3.2 Truy xut bnhSDRAM/SRAM ..................................... 963.3.3 Truy xut bnhFlash (Flash memory) ............................. 993.3.4 TOOLS Multi-Port SRAM/SDRAM/Flash Controller ... 1023.3.5 VGA Display Control ....................................................... 103


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5.2.1 Bi thc hnh s1 Thit kmch thp v mch tun tn gin......................................................................................... 194

5.2.2 Bi thc hnh s2 Thc hnh tm hiu thit klatches, flip-flopsv counters. ...................................................................... 198

5.2.3 Bi thc hnh s3 Thit khthng sdng xung Clock thigian thc .......................................................................... 208

5.2.4 Bi thc hnh s4 Thc hnh tm hiu thit ksdng Statemachine ............................................................................ 210

5.2.5 Bi thc hnh s5 Thc hnh tm hiu phng php thit konchip Memory trn FPGA v phng php sdng offchipMemory ............................................................................ 214

Chng 6. Hng dn thit kv thc hnh mn Kin trc my tnh nngcao. ......................................................................................... 2276.1 Kin thc tng qut vvi xl Nios II ....................................... 227

6.1.1 Gii thiu tng quan Nios II ............................................. 2276.1.2 Kin trc bxl Nios II ................................................. 2336.1.3 M hnh lp trnh .............................................................. 240

6.2 Hng dn thc hnh trn vi xl Nios II .................................. 2736.2.1 Nios II System : ................................................................ 2736.2.2 Mmt project mi.......................................................... 274

6.3 Ni dung thc hnh mn Kin trc my tnh nng cao ............... 2966.3.1 Bi thc hnh s1 Thit kv sdng mt hthng my tnh n

gin .................................................................................. 2966.3.2 Bi thc hnh s2 iu khin nhp xut dliu tVi x

l...301 6.3.3 Bi thc hnh s3 Tm hiu cch thc hot ng v sdng

Subroutine v Stack ca Vi xl NiosII ........................... 313


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6.3.4 Bi thc hnh s4 Tm hiu cch thc hot ng v sdngPolling v Interrupt ca Vi xl NiosII ............................ 327

6.3.5 Bi thc hnh s5 Tm hiu cch thc giao tip Bus .... 350

Chng 7. M phng m tthit kbng ModelSim ......................... 3597.1 Gii thiu ................................................................................... 3597.2 M phng pre-synthesis ............................................................. 3607.3 M phng post-synthesis ............................................................ 372

7.3.1 Dng Quartus to Verilog netlist cho vic m phng post-synthesis ....................................................................... 372

7.3.2 Dng ModelSim chy m phng post-synthesis .......... 3757.3.3 Mli project v waveform chy m phng ................ 389


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MC LC HNH

Hnh 1.1 Board mch DE2 ................................................................................... 20Hnh 1.2 Skhi board mch DE2 .................................................................. 22Hnh 1.3 ng dng trong xl nh v truyn hnh ............................................... 28Hnh 1.4 ng dng giao tip USB ....................................................................... 29Hnh 1.5 ng dng trong xl m thanh .............................................................. 29

Hnh 2.1 Mn hnh VGA mc nh ...................................................................... 32Hnh 2.2 Chvtr driver cho hardware ................................................................ 33Hnh 2.3 Chng dn cho driver ...................................................................... 34Hnh 2.4 Chng dn cho driver ...................................................................... 34Hnh 2.5 Chng dn cho driver ...................................................................... 35Hnh 2.6 Khng cn kim tra driver ..................................................................... 36Hnh 2.7 Driver c ci t thnh cng ......................................................... 36Hnh 2.8 Thit lp cu hnh cho FPGA thng qua JTAG mode ............................ 38Hnh 2.9 Thit lp cu hnh cho FPGA thng qua AS mode ................................ 39Hnh 2.10 Chc nng chng ny cho Push button ................................................ 40Hnh 2.11 Mch thit kca switches v push button .......................................... 41Hnh 2.12 Mapped pins gia switches v FPGA .................................................. 42Hnh 2.13 Mapped pins gia Push button v FPGA ............................................. 42Hnh 2.14 Mch thit kca Leds ........................................................................ 43Hnh 2.15 Mapped pins gia LEDs v FPGA ...................................................... 44Hnh 2.16 Led 7 on .......................................................................................... 45Hnh 2.17 Mch thit kca LEDs 7 on ........................................................... 46Hnh 2.18 Mapped pins gia LEDs 7 on v FPGA ........................................... 48


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Hnh 2.45 Mapped pins gia DM9000A v FPGA ............................................... 76Hnh 2.46 Mch thit kgiao tip gia ADV7181 v FPGA ................................ 77Hnh 2.47 Mapped pins gia ADV7181 v FPGA ............................................... 78Hnh 2.48 TV encoder ADV7123 v FPGA ......................................................... 79Hnh 2.49 Mch thit kgiao tip USB gia chip ISP1362 v FPGA .................. 80Hnh 2.50 Mapped pins gia ISP1362 v FPGA .................................................. 81Hnh 2.51 Mch giao tip gia cng hng ngoi v FPGA .................................. 82Hnh 2.52 Mapped pins gia cng hng ngoi v FPGA...................................... 82Hnh 2.53 Mch giao tip thit kgia DRAM v FPGA .................................... 83Hnh 2.54 Mch giao tip thit kgia SRAM v FPGA ..................................... 83Hnh 2.55 Mch giao tip thit kgia FLASH v FPGA ................................... 84Hnh 2.56 Mapped pins gia SDRAM v FPGA .................................................. 85Hnh 2.57 Mapped pins gia SRAM v FPGA .................................................... 87Hnh 2.58 Mapped pins gia FLASH v FPGA ................................................... 88

Hnh 3.1 Giao din cho vic cu hnh thit kln FPGA ..................................... 90Hnh 3.2 Giao din Control Panel ........................................................................ 91Hnh 3.3 Giao tip gia Control Panel v cc thit bngoi vi trn FPGA ........... 92Hnh 3.4 Skhi giao tip gia Control Panel v cc thit bngoi vi ............ 94Hnh 3.5 Giao din Control Panel iu khin LEDs 7 on ................................. 95Hnh 3.6 Giao din Control Panel iu khin LEDs n ...................................... 96Hnh 3.7 Giao din Control Panel iu khin SDRAM ........................................ 97Hnh 3.8 Giao din Control Panel iu khin FLASH ......................................... 100Hnh 3.9 Giao din Control Panel iu khin Multi-Ports ................................... 102Hnh 3.10 Giao din Control Panel iu khin VGA ........................................... 103Hnh 3.11 Giao din Control Panel iu khin Multi-ports ................................. 105


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Hnh 3.12 Cu hnh trn FPGA ca Multi-ports .................................................. 105Hnh 3.13 Mn hnh VGA................................................................................... 106Hnh 3.14 Trnh bin i nh .............................................................................. 107Hnh 3.15 Gi trngng ca nh ....................................................................... 108

Hnh 4.1 Mn hnh chnh ca Quartus ................................................................. 109Hnh 4.2 Tab File ................................................................................................ 110Hnh 4.3 To project ........................................................................................... 110Hnh 4.4 Chng dn v tn project ................................................................ 111Hnh 4.5 ng dn cha tn ti ........................................................................ 111Hnh 4.6 Add cc file sdng trong project ........................................................ 112Hnh 4.7 Chn thit b FPGA .............................................................................. 112Hnh 4.8 Thit lp EDA tool ............................................................................... 113Hnh 4.9 Hon thnh vic to project .................................................................. 114Hnh 4.10 Mn hnh chnh sau khi to project hon thnh ................................... 114Hnh 4.11 Thit kmt mch sn gin ........................................................... 115Hnh 4.12 Chn cng cthit k ......................................................................... 115Hnh 4.13 Ca sthit kmch s ...................................................................... 116Hnh 4.14 Lu thit k ........................................................................................ 116Hnh 4.15 Chn linh kin .................................................................................... 117Hnh 4.16 Cc linh kin c chn ................................................................ 118Hnh 4.17 t tn pin cho thit k ....................................................................... 118Hnh 4.18 Thit khon chnh ............................................................................ 119Hnh 4.19 Ca strnh bin dch report .............................................................. 120Hnh 4.20 Ca smapped pin gia thit kv FPGA ......................................... 122Hnh 4.21 Ca sgn pin .................................................................................... 122


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Hnh 5.5 ng dn cha tn ti ........................................................................ 170Hnh 5.6 Add cc file lin quan n project ........................................................ 171Hnh 5.7 Chn tn FPGA .................................................................................... 171Hnh 5.8 Thit lp thng s EDA ........................................................................ 172Hnh 5.9 Project mi c to ............................................................................ 173Hnh 5.10 Ca sQuartus sau khi project mi c to ..................................... 173Hnh 5.11 Mch sn gin ............................................................................... 174Hnh 5.12 Chn mi trng thit kVerilog ....................................................... 174Hnh 5.13 Ca sthit kVerilog ....................................................................... 175Hnh 5.14 Lu thit k ........................................................................................ 175Hnh 5.15 M tthit k ..................................................................................... 176Hnh 5.16 Chn template Verilog ....................................................................... 176Hnh 5.17 Add file Verilog lin quan .................................................................. 177Hnh 5.18 Chng dn .................................................................................... 178Hnh 5.19 Ca ssau qu trnh bin dch ............................................................ 179Hnh 5.20 Ca smapped pin gia thit kv FPGA ......................................... 181Hnh 5.21 Ca sgn pin .................................................................................... 181Hnh 5.22 Ca slit k danh sch pin ca FPGA .............................................. 182Hnh 5.23 Ca ssau gn pin ............................................................................. 182Hnh 5.24 Dng Microsoft Excel to file gn pin ........................................... 183Hnh 5.25 Import file gn pin .............................................................................. 184Hnh 5.26 File gn pin to sn bi Altera ............................................................ 185Hnh 5.27 To waveform .................................................................................... 186Hnh 5.28 Ca sto waveform .......................................................................... 186Hnh 5.29 Nhp tn signal ca thit k ................................................................ 187Hnh 5.30 Dng chc nng Node Finder ............................................................. 187


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Hnh 5.31 To input waveform ........................................................................... 188Hnh 5.32 To mc logic "1" .............................................................................. 188Hnh 5.33 Mc logic "1" c to .................................................................. 189Hnh 5.34 Thit lp chchsimulation ............................................................... 189Hnh 5.35 Waveform sau khi chy m phng ..................................................... 190Hnh 5.36 Np thikln FPGA ........................................................................ 191Hnh 5.37 Thit lp cng giao tip gia kit DE2 v Computer ............................ 191Hnh 5.38 Chn cu hnh np thit k ................................................................. 192Hnh 5.39 Thit kchnp ln FPGA bng AS mode .................................... 192Hnh 5.40 Chn loi ROM tng ng ................................................................. 193Hnh 5.41 Chn file thit k.pof ......................................................................... 194Hnh 5.42 Mt mch latch RS ............................................................................. 199Hnh 5.43 Mch thc hin trn FPGA cho mch RS latch .................................. 201Hnh 5.44 Mch D latch ...................................................................................... 202Hnh 5.45 Mch master-slave D flipflop ............................................................. 203Hnh 5.46 Mch v dng sng ng vo cho phn 4 ............................................. 204Hnh 5.47 Mt bm ng b4 bit .................................................................. 206Hnh 5.48 Dng Tool to Mega Wizard .............................................................. 215Hnh 5.49 To mt Mega mi ............................................................................. 216Hnh 5.50 Chn cc thng snhhnh v ........................................................... 217Hnh 5.51 Chn thng snhtrn hnh .............................................................. 218Hnh 5.52 Gn registers cho inputs ..................................................................... 219Hnh 5.53 Khng to gi trban u cho SRAM ................................................. 219Hnh 5.54 Simulation library ............................................................................... 220Hnh 5.55 Chn cc loi dliu cn to ra .......................................................... 221Hnh 5.56 Add dliu to ra vo project hin hnh ............................................ 221


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Hnh 6.51 Chn v thit lp thng scho timer .................................................. 331Hnh 6.52 Chn interrupt request ........................................................................ 331Hnh 6.53 JTAG UART Core Register Map ....................................................... 333Hnh 6.54 Data Register Bits .............................................................................. 333Hnh 6.55 Control Register Bits .......................................................................... 333Hnh 6.56 Schu k cho mi lnh ....................................................................... 335Hnh 6.57 Schu k cho mi lnh ....................................................................... 336Hnh 6.58 Schu k cho mi lnh ....................................................................... 337Hnh 6.59 Exception Vector ................................................................................ 340Hnh 6.60 Thanh ghi ca Timer .......................................................................... 345Hnh 6.61 M hnh Nios System dng Avalon to External Bus Bridge ............... 351Hnh 6.62 Gin xung hot ng ca SRAM ................................................... 352Hnh 6.63 Giao tip LED 7 on ......................................................................... 353Hnh 6.64 Connection gia cc components ....................................................... 354Hnh 6.65 Giao tip vi RAM ............................................................................. 355Hnh 6.66 Giao tip vi RAM v LED 7 on .................................................... 357

Hnh 7.1 Ca sModelSim ................................................................................. 360Hnh 7.2 Ca sto project mi ......................................................................... 361Hnh 7.3 Ca sin thng tin cho project ......................................................... 361Hnh 7.4 To new file ......................................................................................... 362Hnh 7.5 in thng tin cho new file .................................................................. 362Hnh 7.6 Ca ssau khi to project .................................................................... 363Hnh 7.7 Ca sdng cho m tthit k............................................................. 363Hnh 7.8 M tthit kD-Flipflop ...................................................................... 364Hnh 7.9 To new file ......................................................................................... 364


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Hnh 7.10 M tTestbench cho thit k .............................................................. 365Hnh 7.11 Lu m ttestbench ........................................................................... 365Hnh 7.12 Add file Testbench vo project ........................................................... 366Hnh 7.13 Chng dn n file Testbench ...................................................... 366Hnh 7.14 Ca sWorkspace sau thit k ........................................................... 366Hnh 7.15 Compile thit k ................................................................................. 367Hnh 7.16 Compile thnh cng ........................................................................... 367Hnh 7.17 Thit lp m phng ............................................................................ 368Hnh 7.18 Chn thit kcn m phng ............................................................... 368Hnh 7.19 Chn tn hiu dng sng cn quan st ................................................. 369Hnh 7.20 Ca sdng sng ............................................................................... 370Hnh 7.21 Thit lp thi gian chy m phng ..................................................... 370Hnh 7.22 Chy m phng .................................................................................. 370Hnh 7.23 Nhn "No" .......................................................................................... 371Hnh 7.24 Dng sng sau m phng ................................................................... 371Hnh 7.25 M tthit kD-Flipflop .................................................................... 372Hnh 7.26 Thit lp thng scho qu trnh synthesis .......................................... 373Hnh 7.27 Thit lp thng s ............................................................................... 374Hnh 7.28 Thmc sau qu trnh synthesis ......................................................... 375Hnh 7.29 Hai file quan trng c to ra ........................................................... 375Hnh 7.30 Ca sModelSim ............................................................................... 376Hnh 7.31 To project mi .................................................................................. 376Hnh 7.32 in thng tin cho project mi ........................................................... 377Hnh 7.33 Add file thit kc sn ....................................................................... 378Hnh 7.34 Chng dn n file Verilog netlist ................................................ 378Hnh 7.35 To file m tthit kmi ................................................................. 378


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Hnh 7.36 in thng tin cho new file ................................................................ 379Hnh 7.37 Ca sm tthit kc mra ....................................................... 379Hnh 7.38 M tTestbench cho thit k .............................................................. 380Hnh 7.39 Compile thit k ................................................................................. 380Hnh 7.40 M tthit kthnh cng ................................................................... 381Hnh 7.41 Thit lp m phng ............................................................................ 381Hnh 7.42 Ca sthit lp m phng .................................................................. 382Hnh 7.43 ChLibraries cho thit k ................................................................... 383Hnh 7.44 File SDF c gi trong Verilog netlist .............................................. 384Hnh 7.45 Chn thit kcn chy m phng ....................................................... 385Hnh 7.46 Ca swaveform mra ..................................................................... 385Hnh 7.47 Chn tn hiu cn xem waveform ....................................................... 386Hnh 7.48 Ca sdng sng m phng ............................................................... 387Hnh 7.49 Thit lp thi gian chy m phng .................................................... 387Hnh 7.50 Chy m phng .................................................................................. 387Hnh 7.51 Nhn "No" .......................................................................................... 388Hnh 7.52 Dng sng sau m phng ................................................................... 388Hnh 7.53 Mli project ..................................................................................... 390Hnh 7.54 Chng dn project cn m............................................................ 390Hnh 7.55 Ca sTranscript ............................................................................... 391Hnh 7.56 Nhp dng lnh nhtrn .................................................................... 391Hnh 7.57 Nhp dng lnh nhtrn .................................................................... 391Hnh 7.58 Nhp dng lnh nhtrn .................................................................... 392


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MC LC BNG

Bng 6.1 Thao tc htrbi Nios II ALU .......................................................... 235Bng 6.2 Cc thanh ghi a dng ca NIOS II...................................................... 242Bng 6.3 Cc bit v tn ca thanh ghi iu khin ................................................ 244Bng 6.4 Cho bit chi tit cc trng c nh ngha trong thanh ghi status ..... 245Bng 6.5 Cc trng ca thanh ghi iu khin estatus ........................................ 247Bng 6.6 Cc trng ca thanh ghi iu khin bstatus ........................................ 247Bng 6.7 Nhm lnh chuyn dliu ................................................................... 256Bng 6.8 Lnh logic v shc ............................................................................ 257Bng 6.9 Cc lnh di chuyn ............................................................................... 259Bng 6.10 Cc lnh so snh ................................................................................ 260Bng 6.11 Lnh dch v xoay .............................................................................. 261Bng 6.12 Nhm lnh nhy v gi hm khng iu kin .................................... 262Bng 6.13 Nhm lnh nhy c iu kin ............................................................. 263Bng 6.14 Nhm lnh iu khin khc ................................................................ 264Bng 6.15 Cc kiu dliu Nios II ..................................................................... 264Bng 6.16 M ha trng OP ca cc tlnh ..................................................... 269Bng 6.17 M ha trng OPX ca cc tlnh loi R ........................................ 270Bng 6.18 Danh sch cc lnh v lnh tng ng ........................................... 271Bng 6.19 Danh sch cc macro hin hnh ......................................................... 272


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Chng 1. Kit DE2 Development and Education Board

1.1 Tng quan vKit DE2Mc ch ca Kit DE2 l cung cp cho sinh vin mt phng tin ti u

nghin cu vkthut s, cu trc my tnh v FPGA. Kit ny sdng nhng cng

nghmi nht cvphn cng ln cng cCAD (Computer Aid Design) gip

khng chsinh vin m cn cgio vin c thnghin cu c nhiu ng dng

khc nhau. Kit cung cp nhiu c im ph hp cho cng vic nghin cu cng

nh pht trin nhng h thng s thng thng ln phc tp trong phng thnghim ca cc trng i hc.

1.2 c im ca kit DE2Di y l hnh nh ca Kit DE2. N thhin bmt trn ca Kit cng nh

vtr ca nhng linh kin trn Kit.

Hnh 1.1 Board mch DE2

Kit DE2 mang nhng c im cho php ngi sdng c th thit k t

nhng mch in n gin cho n nhng thit kphc tp nhmultimedia.


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Kit DE2 gm nhng linh kin chnh sau:

Chip Cyclone II 2C35 FPGA 672 pins. Tt cnhng linh kin trn kitu c kt ni sn vi nhng pin ca FPGA, iu ny cho php ngi sdng

c thiu khin tt cnhng linh kin cng nhng dng ca chng.

Rom EPCS16 Dng thit lp cu hnh ban u cho thit b, hotng ni tip.

USB Blaster Dng ci t chng trnh tcomputer cho FPGA, htrhai mode : JTAG v AS ( Active Serial ).

512 Kbyte SRAM 8 Mbyte SDRAM 4 Mbyte Flash memory Khe cm thnhSD card. 18 toggle switches 4 push-button switches 18 red LEDs 9 green LEDs LED 7 on (7-segments displays) LED hin thk tdng LCD (16x2 character displays) Ngun xung clock 50 MHz v 27 MHz. 24-bit CD-quality audio CODEC vi nhng u cm line-in, line-out, v

microphone-in.

VGA DAC (10-bit high-speed triple DACs) vi u cm VGA-out. TV Decoder ( NTSC/PAL) vi u cm TV-in. Giao tip chun RS-232 vi u cm 9 pin. Giao tip chun PS/2 cho chut v bn phm. Giao tip USB 2.0 ( chost ln device )


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35 embedded multipliers 4 PLLs 475 I/O pins FineLine BGA 672-pin package.

Serial Configuration device v USB Blaster circuit

Rom EPCS16 Serial Configuration device USB Blaster for programing v user API control JTAG v AS programming modes

SRAM:

512- Kbyte SRAM memory chip c tchc nhl 256K x 16 bits C thtruy cp nhl bnhcho vi xl Nios II hoc truy cp

thng qua bng iu khin Control Panel.

SDRAM:

8-Mbyte Single Data Rate Synchronous Dynamic RAM. c tchc nhl 1M x 16 bits x 4 banks C thtruy cp nhl bnhcho vi xl Nios II hoc truy cp


Flash memory:

4-Mbyte NOR Flash memory 8-bit data bus C thtruy cp nhl bnhcho vi xl Nios II hoc truy cp


Khe cm thnhSD card:

Truy xut SD card bng mode SPI


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C thtruy cp nhl bnhcho vi xl Nios II vi DE2 SDcard driver.

Pushbutton swiches:

4 pushbutton switches Hi phc li tn hiu bng mch Schmitt trigger. trng thi bnh thng, tn hiu mc cao; khi switch c

nhn, tn hiu to ra mt xung tch cc mc thp v hi phc li

trng thi bnh thng mc cao.

Toggle switches:

18 toggle switches Khi switch vtr DOWN ( gn cnh ca Kit DE2 ) th tn hiu

mc thp; ngc li th tn hiu mc cao.

Clock inputs:

Ngun xung clock 50 MHz Ngun xung clock 27 MHz C thsdng ngun xung clock ngoi thng qua chn SMA.

Audio CODEC:

Wolfson WM8731 24-bit sigma-delta audio CODEC u cm Line-in, Line-out, Microphone-in Tn sly mu : 8-96 KHz ng dng cho MP3 players, recorders, PDAs, smart phones,

voice recorders

VGA output:

S dng ADV7123 240-MHz triple 10-bit high-speed videoDAC

Vi u cm 15-pin high-density D-sub


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Cung cp giao tip song song n bvi xl; htrNios II biTerasic driver.

H tr Programmed I/O (PIO) v Direct Memory Access(DMA).

Cng ni tip :

Mt cng giao tip RS-232 Mt cng giao tip PS/2

Cng giao tip hng ngoi ( IrDA)

Btruyn nhn tn hiu 115.2 kb/s Dng iu khin LED 32 mA c bo vbi mt lp EMI IEC825-1 Class 1 eye safe Tn hiu ng vo c xc nhn bi tch cc cnh.

Hai u ni mrng ( 40 pin)

2x40 pin ca 2 u ni c kt ni vi 72 pin ca Cyclone III/O pins v 8 pin power v mass.

u ni 40 pin ny c th tng thch vi cable chun 40 pinc dng cho cng IDE.

c bo vbi diode v in tr.1.3 Ti liu htr

Phn mm i km vi Kit DE2 bao gm Quartus II Web Edition CAD v

Nios II Embedded Processor. Ngoi ra mt shng dn v ng dng n gin

gip sinh vin v gio vin hiu r vng dng ca Kit trong ging dy v nghin

cu.

Thng thng nhng Kit FPGA c sn xut cho mc ch gio dc s

cung cp nhiu c tnh v phn cng cng nh cng cCAD c th to ra


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Hnh 1.4 ng dng giao tip USB

Sdng giao tip USB trn Kit DE2.

Sdng trnh iu khin thit bchv tcho Nios II

Cung cp minh ha vSRAM video buffer.

1.6.3 ng dng to bi ht karaoke v my nghe nhc

Hnh 1.5 ng dng trong xl m thanh

CD audio 24 bit cht lng cao


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Hnh 2.1 Mn hnh VGA mc nh

Bt switch SW17 xung vtr DOWN, ta snghe mt m thanh tn

s1-KHz

Bt switch SW17 ln vtr UP v kt ni u ra ca my nghe nhc (

radio, ipod, MP3 ) vo cng giao tip Line-in trn Kit DE2; Sau khi

kt ni xong, ta snghe c m thanh ca my nghe nhc thng qua

headphone kt ni vo Line-out trc .

Ta c thkt ni mt microphone vo cng giao tip Microphone-in

trn Kit DE2; theadphone ta c thnghe c ging ni ca ta chn

ln trong ting nhc.

2.2 Hng dn ci t USB-Blaster DriverBo mch DE2 c ng gi bao gm tt cnhng phn cn thit cho hot

ng ca n ngoi mt bngun adapter 9 volt v cp kt ni USB. Bo mch c

bo v bi m lp knh nhm hn ch s hhng khng mong mun trong qu

trnh sdng.

Cm ngun adapter 9 volt vo bo mch DE2. Sdng cp USB kt ni

cng USB (cng nm lin knt mngun (power) trn bo mch DE2 vi cng


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Hnh 2.3 Chng dn cho driver

Trnh iu khin USB-Blaster c sn bn trong phn mm ci t Quartus II,

do ta chn Install from a specific location v nhn Next ra mn hnh nh

trong Hnh 2.4.



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By gi, ta chn Search for the best driver in these locations v nhn

Browse xut hin hp thoi nhtrong Hnh 2.5. Tm trnh iu khin mong

mun nm trong thmc C:\altera\90\quartus\drivers\usb-blaster\x32. Nhn OK,

sau mn hnh schuyn vnhtrong Hnh 2.4, nhn Next. Lc ny th vic ci

t c bt u, nhng sc mt hp thoi nhtrong Hnh 2.6 sxut hin

thng bo rng trnh iu khin cha hon thnh kim tra Window Logo. Nhn

Continue Anyway.



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Hnh 2.6 Khng cn kim tra driver

By gitrnh iu khin sc ci t nhtrong Hnh 2.7. Nhn Finish v

ta c thbt u sdng bo mch DE2.

Hnh 2.7 Driver c ci t thnh cng

2.3 Thit lp cu hnh ban u v thay i cu hnh mi cho CyclonII FPGA

Qui trnh ti mt mch thit ktmy chln Kit DE2 c m tchi tit

trong cc phn hng dn thc hnh hthng s, verilog hoc kin trc my tnh

nng cao trong Chng 4. , Chng 5. hoc Chng 6. . Ta nn c phn hng


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dn ny trc v tham kho nhanh nhng thng tin di y hiu r qui trnh s

dng Kit.

Trn kit DE2 c mt bnhEEPROM hot ng ni tip, bnhny cha

dliu khi to cu hnh ban u cho Cyclon II FPGA. Dliu ny stng

c ti ln FPGA tEEPROM mi khi ngun in ca Kit DE2 c cung cp.

Sau khi ngun in c cung cp, FPGA siu khin cc thit btrn Kit DE2

(leds, switchs,) hot ng vi dliu khi to. Sau , ta hon ton c ththay

i cu hnh khi to trn bng vic ti trc tip ln FPGA mt d liu, mt

chng trnh do ta thit kbng phn mm Quartus II. Bn cnh ta cng c th

thay i cu hnh khi to bng vic thay i dliu trn bnhEEPROM. Hai

phng php trn sc lit k di y:

JTAG ( Joint Test Action Group) programming: Trong phng php

ti chng trnh ny, chui bit cu hnh d liu sc ti trc tip

ln Cyclone II FPGA. FPGA sgicu hnh ny cho n khi ngun

in khng cn c cung cp ln Kit DE2 na.AS ( Active Serial) Programming: Trong phng php ti chng

trnh ny, chui bit cu hnh s c ti ln b nh EEPROM

EPCS16 hot ng ni tip. Dliu lu trtrn bnhny cnh

khng bmt hoc xa khi khng cn ngun in cung cp. Mi khi

ngun in c cung cp ln Kit DE2, dliu tbnhEEPROM

ny stng c ti ln Cyclone II FPGA.

Tng bc ca qu trnh thc thi vic ti chng trnh bng JTAG v AS s

c m tdi. chai phng php trn, Kit DE2 c kt ni vi my tnh

chthng qua cap USB. Vi kt ni ny, Kit DE2 sc nhn dng bi my tnh

chnhl mt thit bUSB Blaster. Trnh iu khin (driver) dng nhn dng

v giao tip gia my tnh chvi thit bUSB Blaster cn c ci t trn my


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tnh ch ( trnh by trong phn 2.2). Thit lp cu hnh mi cho FPGA tphn

mm QuartusII trn my tnh thng qua JTAG mode:

Hnh 2.8 Thit lp cu hnh cho FPGA thng qua JTAG mode

ti mt chui bit dliu cu hnh ln FPGA, ta cn thc thi nhng bc

sau:

1- Cung cp ngun cho Kit DE2.2- Kt ni cp USB n cng USB Blaster trn Kit DE2.3- Bt switch RUN/PROG vvtr RUN (pha tri ca Kit).4- S dng cng cProgrammer trn phn mm Quartus II ti file

cha chui bit dliu cu hnh c nh dng .sof ln FPGA.


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2.3.1 Thit lp cu hnh ban u cho FPGA thng qua vic np cu hnh cho bnhEPPROM EPCS16 bng AS mode:

Hnh 2.9 Thit lp cu hnh cho FPGA thng qua AS mode

ti mt chui bit dliu cu hnh ln bnhEPPROM EPCS16, ta cn

thc thi nhng bc sau:

1- Cung cp ngun cho Kit DE2.2- Kt ni cp USB n cng USB Blaster trn Kit DE2.3- Bt switch RUN/PROG vvtr PROG (pha tri ca Kit).4- S dng cng cProgrammer trn phn mm Quartus II ti file

cha chui bit d liu cu hnh c nh dng .pof ln b nh

EPPROM EPCS16..

5- Khi qu trnh ti chng trnh hon thnh, bt li switch RUN/PROGvvtr RUN v ngt ngun khi Kit, sau li cung cp ngun li.

Thao tc ny s lm cho d liu cu hnh mi t bnhEPPROM

EPCS16 c tng np ln FPGA. V dliu cu hnh mi ny s

c xem nhdliu cu hnh khi to mi cho Kit DE2 mi ln ta

cung cp ngun cho n.


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2.4 Smch v hot ng ca cc linh kin trn Kit DE22.4.1 Switches (cng tc) v Button (nt nhn)

Kit DE2 cung cp bn Switch nhn. Khi khng c nhn tn hiu ng ra

ca nhng Switch ny mc cao, khi Switch c nhn gi trtn hiu ng ra ca

mi Switch stch cc mc thp v sc phc hi trli gi trmc cao nhc

nhmch Schmitt Trigger ngay khi Switch c th ra. Bn tn hiu ng ra ca

mch Schmitt Trigger c gi l KEY0, , KEY3 c kt ni trc tip n pin

ca Cyclone II FPGA. Nhng tn hiu ny thch hp cho vic to tn hiu xung

clock hay tn hiu Reset cho mch.

Hnh 2.10 Chc nng chng ny cho Push button

Ngoi ra Kit DE2 cung cp thm 18 Switch bt tt hot ng nh nhng

cng tc in. Khi nhng Switch ny vtr DOWN (gn cnh ca Kit), tn hiu

ng ra ca n sin p mc thp (0Volt) v ngc li khi Switch vtr UP, tnhiu ng ra scung cp in p mc cao (3.3V). Mi tn hiu ng ra tSwitch ny

c ni trc tip n pin ca FPGA. Thng thng ta nn sdng in p mc

thp iu khin hot ng ca mch thit k. Di y l smch kt ni

ca Switch trn Kit DE2 v danh sch lit k nhng tn hiu ng ra tSwitch c

kt ni n nhng Pin tng ng ca Cyclone II FPGA.


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Hnh 2.11 Mch thit kca switches v push button


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Hnh 2.12 Mapped pins gia switches v FPGA

Hnh 2.13 Mapped pins gia Push button v FPGA


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2.4.2 LedsKit DE2 cung cp 27 LEDs, trong c 18 LEDs ( c t ngay trn 18

Switch bt tt), 8 LEDs xanh ( c t ngay trn 4 Switch nhn) v LED xanh th

9 nm ngay gia LED 7 on. Mi LED c iu khin trc tip bi mt tn hiu

tpin ca Cyclone II FPGA; LED sng khi tn hiu ny c in p mc cao v

ngc li LED tt khi tn hiu c in p mc thp. Di y l smch kt ni

LED v danh sch lit k nhng tn hiu ng vo ca LED c kt ni n nhng

Pin tng ng ca Cyclone II FPGA.

Hnh 2.14 Mch thit kca Leds


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Hnh 2.15 Mapped pins gia LEDs v FPGA


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2.4.3 LED hin thby onKit DE2 cung cp 8 LED hin thby on. LED sng khi tn hiu vo mc

thp v LED tt khi tn hiu vo mc cao. By on hin thtrn LED c nh

st0 n 6, vi vtr c thhin nhhnh di, ch l du chm (.) trn mi

LED khng c kt ni nn khng thsdng.

Hnh 2.16 Led 7 on

Di y l smch kt ni LED by on v danh sch lit k nhng

tn hiu ng vo ca LED by on c kt ni n nhng Pin tng ng ca

Cyclone II FPGA.


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Hnh 2.18 Mapped pins gia LEDs 7 on v FPGA

2.4.4 LED hin thLCDKhi LED hin thLCD vi kiu chmc nh c to sn dng hin

thnhng k tbng vic gi nhng cu lnh thch hp n khi iu khin hin


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thLCD HD44780. Ta c th tm hiu chi tit hot ng v chc nng ca LCD

trn Datasheet ca n. Smch kt ni ca LED LCD v nhng tn hiu ng

vo ca LED LCD n nhng Pin tng ng ca FPGA v danh sch lit k nhng

nhng tn hiu ng vo ca LED LCD n nhng Pin tng ng ca Cyclone II

FPGA.

Hnh 2.19 Mch thit kca LCD


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Hnh 2.20 Cu to LCD

Hnh 2.21 Mapped pins gia LCD v FPGA


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Hnh 2.23 Bm a ch

Bnhlu gidliu hin th(DDRAM):

DDRAM c dng lu gik t(c m ha bi mt gi tr8 bit) hin

thtrn LCD. Hnh di y thhin stng ng gia a chca DDRAM vi

vtr hin thca n trn LCD(2x16)

Hnh 2.24 Bnhlu gidliu hin th

Gishin thk tno ln vtr hng th2, ct th15 th ta phi

ghi 8 bit m ha cho k t vo nhc a ch4E (BCD) trong DDRAM,

nhvy a chca AC sl:

Mun ghi dliu vo DDRAM, trc ht ta phi nh a chca DDRAM

m ta mun dliu sc lu vo ( cng chnh l vtr m k t sc

hin th trn LCD). Vic nh a ch ca DDRAM thng qua b m a ch


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AC[6:0], sau khi a chca DDRAM c xc nh, ta sghi dliu ( y

chnh l 8 bits m ha ca mu k tm ta mun hin th) vo thng qua 8 bits

DB[7:0].

BnhROM lu gimu k t( Character Generator ROM Pattern)

B nh ROM ny c dung lng 4096x8 bits nn c 12 ng a ch

A[11:0] gii m. to mt mu k t5x8 th ta cn 8 nh8 bits. Gisnh

trong hnh di lu gimt mu k tb trong ROM, nh sn xut phi dng

8 nhc a cht[011000100000] n [011000100111]. Ni dung ca mi

nhgm 8 bits O[7:0] c gn gi trnhhnh di ( Nhng bit O[7:5] c

gn bng 0 ). Khi mun hin thk tb ra mn hnh LCD, ta ghi 8 bits dliu

m ha ca k tb vo bnhDDRAM (ghi gi trvo DDRAM trnh by

trong phn DDRAM), 8 bits d liu m ha chnh l 8 bits gi tr a ch

A[11:4] ca ROM, vy ta phi ghi d liu 8 bits [01100010] vo trong b nh

DDRAM k tb hin thln LED. Ta thi qu trnh c dliu t8 nh

trong ROM xut ra LED nhthno. Ta c thhnh dung n gin nhsau,sau khi nhn 8 bits dliu tDDRAM, khi iu khin shiu 8 bits chnh l 8

bits A[11:4] ca ROM, n s tng c lin tc (ni tip) d liu t 8 nh

trong ROM m bt u ta chA[11:4][0000] v chuyn n thnh mt chui d

liu song song 8x8 bits bng b chuyn i ni tip sang song song v xut ra

LED.


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Hnh 2.25 Bnhlu gimu k t

Di y l bmu k t c nh sn xut to sn trong ROM ca khi

iu khin v 8 bits dliu m ha ( ta dng ghi vo bnhDDRAM) tngng cho tng mu k t. ( 8 bits dliu ny cng chnh l A[11:4] ca a chm

mu k t c lu trong ROM).


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Hnh 2.26 Bnhlu gitt ccc mu k t


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V d:by gita mun hin ths9 ln LCD hng 2, ct 14 th trc

tin ta phi ghi gi tra chhexadecimal 4D [01001101] vo bm a chAC

sau ghi 8 bits dliu m ha ca k t9 l [00111001].

Bto k tRAM (CGRAM)

RAM c dung lng 64x8 bits nn c 5 ng a chgii m A[5:0].

CGRAM cho php ngi sdng tto mu k tcho ring mnh. V chc dung

lng 64x8 bits nn ta chc th to c ti a 8 k t5x8 hoc 4 k t 5x10.

Di y l bng m tstng quan gia a chca CGRAM vi DDRAM m

biu khin sda vo kim sot hot ng.

Hnh 2.27 Bto mu k t


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hiu ngha ca bng trn, ta sdng mt th dminh ha. V y l

CGRAM cho php ngi sdng tto mu k tring nn trc ht ta phi to

mu k tm mnh mun ( m khng c sn trong CGROM nh sn xut cung

cp). Gista mun to mu k tR 5x8 nhtrn hnh v. V y l mu k t

5x8 nn scn 8 nh trong CGRAM lu gi, y lu mu k tR vo 8

nhm bt u bng nhc a chA[000000] v kt thc l nhc a ch

A[000111] vi ni dung ca tng nhnhbng pha bn phi (CGRAM data)

tng trng cho gi tr1 c lu trong CGRAM. Nhvy ta to xong mt

mu k ttrong CGRAM.

Gita mun hin thk t ra LCD, vy lm sao ta bit c 8 bits dliu

c m ha cho mu k ttrn ghi vo DDRAM cho vic xut ra. Vic m

ha ny khi iu khin stng ngm hiu nhsau: N ly 3 bits a chca

CGRAM A[5:3] lm 3 bits thp D[2:0] ca 8 bits m ha, 4 bits cao D[7:4] ca 8

bits m ha sgn bng 0 , cn bit th4 D[3] n skhng quan tm. Nhvy 8

bits m ha cho mu k tR m ta va to trn l D[0000x000]. Vy hinthk tR trn ta chcn ghi 8 bits c gi tr[0000x000] ( trong x c thl

0 hay 1) vo bnhDDRAM. ( ghi gi trvo DDRAM trnh by trong

phn DDRAM).

Tp lnh ca LCD:


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Hnh 2.28 Tp lnh LCD

2.4.5 Ng vo xung ClockKit DE2 cung cp hai ngun tn hiu xung Clock 27 MHz v 50 MHz. Ngoi

ra ta cng c thcung cp ngun xung Clock tbn ngoi thng qua cng ng vo

SMA. Smch kt ni ngun xung Clock v danh sch lit k nhng tn hiu

ngun xung Clock kt ni n nhng Pin tng ng ca Cyclone II FPGA.

Hnh 2.29 Mch thit kca ng vo xung Clock


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Hnh 2.30 Mapped pins gia ng vo xung Clock v FPGA

2.4.6 Expansion Header (Jac cm mrng)Kit DE2 cung cp thm hai expansion headers 40-pins. Mi header c kt

ni trc tip n 36 pins ca Cyclone II FPGA, 1 pin ngun DC +5V (VCC5), 1pin ngun DC +3.3V (VCC33) v 2 pins GND. Hnh di m t mt phn ca

mch cho 4 pins ca mi expansion headers, mch y sgm 40 pins cho mi

expansion headers. Mi pin texpansion header c kt ni n hai diode v mt

in trdng bo vkhi hin tng qu p hay hp.


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Hnh 2.31 Mch thit kgiao tip gia PIO v FPGA

Di y l bng lit k 80 pins ca hai expansion header v 80 pins caFPGA c kt ni tng ng .


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Hnh 2.32 Mapped pins gia pin PIO v FPGA

2.4.7 VGABo mch DE2 c mt ng raVGA D-SUB 16 pin. Nhng tn hiu ng b

VGA c cung cp trc tip tFPGA Cyclone II, v mt con chip xl tn hiu

ssang tng tvideo DAC ADV7123 vi tc cao 10 bit c dng to ra

nhng tn hiu tng t (, xanh lam, xanh lc). Smch VGA c cho


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Hnh 2.33 v c th h tr phn gii ln n 1600x1200 pixels tc

100MHz.

Hnh 2.33 Smch VGA

c tthi gian cho nhng dliu vng bVGA cng nhdliu RGB

( , xanh luc, xanh lam) c thc tm thy trn nhiu trang web vo to (v

d, ch cn tm kim trn google vi t kha VGA signal timing). Hnh 2.34

minh ha nhng rng buc cbn vthi gian cho mi hng ( horizontal) hin

th trn mn hnh VGA. Mt tn hiu xung tch cc mc thp trong mt khongthi gian nht nh ( khoang thi gian a nhtrong hnh) c cp n tn hiu ng

vo ng bhng (hsync) ca mn hnh cho bit du hiu kt thc mt hng d

liu v bt u mt hng dliu ktip. Nhng ng vo RGB trn mn hnh phi

tt ( iu khin v0V) trong mt khong thi gian gi l back porch (b) sau khi

xung tn hiu ng vo ng bhng (hsync) xut hin, v tip tc theo sau khong


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thi gian (b) ny l khong thi gian hin th(c). Trong sut khong thi gian hin

th, tn hiu RGB iu khin mi pixel hin thdc theo hng. Cui cng, trong

mt khong thi gian gi l front porch (d) nhng tn hiu RGB phi tt i ln

na trc khi tn hiu xung ng vo ng bhng (hsync) ktip xut hin bt

u mt hng mi. c tvthi gian cho tn hiu ng bct (vsync) c trnh

by tng ttrong Hnh 2.34, n chkhc l xung tn hiu vsync cho bit du

hiu kt thc mt khung (frame) mn hnh v bt u mt khung mn hnh ktip.

Hnh 2.35 v Hnh 2.36 m tnhng khong thi gian ng bhng v ct a, b, c

v d ng vi nhng phn gii khc nhau.

Thng tin chi tit vvic sdng chip Video DAC ADV7123 c m tr

trong datasheet ca n m ta c thtm thy trn website ca nh sn xut. Vic

gn pin gia FPGA Cyclone II v chip ADV7123 c lit k trong Hnh 2.37.

Hnh 2.34 Gin nh thi ca tn hiu HSYNC


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Hnh 2.35 M tnh thi cho vic ng bhng

Hnh 2.36 M tnh thi cho vic ng bct


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Hnh 2.37 Mapped pins gia ADV7123 v FPGA

2.4.8 Audio CODEC 24-bitBo mch DE2 cung cp vic xl m thanh cht lng cao 24 bit thng qua

mt chip Wolfson WM8731 audio CODEC (encoder/DECcoder). Con chip ny htrng vo microphone, ng vo v ng ra c khnng iu chnh tc ly mu

t8 kHz n 96 kHz. Chip WM8731 c kt ni vi cc pin trn FPGA Cyclone

II thng qua giao thc giao tip bus ni tip I2C. Smch xl m thanh c

thhin trn Hnh 2.38, v vic gn pin trn FPGA c lit k trong bng Hnh

2.39. Thng tin chi tit vcch thc sdng chip WM8731 CODEC c trnh

by trn datasheet ca n v ta cng c thtm thy trn website ca nh sn xut.


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Hnh 2.38 Mch thit kca Audio Codec

Hnh 2.39 Mapped pins gia Audio Codec v FPGA

2.4.9 Cng ni tip RS-232Bo mch DE2 sdng chip truyn nhn dliu MAX232 v cng giao tip

D-SUB 9 pin cho vic giao tip RS-232. Thng tin chi tit vcch thc sdng


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chip MAX232 cng nhcng giao tip D-SUB c trnh by trn datasheet ca

n v ta cng c thtm thy trn website ca nh sn xut. Hnh 2.40 m tmch

kt ni cng ni tip RS-232, v vic gn pin cho FPGA Cyclone II c lit k

trong Hnh 2.41

Hnh 2.40 Mch thit kgiao tip gia RS-232 v FPGA

Hnh 2.41 Mapped pins gia RS-232 v FPGA

2.4.10 Cng ni tip PS/2Bo mch DE2 c mt giao tip chun PS/2 v mt cng kt ni PS/2 cho

bn phm hoc con chut my tnh. Hnh 2.42 m tmch kt ni ca PS/2. Hng

dn s dng chut PS/2 hay bn phm PS/2 c thc tm thy trn rt nhiu

website. Vic gn pin gia cng kt ni PS/2 c chra trn Hnh 2.43.


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Hnh 2.42 Mch thit kgiao tip gia cng PS/2 v FPGA

Hnh 2.43 Mapped pins gia cng PS/2 v FPGA

2.4.11 Mch iu khin mng Fast EthernetBo mch DE2 cung cp vic h tr kt ni Ethernet thng qua chip iu

khin Davicom DM9000A Fast Ethernet. Chip DM9000A bao gm mt giao tip

vi mt vi x l thng thng, mt SRAM 16 Kbytes, mt khi iu khin truy

xut truyn thng (MAC), v mt b truyn nhn d liu 10/100M PHY. Hnh

2.44 m tmch thc hin vic giao tip Fast Ethernet. Hnh 2.45 lit k vic gn

pin gia chip DM9000A v FPGA Cyclone II. Thng tin chi tit vcch thc s

dng chip DM9000A c trnh by trn datasheet ca n v ta cng c th tm

thy trn website ca nh sn xut.


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Hnh 2.44 Mch thit kgiao tip gia DM9000A v FPGA


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Hnh 2.45 Mapped pins gia DM9000A v FPGA

2.4.12 TV DecoderBo mch DE2 c trang b mt chip m ha thit b tng t TV

ADV7181. Chip ADV7181 l mt mch m ha video tch hp c chc nng d

tm v chuyn i mt tn hiu analog (tng t) truyn hnh c gii nn chun(NTSC, PAL, SECAM) sang tn hiu dliu digital (s) 4:2:2 c khnng tng

thch vi CCIR601/CCIR656 16bit/8bit. Chip ADV7181 tng thch c vi

nhiu thit bVideo khc nhau bao gm u DVD, thit btruyn thng cng nh

camera theo di.

Nhng gi trca nhng thanh ghi trong chip m ha TV c thc lp

trnh thng qua giao tip bus ni tip I2C c kt ni vi FPGA Cyclone II nh

trong Hnh 2.46. Vic gn pin c lit k trong Hnh 2.47. Thng tin chi tit v

cch thc sdng chip ADV7181 c trnh by trn datasheet ca n v ta cng

c thtm thy trn website ca nh sn xut.


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Hnh 2.46 Mch thit kgiao tip gia ADV7181 v FPGA


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Hnh 2.47 Mapped pins gia ADV7181 v FPGA

2.4.13 TV EncoderMc d bo mch DE2 khng c chip TV Encoder, nhng ta c thsdng

chip ADV7123 (chip ADC 10 bit tc cao) thc thi mt khi TV encoder vi

cht lng cao trong phn xl tn hiu sc thc hin trong FPGA Cyclone

II. Hnh 2.48 m tskhi thc thi mt TV encoder


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Hnh 2.48 TV encoder ADV7123 v FPGA

2.4.14 USB Host and DeviceBo mch DE2 cung cp ng thi hai giao tip USB host v device bng

vic sdng mt chip iu khin USB ISP1362 ca Philips. Biu khin host v

device tng thch vi chun giao tip USB 2.0, htrvic truyn dliu vi tc

cao (12 Mbit/s) v tc thp (1.5 Mbit/s). Hnh 2.49 m tsmch kt ni

USB. Hnh 2.50 lit k vic gn pin kt ni tchip ISP1362 n FPGA Cyclone II.

Thng tin chi tit v cch thc s dng chip ISP1362 c trnh by trn

datasheet ca n v ta cng c th tm thy trn website ca nh sn xut. Phn

thch thc nht ca mt ng dng USB l lun cn mt phn mm iu khin.


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Vic kt ni pin gia cng hng ngoi v FPGA Cyclone II c lit k

trong Hnh 2.52

Hnh 2.51 Mch giao tip gia cng hng ngoi v FPGA

Hnh 2.52 Mapped pins gia cng hng ngoi v FPGA

2.4.16 BnhSDRAM/SRAM/FlashBo mch DE2 cung cp mt bnhSDRAM 8 Mbyte, mt bnhSRAM

512 Kbyte v mt bnhFlash 4 Mbyte (1 Mbyte trn mt sboard mch). Hnh

2.53, Hnh 2.54 v Hnh 2.55 m tsmch kt ni ca mi loi bnh. Vic

gn pin kt ni gia FPGA Cyclone II vi mi loi bnhc lit k trong cc

Hnh 2.56, Hnh 2.57 v Hnh 2.58. Datasheet ca mi loi bnhc thtm thy

ddng trn cc website.


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Hnh 2.53 Mch giao tip thit kgia DRAM v FPGA

Hnh 2.54 Mch giao tip thit kgia SRAM v FPGA


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Hnh 2.55 Mch giao tip thit kgia FLASH v FPGA


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Hnh 2.56 Mapped pins gia SDRAM v FPGA


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Hnh 2.58 Mapped pins gia FLASH v FPGA


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Chng 3. Hng dn ci t v sdng phn mm ControlPanel iu khin kit DE2

3.1 Hng dn ci t Control Panel iu khin Kit DE2Trnh ng dng Control Panel i km vi Kit DE2 cho php ngi sdng

iu khin tt c nhng linh kin trn Kit DE2 thng qua cng USB t mt

computer cha trnh ng dng Control Panel trn. Trong phn ny, ta sm tmt

schc nng cbn ca trnh ng dng Control Panel, sau ta sm tcu trc

ca n di dng skhi, v cui cng l m tnhng khnng ca n.

ci t trnh iu khin Control Panel, Altera cung cp cho ngi s

dng 2 file sau y:

i. DE2_USB_API.sofii. DE2_control_panel.exe

kch hot trnh ng dng Control Panel, ta cn thc hin nhng bc sau:

1- Kt ni cp USB n cng USB Blaster. Cung cp ngun 9V. Btngun ln vtr ON.

2- Chuyn switch RUN/PROGvtr RUN.3- Mphn mm Quartus II .4- Chn Tools Programmer, ta sc hnh sau:


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Hnh 3.1 Giao din cho vic cu hnh thit kln FPGA

5- Nhn chn Add File, ch ng dn n file cu hnhDE2_USB_API.sof

6- Nhn chnct Program/Configure.7- Nhn Startnp file cu hnh DE2_USB_API.sof xung FPGA.

thc thi file DE2_control_panel.exetrn computer bng cch nhp p

ln biu tng ca file. Sau khi chy xong, ta sthy mt giao din nhsau:


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Hnh 3.3 Giao tip gia Control Panel v cc thit bngoi vi trn FPGA

Trong IP thc thi chc nng iu khin. IP ny c thit ktrn FPGA.

N lin lc vi trnh ng dng DE2 Control Panel trn computer thng qua cng

USB Blaster. Giao din ha c s dng truyn lnh xung mch iu

khin. Cng vic ca IP l qun l tt cnhng yu cu v thc thi vic truyn d

liu gia my tnh v Kit DE2.

Trnh ng dng DE2 Control Panel c thc dng thay i gi trhin

thtrn LEDs by on, bt LEDs, giao tip vi bn phm PS/2, c v ghi SRAM,

Flash Memory v SDRAM, ti hnh nh ln mn hnh VGA, ti nhc vo bnh

v nghe nhc qua audio DAC. c tnh c v ghi mt byte hay ton bfile thay

n Flash Memory cho php ngi sdng pht trin nhiu ng dng multimedia (

Flash Audio Player, Flash Picture Viewer) m khng cn quan tm n cch to ra

mt Flash Memory Programmer.

3.2 Tng quan vcu trc v hot ng ca Control PanelDE2 Control Panel giao tip vi mt module in t(thit kbng ngn ng

phn cng nhVerilog hay VHDL) c bin dch v np vo Chip Cyclone II

FPGA. V Altera cung cp cho chng ta nhng module trn di dng ngn ng


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Verilog, do ta hon ton c thda vo chnh sa v thay i chc nng

hot ng ca Control Panel, tt nhin ta phi nm vng ngn ngVerilog.

Hnh di m tcu trc ca Control Panel. Mi thit bng vo hoc ng

ra u c iu khin bi mt trnh iu khin c thit k bng ngn ng

Verilog v c np ln FPGA (DE2_USB_API.sof). Vic giao tip gia nhng

trnh iu khin ny vi PC c thc hin thng qua USB Blaster. Nhn trn hnh

ta thy khi Command Controller, chc nng ca khi ny l bin dch nhng lnh

nhn tPC v thc thi nhng tc vthch hp. Nhng khi trnh iu khin cho

SDRAM, SRAM v Flash Memory c ba chn user-selectable bt ng bcng

vi mt chn Host kt ni n khi Command Controller. Kt ni gia trnh

iu khin VGA DAC n bnhca FPGA cho php hin thmt hnh nh mc

nh (Tiger) lu sn trong b nh ca FPGA. Kt ni gia trnh iu khin

Audio DAC ti mt lookup table trn FPGA to ra mt tn hiu m thanh

test c tn s1KHz.


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Hnh 3.4 Skhi giao tip gia Control Panel v cc thit bngoi vi

Ta c thkt ni nhng module ca mnh n mt trong nhng User

Ports ca trnh iu khin SRAM/SDRAM/Flash memory, sau ta c thti d

liu nhphn vo trong SRAM/SDRAM/Flash memory. Khi d liu c ti

vo trong SRAM/SDRAM/Flash memory, ta c ththit lp li cu hnh cho cc

khi trnh iu khin SRAM/SDRAM/Flash memory nhng khi ny c th

c/ghi d liu ca SRAM/SDRAM/Flash memory thng qua User Ports (

thit lp li cu hnh cho nhng khi ny i hi ta phi c kin thc vVerilog).


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3.3 Hng dn sdng Control Panel3.3.1 iu khin LEDs, LEDs by on, LCD

Chc nng cbn ca Control Panel l cho php thit lp nhng gi trhin

thtrn LEDs, LEDs by on v LCD.

Trn ca sControl Panel hnh di y, chn tab PS2 & 7-SEGnhng

gi trc thhin trn LEDs by on (HEX7-HEX0) c thc nhp vo t

nhng tng ng. nhng gi trva nhp trn hin th trn LED by on

bng cch nhn vo nt Set. hin thcc k ttrn LCD, ta c thsdng bn

phm c kt ni vi Kit DE2 thng qua cng PS/2, sau ta c thnhp k tt

bn phm ny hin thln LCD.

Hnh 3.5 Giao din Control Panel iu khin LEDs 7 on

1- Chn tab LED & LCD ta sc ca snhhnh di


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Hnh 3.6 Giao din Control Panel iu khin LEDs n

2- Ta c thbt sng mt LED bt k bng cch chnvo LED sau nhn nt Set. Ta cng c thhin thnhng k t ln LCD bng

cch nhp nhng k t ln hp LCD trn ca sControl Panel, sau nhn nt Set.

Vic thit lp gi tr hin th ln nhng thit b hin th n gin trn th

cng khng cn n mt trnh ng dng nhControl Panel, tuy nhin vi trnh ng

dng Control Panel, ta sc mt cng cn gin kim tra hot ng ca tng

linh kin trn Kit DE2, ng thi n cng c dng debug trong qu trnh thit

k.

3.3.2 Truy xut bnhSDRAM/SRAMTa c thtruy xut dliu nhc dliu tbnhhay ghi dliu vo b

nh (SDRAM/SRAM) trn Kit DE2. Di y ta s m t cch thc truy xut

SDRAM thng qua Control Panel (cch thc ny cng tng ti vi SRAM).

Chn tab SDRAM, ta snhn thy mt ca snhhnh di


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Hnh 3.7 Giao din Control Panel iu khin SDRAM

Vi Control Panel, ta c th truy xut mt t16 bits hoc truy xut

mt dy nhng tnhng nhlin tip.

ghi mt t16 bits (Random access), ta nhp a ch nhcn ghi

vo Address, tip n nhp data cn ghi vo wDATA, sau

nhn nt Write. Trong hnh trn, ta mun ghi gi tr di dng

hexadecimal 6CA vo b nh a ch 200. Sau khi ta nhn nt

Write th gi tr6CA c ghi vo nh c a ch200 ca b

nh.c mt t16 bits (Random access), ta nhp a ch nhcn c

ra, sau nhn nt Read. Trong hnh trn, ta mun c gi tr t

nhc a ch200. Sau khi ta nhn nt Readth gi tr6CA ( gis

gi trny c ghi vo tthao tc ghi) shin thtrn rDATA


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ghi mt chui nhng k tlin tip hay ni dung ca mt file vo

SDRAM (Sequential Write), ta thc hin nhng thao tc sau:

1. Nhp a ch ca nhbt u lu trni dung ca mt filevo Address.

2. Nhp chiu di ca ni dung file cn ghi vo hp Length. Nu tamun ghi ton bfile vo trong SDRAM ta chi vic chn cho

File Lengthm khng cn Nhp chiu di ca ni dung file cn

ghi vo Length.

3. Chng dn ca file data cn ghi bng cch nhn Write a Fileto SDRAMv xc nh ng dn cho file .

Control Panel cng htrghi file c ni dung c nh dng Hexa.

File nh dng Hexa l file cha nhng k t ASCII biu din

nhng gi trHexadecimal. Gis, ta c mt file cha dng nhng k

tASCII sau :0123456789ABCDEF

Dng k ttrn xc nh bn gi tr16-bit : 0123, 4567, 89AB, CDEF.

Nhng gi trny sc ghi theo tun tvo SDRAM.

c mt chui nhng k tlin tip hay ni dung ca mt file t

SDRAM (Sequential Read), ta thc hin nhng thao tc sau:

1. Nhp a chca nhbt u ca chui nhm ta mun c ravo Address.

2. Nhp chiu di ca ni dung file cn c (s byte) vo hpLength. Nu ta mun c ton bni dung trong SDRAM ( tt c


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8 Mbytes) ta chi vic chncho Entire SDRAMm khng cn

nhp chiu di ca ni dung file cn c vo Length.

3. Ch ng dn ca file th hin nhng gi tr mun c tSDRAM ra bng cch nhn Load SDRAM Content to a Filev

xc nh ng dn cho file . Sau ta c thxem ni dung va

c ra tSDRAM trn file ny.

3.3.3 Truy xut bnhFlash (Flash memory)Control Panel cho php ta truy xut (ghi/c) d liu ca Flash

memory trn Kit DE2. Ta c thsdng Control Panel thc hin cc thao tc

sau:

Xa ton bbnhFlash

Ghi mt byte ln bnhFlash

c mt byte tbnhFlash

Ghi mt file binary ln bnhFlash

c ni dung ca bnhFlash ra mt file.

Ch : Di y l nhng c tnh ca bnhFlash

Dung lng bnhFlash l 4Mx8bits

Ta phi xa ton bbnhFlash trc khi ghi dliu ln n. (Sln

xa bgii hn bi nh sn xut, do ngi sdng phi nhn thc

c sln c thxa bnhFlash m khng khin n bhng).Thi gian xa ton bbnhFlash l khong 20s. Do khng

c ng (ngt ngun) Kit DE2 trong sut qu trnh xa b nh

Flash.

truy xut bnhFlash thng qua Control Panel, ta chn tab FLASH trn

ca sControl Panel, mt ca snhhnh di sxut hin


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ghi mt file d liu (Sequential Write) vo trong bnhFlash, ta cn

thc hin nhng bc sau:

1. Nhp a ch ca nhbt u lu trni dung ca mt filevo Address.

2. Nhp chiu di ca ni dung file cn ghi vo hp Length. Nu tamun ghi ton bfile vo trong bnhFlash ta chvic chn

cho File Lengthm khng cn nhp chiu di ca ni dung file

cn ghi vo Length.

3. Chng dn ca file data cn ghi bng cch nhn Write a Fileto Flashv xc nh ng dn cho file .

c mt chui nhng k tlin tip hay ni dung ca mt file tbnh

Flash (Sequential Read), ta thc hin nhng thao tc sau:

1. Nhp a chca nhbt u ca chui nhm ta mun c ravo Address.

2. Nhp chiu di ca ni dung file cn c (s byte) vo hpLength. Nu ta mun c ton bni dung trong bnhFlash ta

chi vic chn cho Entire Flashm khng cn nhp chiu di

ca ni dung file cn c vo Length.

3. Chng dn ca file thhin nhng gi trmun c tbnhFlash ra bng cch nhn Load Flash Content to a Filev xc

nh ng dn cho file . Sau ta c thxem ni dung va c

ra tbnhFlash trn file ny.


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3.3.4 TOOLS Multi-Port SRAM/SDRAM/Flash ControllerChn Tab TOOLS trn ca s Control Panel s cho php ta chn User

Ports. Chng ta smt v dcthbng vic thc thi mt Flash Music Player. Ta

ti mt file nhc vo trong Flash memory. User Port 1 ca trnh iu khin Flash

memory c dng truyn file nhc n trnh iu khin Audio DAC v xut ra

output.

thc hin v dtrn ta thc thi theo cc bc sau:

1. Xa bnhFlash . Sau ghi file nhc (music.wav) ln bnhFlash (Trnh by trong phn 3.3.3 )

2. Trn Control Panel, chn Tab TOOLS, mt ca snhhnh disxut hin.

Hnh 3.9 Giao din Control Panel iu khin Multi-Ports

3. Chn cng Asynchronous 1 cho Flash Multiplexer v nhn ntConfigurekch hot cng trn. Ta cn nhn nt Configure

cho php kt ni t Flash Memory n Asynchronous Port 1 ca

trnh iu khin Flash.


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4. Tt SW1 ( vtr DOWN) v bt SW0 ( vtr UP).5. Cm headphone vo audio output, ta c thnghe nhc c pht ra

tkhi mch Audio DAC.

Ch rng, Asynchronous Port 1 c kt ni n Audio DAC nh hnh

trn. Khi ta chn Asynchronous Port 1 v nhn nt Configure, trnh iu khin

Audio DAC sgiao tip trc tip vi bnhFlash. Trong v dtrn, khi module

Verilog AUDIO_DAC c nhim vc ni dung ca bnhFlash v truyn n

n Chip Audio bn ngoi FPGA.

3.3.5 VGA Display ControlControl Panel cung cp mt cng ckt hp vi IP cho php ta hin thhnh

nh thng qua cng ng ra VGA. Di y l nhng bc dng minh ha cch

thc hin thmt bc nh ln mn hnh VGA.

Chn tab VGA trn ca sControl Panel, mt ca snhhnh di sxut

hin.

Hnh 3.10 Giao din Control Panel iu khin VGA

1. nh duvo hai Default Image v Cursor Enable


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2. Kt ni mn hnh VGA n kit DE2. Ta snhn thy mt mn hnhmc nh (do ta chn Default Image) nhhnh mc nh

nhhnh trn. Trn mn hnh bao gm mt con tr(do ta chn

Cursor Enable) m vtr ca n c iu khin bi thanh

cun X/Y trn Control Panel.

Hnh nh xut hin mn hnh trn c lu trtrong mt vng nhM4K

trn Cyclon II FPGA. N sc ti n vng nhM4K di nh dng MIF/Hex

(Intel) trong sut qu trnh ta thit lp cu hnh mc nh cho n.

Tip theo ta strnh by cch hin thmt hnh nh bt k ta mong mun ln

mn hnh VGA.

1. Ta c thly mt hnh nh c nh dng pitutre.dat (minh hacho phn trnh by ny ta s ly hnh nh c sn trong thmc

DE2_demonstrations/picture/picture.dat trn a CD DE2 System.

2. Ti file picture.dat vo trong SRAM ( trnh by phn c/GhiSRAM)

3. Chn tab TOOLS trn Control Panel, trn tab TOOLS ta chnAsynchronous 1 cho mc SRAM multiplexer nhhnh di.


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Hnh 3.15 Gi trngng ca nh

Ta c thiu chnh mu sc cho hnh nh bng cch thay i nhng thng

strong nhng trng BW Thresholdv Band of RGBtrn ca sImvConv.


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Chng 4. Hng dn thit kv thc hnh mn hc Hthngstrn Kit DE2

4.1 Hng dn thc hnh4.1.1 To mt project trn Quartus II

Bc 1. Start Programs Altera Quartus II 7.2 QuartusII 7.2 (32 -Bit)

Hnh 4.1 Mn hnh chnh ca Quartus

Bc 2. Nhn tab File trn mn hnh chnh


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Hnh 4.2 Tab File

Bc 3. Mmt project mi : FileNew Project Wizard

Hnh 4.3 To project

Bc 4. Nhn Next


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Hnh 4.4 Chng dn v tn project

Bc 5. Nhp ng dn thmc ca project (c thto trc hoc nucha to sc tng to).

Bc 6. Nhp tn ca project.Bc 7. Nhp top-level ca thit kcho project (nn cho ging tn ca

project).

Bc 8. Nhn NextBc 9. Nu ng dn thmc ca project cha c to trc :

Hnh 4.5 ng dn cha tn ti

Bc 10. Nhn Yes


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Hnh 4.6 Add cc file sdng trong project

Bc 11. Nhn Next

Hnh 4.7 Chn thit bFPGA

Bc 12. Chn Family : Cyclone II


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Bc 13. Chn Available devices : EP2C35F672C6 (H ca ChipFPGA Cyclone II trn Kit DE2).

Bc 14. Nhn Next

Hnh 4.8 Thit lp EDA tool

Bc 15. Nhn Next


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Hnh 4.9 Hon thnh vic to project

Bc 16.

Nhn Finishchvmn hnh chnh.

Hnh 4.10 Mn hnh chnh sau khi to project hon thnh


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4.1.2 Thit kmt mch in n gin ( cng XOR ) dng Schematic trn Quartus II:

Hnh 4.11 Thit kmt mch sn gin

4.1.2.1 Mtrnh thit ksdng schematicBc 1. MFileNew

Hnh 4.12 Chn cng cthit k

Bc 2. Chn Block Diagram/Schematic File


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Hnh 4.13 Ca sthit kmch s

Bc 3. Save as file : FileSave as

Hnh 4.14 Lu thit k

4.1.2.2 Thit kmch hthng sBc 1. Chn v nhp cng LogicGraphic Editor cung cp mt sthvin cha nhng linh kin in t, cho

php ngi sdng chn v nhp vo schemtic. Nhp p ln khong trng bn


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trong ca sGraphic Editor hoc nhp ln biu tng trong thanh cng c.

Mt ca snhhnh di xut hin

Hnh 4.15 Chn linh kin

Tca sny, ta c thtm v chn nhng linh kin hay cng logic m ta

mun nhp vo ca sGraphic Editor bng cch sau khi chn linh kin th ta

nhp nt OK. Th dta mun nhp mt cng AND 2 ng vo, ta stm v chnand2 tLibrary, sau nhn OK, ta sc mt biu tng cng AND2 xut hin

trn ca sGraphic Editor. Sdng chut di chuyn linh kin n vtr mong

mun bng cch nhn chut ln linh kin v ko ri nhp chut t n xung v

tr mi. Nu mun nhp mt cng AND2 ln thhai, ta c thlm nhcch trn

hoc c thcopy tbiu tng c sn trn ca sbng cch nhp phi chut,

ko r chut to ra mt biu tng thhai. Ta cng c thxoay biu tng ca

linh kin bng vic sdng biu tng trn thanh cng c.

Bc 2. Gn ng vo v ng ra cho linh kin:Sau khi nhp linh kin vo trong ca sGraphic Editor, ta phi gn ng

vo v ng ra cho linh kin trong mch in. Qui trnh cng tng tnhtm v

nhp linh kin, nhng biu tng ng vo hay ng ra sc tm thy trong th


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vin primitives/pin. Trong hnh di, ta snhn thy biu tng ca ng vo v

ng ra c gn vo chn ca linh kin.

Hnh 4.16 Cc linh kin c chn

Sau khi gn ng vo v ng ra cho linh kin, ta phi t tn cho chng.

t tn, ta nhp p vo tpin_name ca ng vo hay ng ra. Mt hp thoi nh

hnh sau sxut hin

Hnh 4.17 t tn pin cho thit k

Nhp tn cho chn linh kin vo Pin name(s), ri nhn OK.


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4.1.2.3 Trnh bin dchVi dliu vo l file nh dng .bdf (light.bdf), nhiu cng ctrong

phn mm Quartus II c dng phn tch, tng hp mch c thit k

phn trn, ri sau sto ra mt file thc thi dng np ln FPGA. Nhng cng

cc sdng trong qu trnh ny c gi l trnh bin dch. thc thi qu

trnh bin dch, ta thc hin cc bc sau:

Bc 1. Chn: ProcessingStart Compilationhoc nhn chn biutng trn thanh cng c. Sau khi qu trnh bin dch c hon tt,

mt bng bo co c to ra nhhnh di

Hnh 4.19 Ca strnh bin dch report

Bc 2. xem li qu trnh bin dch, ta chn : Processing Compilation Reporthoc nhn chn biu tng trn thanh cng

c.


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4.1.2.4 Message windowPhn mm Quartus II shin th thng tin trong sut qu trnh bin

dch trn ca sMessagewidow. Nu smch in c thit ktrong phn

Graphic Editor hon ton ng, th mt thng bo The compilation was

successful c hin th. Trong trng hp qu trnh bin dch xut hin li th c

ngha c li xy ra trong qu trnh thit ktrn Graphic Editor. Mi thng bo

tng ng vi mt li c tm thy sxut hin trn ca sMessage. Nhp p

vo thng bo li ta sbit r hn vli xy ra trn mch in. Tng t,

trnh bin dch cng thng bo mt scnh bo Warning. Ngoi ra ta cng c

th tm hiu thm thng tin v li cng nh cnh bo bng cch nhn chn vo

thng bo ri nhn phm F1 trn bn phm.

4.1.3 Gn pinV ta cha thc hin gn pin trn FPGA cho linh kin trong mch in

thit k trn nn khi thc hin bin dch th trnh bin dch Quartus II gn

chn ca linh kin vi pin ca FPGA mt cch ngu nhin. Tuy nhin, gistrong

thit k cng XOR n gin trn, sau khi thit k c bin dch v np ln

FPGA, ta mun hai ng vo x1, x2 c iu khin bi hai switch SW0 v SW1

cn kt qung ra f sc thhin trn led LEDG0 (SW0, SW1, LEDG0 c

ghi trn Kit). Mt khc ta bit switch SW0 c kt ni cnh vi pin N25 ca

FPGA, tng tvy switch SW1 c kt ni cnh vi pin N25 ca FPGA v

led LEDG0 c kt ni cnh vi pin AE22 ca FPGA. thc hin c iu

ta phi gn chn linh kin trn mch (x1, x2, f) vi pin tng ng trn FPGA

(N25, N26, AE22). gn pin ta thc hin cc bc sau

Bc 1. Chn Assignments > Pins, mt ca snhhnh di sxuthin


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Hnh 4.20 Ca smapped pin gia thit kv FPGA

Bc 2. Trong mc Category chn Pin. Nhp p ln mc trong ct To. Mt ca snhhnh di xut hin

Hnh 4.21 Ca sgn pin

Bc 3. Nhn chn x1 gn pin trc, tip n nhp p ln mc ngaybn phi ca x1 trong ct Location, mt ca snhhnh di sxut

hin


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Hnh 4.22 Ca slit k danh sch pin ca FPGA

Bc 4. Ta nhp chn PIN_N25.Bc 5. Tng t, ta gn pin cho chn ng vo x2 ti pin PIN_N26, v

chn ng ra f ti pin PIN_AE22. Sau khi gn pin hon tt, ta sc nh

hnh di

Hnh 4.23 Ca ssau gn pin

Bc 6. Lu li kt qugn pin: FileSaveBc 7. Ta phi bin dch li thit ktrn vi kt qugn pin ny v

nhta ni trn, v qu trnh bin dch trn, trnh bin dch Quartus


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II chgn pin mt cch ngu nhin nn skhng ng vi yu cu thit

kca ta, do ta phi gn li pin cho ng vi yu cu ri phi chy li

qu trnh bin dch. Lc ny trnh bin dch Quartus II ssdng nhng

pin m ta gn cho chn ca mch in trong thit kphn tch, tng

hp v to ra mt file thc thi vic np xung cho FPGA.

Ngoi ra ta cng c mt cch khc gn pins cho design, c bit l rt

hu ch trong thit km c nhiu chn, ta khng thngi gn pin cho tng chn

c v stn nhiu thi gian, Quartus II cung cp mt phng php gip ta gn

nhiu pin vo hoc gnhiu pin ra cng mt lc bng mt file c nh dng c

bit dng cho mc ch ny l nh dng .CSV. Format ca file ny nhsau

Nu ta dng file text to file ny, th n gin ta chcn nhp theo

mu sau

To, Location

x1, PIN_N25x2, PIN_N26

f, PIN_AE22

Nu ta dng Microsoft Excel, th ta sc format nhsau:

Hnh 4.24 Dng Microsoft Excel to file gn pin


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Sau khi to file c format nhtrn, ta sthc hin vic gn pin nhsau

Bc 1. Chn Assignments -> Import Assignments, mt hp thoinhhnh di xut hin

Hnh 4.25 Import file gn pin

Bc 2. Click button , chng dn ca file ta va to trn. Rinhn OK.

thun tin cho ngi s dng Altera cung cp mt file CSV c tn

DE2_pin_assignments, file ny lit k tt ccc pin ca FPGA, c format nhsau:


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Hnh 4.26 File gn pin to sn bi Altera

Nu ta mun sdng file c sn ny vo vic gn pin cho thit kca ta th

mt yu cu bt buc khi ta t tn cho chn linh kin phi trng vi tn trong ct

Toca file ny. Th d, nu ta mun hai chn ng vo ca cng XOR c iu

khin bi hai Switch 0 v Switch 1 trn Kit DE2 th ta phi t tn cho hai chn

ny ln lt l SW[0], SW[1] nhtrong ct Toca file ny. Do ta phi tham

kho file ny trc khi t tn cho chn linh kin khi gn pin ta srt thun tin

l khng phi to file.csv na m chcn Import file c sn ny vo thi.

Sau khi gn pin xong, ta bin dch li.

Re- compiling design : ProcessingStart CompilationReview Compilation report : ProcessingCompilation Report

4.1.4 M phng mch thit k:Bc 1. To input waveform : File New Other Files Vector

Waveform File


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Hnh 4.29 Nhp tn signal ca thit k

Bc 7. Chn Node Finder

Hnh 4.30 Dng chc nng Node Finder

Bc 8. Chn Filter : Pins : allBc 9. Nhn button ListBc 10. Chn signal bn Nodes found; nhn >> chuyn sang bn

Selected Nodes

Bc 11. Nhn OK


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Hnh 4.31 To input waveform

Bc 12. Chn mt input signal bng cch nhp chut vo signal .Bc 13. Chn biu tng mi tn con trBc 14. Di chuyn con trsang mn hnh waveform .Bc 15. Nhn v gichut v ko r (left) trong mt khong thi gian

(gista mun trong khong thi gian t40ns -> 60 ns , SW0 signal c

gi tr1, th ta nhn , giv r chut trong khong thi gian t40ns ->

60ns.

Hnh 4.32 To mc logic "1"

Bc 16. Nhn button 1pha bn tri mn hnh


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Bc 24. To simulation netlist : Processing Generate FunctionalSimulation Netlist

Bc 25. Chy m phng : ProcessingStart Simulation.Bc 26. Quan st waveform ca Output v debug nu c li.

Hnh 4.35 Waveform sau khi chy m phng

4.1.5 Programming mch thit kln FPGA :

Bc 1.

Kt ni Kit DE2 vi my tnh qua cng USB-Blaster (phi cit driver trc ).

Bc 2. Bt ngun Kit DE2.C 2 mode cho vic programming : JTAG v Active Serial modes

JTAG mode

Bc 3. Trn Kit DE2 , chuyn Switch RUN/PROGvvtr RUNBc 4. Trn mn hnh chnh Quantus II, chn ToolsProgrammer


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Hnh 4.36 Np thikln FPGA

Bc 5. Nhn Hardware Setup , chn USB-Blaster[USB-0] (Ch :phi ci t driver cho USB-Blater trc).

Hnh 4.37 Thit lp cng giao tip gia kit DE2 v Computer

Bc 6. Nhn CloseBc 7. Chn Mode JTAGBc 8. Nhn Add File , chng dn n File .sof (c to ra khi

chy Compilation).

Bc 9. Check box Program/Configure


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Hnh 4.38 Chn cu hnh np thit k

Bc 10. Nhn Start.Bc 11. Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

Active Serial Mode :

Bc 12. Chn Assignments Devide

Hnh 4.39 Thit kchnp ln FPGA bng AS mode

Bc 13. Chn Family : Cyclone IIBc 14. Chn Available devices : EP2C35F672C6Bc 15. Nhn Device & Pin Option


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Bc 16. Chn Tab Configuration

Hnh 4.40 Chn loi ROM tng ng

Bc 17. Chn Configuration device : EPCS64 (hEPPROM trn KitDE2 , dng lu chng trnh np cho FPGA mi khi power on).

Bc 18. Tng tJTAG nhng bc ktip :Bc 19. Trn Kit DE2 , chuyn Switch RUN/PROGvvtr RUNBc 20. Trn mn hnh chnh Quantus II, chn Tools ProgrammerBc 21. Chn Hardware Setup : USB-Blaster[USB-0]Bc 22. Chn Mode : Active Serial ProgrammingBc 23. Nhn Add File, chng dn n File .pof(File c to ra

trong qu trnh chy Compilation).


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Hnh 4.41 Chn file thit k.pof

Bc 24. Check box Program/Configure.Bc 25. Nhn Startprogramming chng trnh cho EPPROM.Bc 26. Nhn Phm Restarttrn Kit DE2,Bc 27. Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.

4.2 Ni dung thc hnh mn Hthng s4.2.1 Bi thc hnh s1 Switchs, Lights, Multiplexers

Mc ch ca Lab 1: Hc cch kt ni n gin nhng ng vo v ng ra

ca linh lin n FPGA v thit kmt smch in n gin sdng nhng linh

kin trn Kit DE2 nhl ng vo v ng ra ca mch thit k. Trong Lab ny, ta s

s dng Switch SW17-SW0 trn Kit DE2 nh l ng vo ca mch v s dng

LED v LED by on nh l ng ra ca mch. lm tt Lab1, sinh vin cn

phi nm trc nh vcch thit k, bin dch v m phng mt mch in n

gin trn Quartus II.

4.2.1.1 Phn 1Tng bc thc hin:

Bc 1. To mt project Quartus mi, t tn: user_dir/lab1/lab1_par1Bc 2. Thit kmt mch nhsau:


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2. Cho mch sau:

Hnh 4.44 Mch gm 8 MUX 2-1

Bc 2. Nu hot ng ca mch trnBc 3. To mt project Quartus mi, t tn:

user_dir/lab1/lab1_part2

Bc 4. Thit kmt mch nhsau:


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Hnh 4.45 Mch 8 MUX 2-1 vi SW v LED

Bc 5. Bin dch phn tch, tng hp v to ra file .sof.Bc 6. To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.

Bc 7. Np file thc thi ln FPGA. Kim tra hot ng ca mch.Ch : Sinh vin cn chun btrc nh nhng cng vic sau ( Khng c

bi chun bkhng c vo lp lm th nghimTnh vng bui )

c v thc hin cc bc t1 n 6 nh.

4.2.1.3 Phn 3Cho mch sau:


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Hnh 4.46 Mch chn knhBc 1. Nu hot ng ca mch trn v vit bng stht cho mch.Bc 2. To mt project Quartus mi, t tn:

user_dir/lab1/lab1_part3

Bc 3. Thit kmt mch nhsau:

Hnh 4.47 Mch chn knh 3 input

Bc 4. Bin dch phn tch, tng hp v to ra file .sof.Bc 5. To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.


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4.2.1.4 Phn 4Cho mch sau:

Hnh 4.48 Mch gii m HEXDi y l bng stht ca mch gii m cho Led 7 on trn dng hin

thmt trong 4 k tH, E, L, O.

Hnh 4.49 Bng gii m


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Bc 1. Sinh vin hon thnh bng stht trn. ( Ch : Cc on LEDtch cc mc thp).

Bc 2. Da vo bng s tht, thit kmch gii m cho LED 7 ontrn.

Bc 3. To mt project Quartus mi, t tn:user_dir/lab1/lab1_part4

Bc 4. Thit kmch nhhnh trn.Bc 5. Bin dch phn tch, tng hp v to ra file .sofBc 6. To file Vector Waveform (.vwf) v chy m phng kim tra

hot ng ca mch.




4.2.1.5 Phn 5Cho dliu mch in nhsau:

Hnh 4.50 Mch chn knh v hin th


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Da vo nhng dkin cho hnh trn v kin thc nm c

tPart1 n Part4, hy thit kmch in hot ng theo bng stht

sau ( Ch : c th thit kbng nhiu cch, c thsdng ht cc

SW hoc sdng mt sSW ty vo cch thit k)

Hnh 4.51 Mode hin th

4.2.2 Bi thc hnh s2 Sv cch hin thMc ch lab 2: Thit kmch chuyn t s nhphn sang thp phn v

mch cng sBCDHng dn cch ng gi v ti sdng 1 mch thit k

Bc 1. To 1 file .bdf, vmch cn sdng li trn .Bc 2. Chn File Create / Update Create symbol file for

current file, to ra file .bsf


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Hnh 4.53 Mch gii m hin thHEXA

Tng bc thc hin:Bc 1. To project Quartus mi, t tn user_dir/lab2/part1Bc 2. Thit kmch nhHnh 4.53Bc 3. Gn pin cho mch hnh trnBc 4. Bin dch phn tch, tng hp v to ra file .sof.


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Bc 5. To file Vector Waveform (.vwf) v chy m phng kim trahot ng ca mch.

Bc 6. Np file thc thi .sof ln FPGA. Kim tra hot ng ca mch.Ch : Sinh vin chun btrc nhng cng vic sau (Khng c bi chun

bkhng c vo lp lm th nghimtnh vng bui )

c v thc hin cc bc t1 n 5 nh

4.2.2.2 Phn 2

Phn I chuyn tsnhphn 4 bit sang sthp phn dng 1 n led 7on. Yu cu ca Phn II l sdng 2 led 7 on c thbiu din thm cc s

thp phn t10 n 15.

Mt phn thit kca mch ny c gi nhhnh Hnh 4.54

Hnh 4.54 Mch hin tht0 n 15


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Bc 1. Nu hot ng ca mch trn v vit bng stht cho mch2. Cho mch sau

Hnh 4.56 Mch cng FA 4 bit

Trong hnh Hnh 4.56, FA l 1 khi thhin cho mch hnh Hnh 4.55.

Bc 2. Nu ngha hot ng ca mch ny.Bc 3. To project Quartus mi, t tn user_dir/lab2/part3Bc 4. Thit kmch nhhnh Hnh 4.55, sau sdng mch ny

thit kmch nhHnh 4.56

Bc 5. Gn pin Input a3a2a1a0 c gn ti SW[3:0], input b3b2b1b0 c gn

135995051-Giao-Trinh-Thá»±c-Hanh-DE2

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