12284 Digital Mwtastability

7/31/2019 12284 Digital Mwtastability

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Metastability

When asynchronous events enter synchronous system they can cause to go intometastable states.

Every real life bistable (such as a D-latch) has a metastable state

Whenever there are setup and hold time violations in any flip-flop, it enters a state where

its output is unpredictable: this state is known as metastable state(quasi stable state).

Metastability Can occur if the setup (tSU

), hold time (tH), or clock pulse width (t

PW) of a flip-

flop is not met.

A problem for asynchronous systems or events.

Three possible symptoms:

Increased CLK Q delay.

Output a non-logic level

Output switching and then returning to its original state.

Theoretically the amount of time a device stays in the metastable state may be infinite.

At the end of metastable state, the flip-flop settles down to either '1' or '0'.


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Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 4

Inconsistent Perception

D

CLK

D

CLK

X

0

1

Metastab.

The metastable state may be regarded as 1 by one FFand as 0 by another

CMOS 3V

0.8V

2.0V

0.0V

0.4V

2.4V

3.3V

D

CLK

X

threshold A

A

Btreshold B

A


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Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 5

Resolution Time

clk

asyn

syntclk2out

tcomb tSUtres

SUcombclkresttTt

D

CLK

D

CLK

asyn

clk

syncomb.logic

normal operation:tclk2out < tr

upset:tclk2out

> tr


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mean time between failures (MTBF)

Suppose an asynchronous input changes with a frequency of fD and the clock

frequency of the system is fc We sample the output value of the flip-flop to which

the asynchronous input is connected after a period t.

The sampled value will be incorrect due to metastability in the flip-flop and that

will cause some form of failure called mean time between failures (MTBF):

MTBF is a figure of merit related to metastability(IT IS A MEASURE OF REALIBILITY)

FD: Data Frequency

FC: Clock Frequency

TP: Flip Flop Propagation Delay

tr: Resolve Time/settling time


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2/19/03 ECE 426 - Lecture 7 7

Resolution Time Example

Suppose that

fclk = 100MHz (tclk = 10ns)

a = 1MHz

tprop = 6.7ns

tsu = 1ns

Calculate tr:

tr = tclk - tsu - tprop

tr = 10ns - 6.7ns -1ns

= 2.3ns

Comb.

Logic

D Q D Q

clk

tprop=6.7ns

tsu=1ns


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MTBF gives us information on how often a particular element will fail or it gives the average

time interval between two successive failures


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Example

Type of flip-flop SN74ALS74

Mean frequency of asynchronous interrupt signal fin = 10kHzSystem clock frequency fclk = 25MHz

Setup time of following circuit tsu = 15 ns,RC= =1.0

At the output of the synchronization stage, the settling time (tx) is

calculated as follows:


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A 74LS74 FF (T0 = 0.4, = 1.5) at a clock rate of 10 MHz and in input av. rate of

change = 100 KHz tr = 80 ns (100 ns clock period - 20 ns tsu)

MTBF = 3.6 1011 sec.

If we just change the clock to 16 MHz, things get really strange

tr = 42.5 ns (62.5 ns clock period - 20 ns tsu)

MTBF = 3.1 sec.

if we change to a 74ALS74 FF (tr = 52.5 ns)

(62.5 ns clock period - 10 ns tsu)

MTBF = 4.54 1015 sec.


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Synchronizers

Adding a second Flip Flop to the design will reduce the chance of the output going

Metastable.

The output from the first flip flop may go valid before the second flip flop is clocked.

It connect asynchronous input to the rest of system

Whenever there is signal transfer between two systems operating at different

frequencies or same frequency with different phases, synchronizer block is used as an

interface so that signal from transmitter block is reliably interpreted by the receiver.

This block ensures that there is no metastability for a target MTBF.

There are two inputs the clock C and the

asynchronous signal D and one output the

synchronised signal D.

The two input signals interact asynchronously

modelled roughly by operating frequencies f1 and

f2


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A simple synchronizer comprises two flip-flops in series without any

combinational circuitry between them. This design ensures that the first

flip-flop exits its metastable state and its output settles before the second

flip-flop samples it

The synchroniser is expected to provide a defined logic level (0 or l) within

a bounded decision time after D otherwise a synchronisation failure has

occured.
http://photos1.blogger.com/blogger/6758/632/1600/clip_image002.gif


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2/19/03 ECE 426 - Lecture 7 13

MTBF Calculation Example

Typical values for a 0.25m ASIC library

flip-flop

= 0.31ns

To= 9.6as a = 10-18

tr = 2.3ns

MTBF = 20.1 days - unacceptable!

MTBF(tr)e(t r / )

To fclk a


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Two-Stage Synchronization

The second flip-flop receives the output signal of the first stage after one clock

period and can go into a metastable state only if its input conditions are also

violated.

the output of the first flip-flop is still metastable during its setup and hold time. So

the critical input frequency fin(2) of the second stage is calculated from the

reciprocal of the mean time between two failures of the first stage:


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one SN74ALS74 flip-flop, the MTBF was 54 minutes. Again, assuming that the

second flip-flop is sampled after 25 ns


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Mean Time Between Failure (MTBF) of a particular flip-flop in the context of a given clock

rate and input transition rate is 33.33 seconds then the MTBF of two such flip-flops used tosynchronize the input would be (33.33* 33.33) = 18.514 Minutes


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Double Synchronizer for Single-Bit

Data Transfer

2-bit shift register structure clocked by the receiving clock.

The second stage of the shift register reduces the probability of metastability on the data

output from the first register propagating through to the output of the second register.

More than two stages of the synchronizer circuit can be used at the expense of increased

latency.

The benefit of more stages is that the mean time between failures (MTBF) is increased with

each additional stage.


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SRAM - DRAM

SRAM(Static RAM)- stored data persists indefinitelyso long as power is

applied to the memory component.

DRAM (dynamic RAM) which we will describe laterand which loses stored data if it is not periodicallyrewritten.

Static RAM is volatile, it requires powerto maintainthe stored data and loses data if power isremoved

asynchronous SRAM because it does not rely on aclock for its timing


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Asynchronous SRAM

Asynchronous SRAM internally uses 1-bit storage cells that are similar to the D-latch circuit

Address is decoded to select a particular group of cells that comprise one location.

For a write operation the selected latch cells are enabled and the input data is

stored.

For a read operation the address activates a multiplexer that routes the outputs of

the selected latch cells to the data outputs of the memory component.

chip-enable input (CE) is used to enable or disable the memory chip.

This input from a select control signal (address decoder)

write-enable input (WE) controls whether the memory if enabled

performs a write or read operation.The output-enable input (OE) controls the tristate data drivers during a

read operation.

When (OE) is low during a read the drivers are enabled and

can drive the read data onto the data pins.

When (OE) is high the drivers are in the high-impedance

state.


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Write

The control section selects the particular

memory chip by driving CE low activates

The write operation by driving WE low and

ensures that the chips tristate drivers are

disabled by driving OE high.

It also sets control signals to the datapath toprovide data on the data signals. The data is

stored transparently in the latch cells for the

addressed location.

The final data to be stored must be stable on

the data signals a setup time before the

rising edge of the WE signal or the CE

signal.

The data and the address must also remain

stable for a hold time after the WE or CE

signal goes high.


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Read

The control section selects the particular

memory chip by driving CE low activates

The write operation by driving WE high and

ensures that the chips tristate drivers are

disabled by driving OE low.

It also sets control signals to the datapath toprovide data on the data signals. The data is

stored transparently in the latch cells for the

addressed location.

The final data to be stored must be stable on

the data signals a setup time before the

rising edge of the WE signal or the CE

signal.

The data and the address must also remain

stable for a hold time after the WE or CE

signal goes high.


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charge-coupled device

A charge-coupled device (CCD) is a device for the movement of electrical charge within the

device to an area where the charge can be manipulated.

The charge-coupled device (CCD) is by far the most common mechanism for converting

optical images to electrical signals.

It uses a quantity of electrical charge to represent an analog quantity, such as light intensity

sampled at discrete times

CCD is a discrete-time device, i.e., a continuous, or analog, signal sampled at discrete times.

The fundamental element of every CCD is the metal oxide semiconductor (MOS) capacitor

The CCD is a major technology for digital imaging. In a CCD image sensor, pixels are

represented by p-doped MOS capacitors.

These capacitors are biased above the threshold for inversion when image acquisition begins

allowing to convert incoming photons into electron charges at the semiconductor-oxide

interface; the CCD is then used to read out these charges.

Invention of CCD Smith & Boyle 1969 George Smith and Willard Boyle were working in a

Bell Labs group interested in creating a new kind of semiconductor memory for computers.

Also great hope was then held for the video telephone service.


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Basics of operation

An image is projected through a lens onto the capacitor causing each capacitor toaccumulate an electric charge proportional to the light intensity at that location.

A one-dimensional array, used in line-scan cameras, captures a single slice of theimage, while a two-dimensional array, used in video and still cameras, captures atwo-dimensional picture corresponding to the scene projected onto the focalplane of the sensor.

Once the array has been exposed to the image a control circuit causes each capacitorto transfer its contents to its neighbor (operating as a shift register). The lastcapacitor in the array dumps its charge into a charge amplifier.

charge amplifier converts the charge into a voltage.

By repeating this process, the controlling circuit converts the entire contents of thearray in the semiconductor to a sequence of voltages.

In a digital device, these voltages are then sampled, digitized, and usually stored in

memory.in an analog device they are processed into a continuous analog signal (e.g. by

feeding the output of the charge amplifier into a low-pass filter) which is thenprocessed and fed out to other circuits for transmission, recording, or otherprocessing.


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Single CCD Cell

One cell of a CCD would just be a MOS capacitor if its function were to just pass along the

analog charges by bucket-brigade.

MOS capacitor is light sensitive as in aphotodiode (PD).

As an elementof a CCD the single cell would, in general, be capable of:

(1) receiving a quantity ofcharge from an upstream cell,

(2) holding the charge for a time withoutappreciable loss(3) passing the charge to the next cell downstream.

CCD would be a few MOS capacitors arranged in a single row


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Device Architectures

Full Frame Readout: full-frame would require a mechanical shutter to cut off the

light input in order to prevent smearing during the time the charges are passing

through the parallel vertical registers or vertical-CCD (V-CCD).

The pixel charges are transferred in parallel, to the horizontal-CCD (H-CCD) where

they are then transferred in serial to the output.


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Frame Transfer. The image is transferred from the image array to the opaque

frame storage array b

Inter-Line Transfer. Each pixel includes both aphotodiode and a separate opaque

charge storage cell. The image charge is first quickly shifted from the lightsensitive

PD to the opaque V-CCD. Inter-line transfer hides the image in one transfer

cycle, thus producing the minimum image smear and the fastest optical shuttering.

12284 Digital Mwtastability

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