103601-8484 IJBAS-IJENS

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International Journal of Basic & Applied Sciences IJBAS-IJENS Vol: 10 No: 01 24

Reusable IP core for Forward Error Correcting

Codes

Farhan Aadil, Shahzada Khayyam Nisar, Wajahat Abbas, Asim ShahzadDepartment of Software Engineering,

University of Engineering and Technology, Taxila, Pakistan[farhan.aadil | shahzada.khayyam | wajahat.abbas | asim.shahzad]@uettaxila.edu.pk

Abstract - Error Correction codes are a mean of

including redundancy in a stream of information bits to

allow the detection and correction of symbol errors

during transmission. Forward Error Correcting

codes are a new class of codes that can achieve

exceptional error performance and energy efficiency at

low signal-to-noise ratio. These codes achieve a near-

Shannon limit performance. Owing to the

computational complexity of these FEC codes they are

well suited for optimized implementation using customhardware in FPGA. As; this allows us more parallelism

and less latency.

INTRODUCTION

The availability of wireless technology has revolutionizedthe way communication is done in our world today.Cellular and Satellite technologies make it possible for

people to be connected to the rest of the world fromanywhere. With this increase availability comes increaseddependency on the under line systems to transmitinformation both quickly and accurately. Because thecommunication channels in wireless systems can be muchmore hostile than in “wired” systems, voice and data mustuse forward error correction coding to reduce the

possibility of channel affects corrupting the information being transmitted [1]. Our research is based on the field of digital Communications. We used FPGA boardXCS3S1000 to achieve the following

• 2 Bit Error detection

• 2 Bit Error Correction

• In Case of Convolution codes supportsconstraint length K of 3 and inMATLAB supports K=3 to 7

• In case of Block codes n=7 and k=3

FORWARD ERROR CORRECTION

FEC codes or channel codes have become an inevitable inwireless based digital communication systems. That is, by

allowing a system to operate at a lower signal to noise ratiothan would otherwise be the case, a desired quality of service over a link can be achieved within a transmit power or antenna gain constraints of the system [1] [3]. This

property of error correcting codes is often referred to as‘Power Efficiency’.

Figure 1 shows an error correcting code within a digitalcommunication system. The channel encoder adds code bitsto the transmission bit stream, based on the data bits at itsinput. These extra bits are used by the channel decoder at

the receiver to correct errors introduced into thetransmission stream by a noisy or fading channel.

Figure 1: A Typical Digital Communication System

Forward error correction (FEC) is a system of error controlfor data transmission, whereby the sender adds redundantdata to its messages, also known as an error correction code[4]. This allows the receiver to detect and correct errors(within some bound) without the need to ask the sender for

additional data.

Figure 2: Forward Error Correction

Forward Error Correction is a critical component in manymodern digital communications applications, turningotherwise unusable communications links into real and

practical systems. From DVDs to cell phones, satellite TVto disk drives, error correction technology is amathematical marvel that effectively makes a silk pursefrom a sow’s ear [5].

HOW IT WORKS

FEC is accomplished by adding redundancy to thetransmitted information using a predetermined algorithm.

Noise

Sender Encoder Modulator

Channel

User Decoder Demodulator

Communication

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Each redundant bit is invariably a complex function of many original information bits. The original informationmay or may not appear in the encoded output; codes thatinclude the unmodified input in the output are systematic,while those that do not are nonsystematic. An extremelysimple example would be an analog to digital converter thatsamples three bits of signal strength data for every bit of

transmitted data. If the three samples are mostly all zero,the transmitted bit was probably a zero, and if threesamples are all one, the transmitted bit was probably a one.The simplest example of error correction is for the receiver to assume the correct output is given by the most frequentlyoccurring value in each group of three as shown in thetable.

Triplet Received Interpreted as

000 0

001 0

010 0

100 0

111 1

110 1

101 1

011 1

Table 1: Analog to digital converter that samples three

bits of signal to one bit

FEC could be said to work by "averaging noise"; since eachdata bit affects many transmitted symbols, the corruption of some symbols by noise usually allows the original user datato be extracted from the other, uncorrupted receivedsymbols that also depend on the same user data.

Most telecommunication systems used a fixed channel codedesigned to tolerate the expected worst-case bit error rate,and then fail to work at all if the bit error rate is ever worse.However, some systems adapt to the given channel error conditions: hybrid automatic repeat-request uses a fixedFEQ method as long as the FEQ can handle the error rate,then switches to ARQ when the error rate gets to high;adaptive modulation and coding uses a variety of FEQrates, adding more error-correction bits per packet whenthere are higher error rates in the channel, or taking themout when they are not needed.

CONVOLUTIONAL CODING

Convolution codes are a popular class of coders withmemory, i.e., the coding of an information block is afunction of the previous blocks [6]. A Convolutional codeis a type of error-correcting code in which

(a) Each m-bit information symbol (each m-bit string) to beencoded is transformed into an n-bit symbol, where m/n isthe code rate (n ≥ m) and

(b) The transformation is a function of the last k information symbols, where k is the constraint length of thecode.

Convolutional codes are often used to improve the performance of digital radio, mobile phones, satellite links,and Bluetooth implementation [7].

Convolution codes involve simple arithmetic operationsand therefore they are easily implemented. If a block codeis used for error detection, only simple integer division isneeded; however, decoding block codes or convolutioncodes for error correction is much more tedious [8].

For block codes, an iterative algorithm is often used tocorrect the errors. Error correction algorithms become quitecomplex for long codes with large error correctioncapability; especially, for non-binary codes.

For convolution codes, decoders are often based on theVeterbi algorithm which is known to be an optimalalgorithm. Its decoding complexity grows exponentially

with code memory length. Therefore it is effective for shortmemory length codes.

Veterbi Decoding AlgorithmThe Veterbi Algorithm (named after Andrew Veterbi) is adynamic algorithm that uses certain path metrics tocompute the 'most likely' path of a transmitted sequence.From this 'most likely' path, certain bit errors can becorrected to decipher the original bit sequence after it has

been sent down a communicative line.

An important feature of the Veterbi algorithm is that tiesare arbitrarily solved (can be picked randomly) and stillyield an original sequence [8]. What the Veterbi algorithmcan do is correctly replicate your input string at the output

even in the presence of one or more errors. Obviously,with more errors introduced the likelihood of a successfuldecryption does go down.

Convolution encoding and veterbi decoding are the most popular because of their powerful coding-gain performances. Convolutional encoder and veterbi decoder is extensively used in a wide variety of devices to reducetransmitted power, decrease the degrading effects of noisein the channel.

This veterbi decoder is used in devices ranging from themobile phones people use in the daily life to the morecomplex satellite receivers and deep space missions.

Veterbi decoder is mainly used in the wireless connectionswhere the additive wide Gaussian noise is pre dominanat.FEC suit FPGA because they have efficient parallelarchitecture, we can reconfigure them withoutnonrecurring-engineering costs, and their performance isalways improving [9].

Z

Nois

RY

X Convolutio

n

Viterbi

Decoder

Chann

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Communicati

ons Cha nnel

or Storage

Figure 3: Convolutional encoder with Veterbi decoder

VETERBI DECODER TECHNICAL

SPECIFICATIONS

• Constraint Length, K=7

• Code Rate k/n=1/2, Where k=input bit/s andn=no of output data bits

• Parameterizable Constraint Length From 3 to 7

• High Speed compact Veterbi Decoder

APPLICATIONS OF VETERBI

• Wireless LAN• Digital Cellular Phones

• Satellite Communications

• Digital Video Broad Casting

• Digital wireless Transmitters and receivers

REED SOLOMON CODES

Reed-Solomon codes are block codes. This means that afixed block of input data is processed into a fixed block of output data. In the case of the most commonly used R-Scode (255, 223) – 223 Reed-Solomon input symbols (eacheight bits long) are encoded into 255 output symbols [2].

• Most R-S ECC schemes are systematic. Thismeans that some portion of the output codewordcontains the input data in its original form.

• A Reed-Solomon symbol size of eight bits waschosen because the decoders for larger symbolsizes would be difficult to implement withcurrent technology. This design choice forces thelongest codeword length to be 255 symbols.

• The standard (255, 223) Reed-Solomon code iscapable of correcting up to 16 Reed-Solomonsymbol errors in each codeword. Since eachsymbol is actually eight bits, this means that thecode can correct up to 16 short bursts of error dueto the inner convolutional decoder.

The Reed-Solomon code, like the convolutional code, is atransparent code. This means that if the channel symbolshave been inverted somewhere along the line, the decoderswill still operate. The result will be the complement of theoriginal data. However, the Reed-Solomon code loses itstransparency if virtual zero fill is used. For this reason it ismandatory that the sense of the data (i.e., true or complemented) be resolved before Reed-Solomondecoding [8].

Reed-Solomon codes are block-based error correctingcodes with a wide range of applications in digitalcommunications and storage. Reed-Solomon codes areused to correct errors in many systems including:

• Storage devices (including tape, Compact Disk,DVD, barcodes, etc)

• Wireless or mobile communications (includingcellular telephones, microwave links, etc)

• Satellite communications

• Digital television / DVB

• High-speed modems such as ADSL, xDSL, etc.

In addition, the Reed-Solomon codewords can beinterleaved on a symbol basis before being convolutionallyencoded. Since this separates the symbols in a codeword, it

becomes less likely that a burst from the Viterbi decoder disturbs more than one Reed-Solomon symbol in any onecodeword [2] [8].

A typical system is shown here

Figure 4: Reed Solomon Encoder/Decoder

The Reed-Solomon encoder takes a block of digital dataand adds extra "redundant" bits. Errors occur duringtransmission or storage for a number of reasons (for example noise or interference, scratches on a CD, etc). TheReed-Solomon decoder processes each block and attemptsto correct errors and recover the original data. The number and type of errors that can be corrected depends on thecharacteristics of the Reed-Solomon code.

PROPERTIES OF REED-SOLOMON CODES The error-correcting ability of any Reed-Solomon code isdetermined by n − k, the measure of redundancy in the

block. If the locations of the errored symbols are not knownin advance, then a Reed–Solomon code can correct up to (n− k) / 2 erroneous symbols, i.e., it can correct half as manyerrors as there are redundant symbols added to the block.Sometimes error locations are known in advance (e.g.,“side information” in demodulator signal-to-noise ratios)these are called erasures [2]. A Reed–Solomon code (likeany linear code) is able to correct twice as many erasures aserrors, and any combination of errors and erasures can be

Data

Sink

Noise/ error

Data

SourcReed-

Solom on

Reed-

Solom on

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corrected as long as the inequality 2E + S < n − k issatisfied, where E is the number of errors and S is thenumber of erasures in the block.Reed Solomon codes are asubset of BCH codes and are linear block codes. A Reed-Solomon code is specified as RS (n, k ) with s-bit symbols.This means that the encoder takes k data symbols of s bitseach and adds parity symbols to make an n symbol

codeword. There are n-k parity symbols of s bits each. AReed-Solomon decoder can correct up to t symbols thatcontain errors in a codeword, where 2t = n-k .

The following diagram shows a typical Reed-Solomoncodeword (this is known as a Systematic code because thedata is left unchanged and the parity symbols areappended)

The properties of Reed-Solomon codes make them

especially well-suited to applications where errors occur in bursts [10] [11] [12]. This is because it does not matter tothe code how many bits in a symbol are in error—if multiple bits in a symbol are corrupted it only counts as asingle error. Conversely, if a data stream is notcharacterized by error bursts or drop-outs but by randomsingle bit errors, a Reed-Solomon code is usually a poor choice.

REED SOLOMON ENCODER / DECODER

TECHNICAL SPECIFICATIONS

• Symbol Length(m)=3 to 24

• No of input Symbols to encoder=k symbols

• No of encoded symbols of encoder=n symbols• Error detecting capability(d)=n-k

• Error correcting capability(t)=(n-k)/2

• Use for Burst Error correction

APPLICATIONS OF REED SOLOMON CODES

• The Digital Audio Disc

• Deep Space Telecommunication Systems

• Error Control for Systems with Feedback

• Spread-Spectrum Systems

• Computer Memory

SIMULATIONS AND RESULTS

Our research paper consists of two main phases. In the first phase we have implemented these FEC codes (convolutionEncoder with Veterbi decoder & Reed Solomonencoder/decoder) in MATLAB. And in other phase wehave implemented these codes on FPGA board by using thesoftware’s like XILINX & MODELSIM.

CONVOLUTIONAL ENCODER & VETERBI

DECODER USING MATLAB

Step 1

In the first step we have made a XLS file named “data”that provide the input bits 10110100 for the convolutionalencoder. The XLS file look like this

Figure 5: Data in MS Excel

Step 2

In the second step we call the transceiver function inMATLAB work space window this will open a new dialog

box that ask you to enter the name of file and the type of the file like this

Figure 6: Data in MATLAB

There are three steps involve in the transceiver function

1) Transceiver function calls the encoder function that getsthe input bits, upper polynomial and lower polynomial and

provides us the convolved data.

2) It introduce error in the data .If 8 bit data is provided itcreates 1 bit error and 2 bit error for higher no of bits.

3) In the end it perform the decoding by calling veterbidecoder function that removes the redundant bits detect andcorrect the error and provide us the actual no of bits that wehave transmitted.

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Here we have given the input data 10110100 as shownfrom the file named “data.xls”. Encoded data is1110100111101001 and the decoded data is same as theinput data.

Figure 7: Data in MATLAB (1)

REED SOLOMON ENCODER & DECODER USING

MATLAB

Step1

In the first step we have made a XLS file named“RS_Data” that provide the input bit symbols 010110111for the RS encoder. The XLS file look like this

Figure 8: Data in MS Excel

Step 2

In the second step we call the RS_Transceiver function inMATLAB work space window this will open a new dialog

box that ask you to enter the name of file and the type of the file like this

Figure 9: Data in MATLAB

There are three steps involve in the transceiver function

1) Transceiver function calls the encoder function that getsthe input bits symbol,2) It introduces error in the data. Reed Solomon can correctthe burst error therefore error is introduced in two symbols.3) In the end it perform the decoding by calling RS

decoder function that detect and correct the error in thesymbols and provide us the actual no of bits that we havetransmitted.

Figure 10: Data in MATLAB (1)

Here we have given the input data 010110111 as shownfrom the file named “RS_Data.xls”. Encoded data is100001011101010110111 and the decoded data is same asthe input data.

MODELSIM SIMULATION

CONVOLUTIONAL ENCODER

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VETERBI DECODER

Figure 11: Simulations

SOFTWARE ARCHITECTURE

CONVOLUTIONAL ENCODER & VETERBI DECODER

Figure 12: Software Architecture

VETERBI DECODER TECHNICALSPECIFICATIONS

• Constraint Length, K=7

• Code Rate k/n=1/2, Where k=input bit/s andn=no of output data bits

• Parameterizable Constraint Length From 3 to 7

• High Speed compact Veterbi Decode

REED SOLOMON ENCODER & DECODER

Figure 13: Reed Solomon Encoder & decoder

REED SOLOMON ENCODER / DECODER

TECHNICAL SPECIFICATIONS

• Symbol Length(m)=3 to 24

• No of input Symbols to encoder=k symbols

• No of encoded symbols of encoder=n symbols• Error detecting capability(d)=n-k

• Error correcting capability(t)=(n-k)/2

• Use for Burst Error correction

ACHIEVED RESULTS AND CONCLUSIONS

In our research we have implemented ConvolutionalEncoder and Veterbi decoder, Reed Solomon Encoder andDecoder in MATLAB as well as in Verilog and implementthem on FPGA, thus achieved the required results.

FUTURE RECOMMENDATIONS

We would like to recommend the following features to beincorporated in our developed software

• Constraint length k can be increased

• Error Detection capability can be increased

• Error Correction capability can be increased

• Interfacing can be implemented

REFERENCES

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[1] X. Yu, J. Modestino, and I. Bajic, “Performanceanalysis of the efficacy of packet-level FEC in improvingvideo transport over networks,” in Proc. IEEE Int. Conf.Image Process. (ICIP ’05), pp. II-177–II-180.[2] Reed Solomon Forward Error Correction Codes,

http://en.wikipedia.org/wiki/Reed-Solomon_error_correction

[3]Dan Jurca et al, “Forward Error Correction for MultipathMedia Streaming” IEEE Transactions on circuits andsystems for video technology, vol. 19, no. 9, pp 1315-1326,September 2009[4] Why Digital Fountain's Raptor Code Is Better ThanReed Solomon Erasure Codes For Streaming Applications,2005 Digital Fountain, Inc.[5] Recent Advances in Error/Erasure Correcting andCoding, Vijay Subramanian, Networks Lab - RPI,http://networks.ecse.rpi.edu/pubs/ecc.ppt[6] 3GPP TSG-SA4#31 Tdoc S4-040348 May 17-21, 2004,Montreal, Canada, Simulation Guidelines for theEvaluation of FEC Methods for MBMS Download andStreaming Services.[7] Frenger, P., P. Orten, and T. Ottosson, "Convolution

Codes with Optimum Distance Spectrum," IEEECommunications Letters, vol. 3,pp. 317-319, November 1999.[8] Ufuk DEMIR and Ozlem AKTA$ “Raptor versus ReedSolomon Forward Error Correction Codes” Proceedings of the Seventh IEEE International Symposium on Computer

Networks (ISCN'06) pp 264-269, 2006[9]B. Fong et al. “Forward Error Correction with Reed-Solomon Codes for Wearable Computers” IEEETransactions on Consumer Electronics, Vol. 49, No. 4, pp917-921, NOVEMBER 2003

[10] L. Yin, J. Lu, K. Ben Letaief and Y. Wu, "Burst-error correcting algorithm for Reed-Solomon codes", ElectronicsLetters, Vol. 37 No. 11, May 25, 2001, pp. 695- 697

[11] Ted H. Szymanski, “Optical Link Optimization UsingEmbedded Forward Error Correcting Codes” IEEE Journalof selected topics in quantum electronics, vol. 9, no. 2, pp647-656, March/April 2003[12] Peter Klapproth, “General Architectural Concepts for IP Core Re-Use “Proceedings of the 15th InternationalConference on VLSI Design (VLSIDí02), 2002

Mr. Farhan Aadil Malik is stud ent of M S

Soft wa re Eng ineering a t University of

Eng ineering & Tec hnology Taxila. He

earned his Bachelor’s degree in

Com pute r Scienc es from Allama Iqba l

Open University, Islamabad, Pakistan

in 2005 with distinction and currently working asProg ram mer a t UET Taxila . His c urrent a rea s of int erest

are ad hoc Networks and Data Communication

System s & Sec urity.

Mr. Shahzada Khayyam Nisar

co mpleted his graduation in Computer

Sc iences from Allam a Iqb al Op en

University, Islamabad Pakistan in 2004

with honors. He was awarded Allama Iqbal Award by

the University. He is a lso HEC Sc ho larship ho lde r.

Currently he is stud ent of M S Soft wa re Eng ineering a t

UET, Taxila . He ha s mo re tha n 5 yea rs of t ea c hing

expe rienc e, p resent ly wo rking a s Program me r at UET,

Taxila. His area s of interest a re Vehic ular ad hoc

Netw orks and Da ta C om munica tion System s & Sec urity.

Mr. Wajahat Abbas is pursuing his PhD

from University of Engineering &

Tec hno logy Taxila, Pakista n. He has

co mp leted his M.S in Comp uter

Eng inee ring from UET Taxila . He is a lso

working as Lecturer in the department

of Sof tw are Eng inee ring, UET Taxila . His a reas of inte rest

are Vehicular ad hoc Networks and Parallel &

Distribute d Com puting.

Mr. Asim Shahzad is pursuing his PhD

from University of Engineering &

Tec hno logy Taxila, Pakistan. He ha s

co mp leted his M.S in Comp uter

Eng ineering from UET Taxila a nd also he

has earned a n MS Degree in

Telec om mun ica tion Eng ineering from Institute of

Com munica tion Tec hnologies, Islama ba d Pakistan. He

is also working as Assistant Professor in the department

of Telec om munic a tion Eng inee ring , UET Taxila . His a reas

of interest are Optical Communication and Data &

network security.

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