10/20/05ELEC 5970-001/6970-001 Lecture 141 ELEC 5970-001/6970-001(Fall 2005) Special Topics in...
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10/20/05 ELEC 5970-001/6970-001 Lectur e 14 1 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Low-Power Logic Families Pass-Transistor Logic Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal [email protected]
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Transcript of 10/20/05ELEC 5970-001/6970-001 Lecture 141 ELEC 5970-001/6970-001(Fall 2005) Special Topics in...
10/20/05 ELEC 5970-001/6970-001 Lecture 14 1
ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic Circuits
Low-Power Logic FamiliesPass-Transistor Logic
Vishwani D. AgrawalJames J. Danaher Professor
Department of Electrical and Computer EngineeringAuburn University
http://www.eng.auburn.edu/[email protected]
10/20/05 ELEC 5970-001/6970-001 Lecture 14 2
Low-Power Logic Styles
• Pass transistor logic
• Dynamic logic
• Domino logic
• Adiabatic and charge recovery logic
• Asynchronous logic
• Logic restructuring
10/20/05 ELEC 5970-001/6970-001 Lecture 14 3
Pass-Transistor Logic
• Requires fewer transistors– Smaller area– Reduced capacitance– Reduced energy and power
10/20/05 ELEC 5970-001/6970-001 Lecture 14 4
AND Gate
A
B
F = AB
0
Need 4 transistors instead of 6 for CMOS gate.
10/20/05 ELEC 5970-001/6970-001 Lecture 14 5
Reduced Voltage Swing
VDD = 2.5V
IN
OUT
n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ
Vx = VDD – Vtn
10/20/05 ELEC 5970-001/6970-001 Lecture 14 6
Spice Simulation
Time, ns
0 0.5 1.0 1.5 2.0
3.0
2.0
1.0
0.0
Vo
ltage
, VIN
OUT
Vx
J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
10/20/05 ELEC 5970-001/6970-001 Lecture 14 7
Voltage Transfer Characteristic (VTC) of AND Gate
A
B
F = AB
0
n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ
10/20/05 ELEC 5970-001/6970-001 Lecture 14 8
VTC: Spice Simulation
Vin, V
0 0.5 1.0 1.5 2.0 2.5
3.0
2.0
1.0
0.0
F, V
IN
OUT
B = VDDA = 0 → VDD
A = VDD, B = 0 → VDDA = B = 0 → VDD
VDD – Vtn
10/20/05 ELEC 5970-001/6970-001 Lecture 14 9
Energy
VDD = 2.5V
0 → VDD
CL
T TE0→1 = ∫ P(t) dt = VDD ∫ i(t) dt
0 0
VDD-Vtn
= ∫ CL dVout = CL VDD (VDD – Vtn)0
If this voltage is insufficient for turning the pMOSTransistor in inverter off, leakage power will be consumed.
Vout
i(t)
10/20/05 ELEC 5970-001/6970-001 Lecture 14 10
Ways to Reduce Leakage
• Level restoration
• Multiple-threshold transistors
• Transmission-gate logic
10/20/05 ELEC 5970-001/6970-001 Lecture 14 11
Level Restoration
A
B
CL
Vout
VDD Level restorer
Level restorer device should be weaker than the nMOS pass transistor. Otherwise, VDD → 0 transition at Vout will be impossible.
Switching threshold= VDD/2
10/20/05 ELEC 5970-001/6970-001 Lecture 14 12
Multiple-Threshold Transistors• Use zero-threshold pass-transistors.• Use high-threshold transistors in all other
gates.• This can cause leakage through multiple
gates.
10/20/05 ELEC 5970-001/6970-001 Lecture 14 13
Leakage Through Zero-Threshold Transistors
0
1
1
0
Zero or low-threshold transistors
Leakage current path
10/20/05 ELEC 5970-001/6970-001 Lecture 14 14
Transmission-Gate Logic
• Provides both power and ground levels.• Good design, except needs more
transistors.
A
S
B
S’A’ + SB’
Inverting multiplexer
10/20/05 ELEC 5970-001/6970-001 Lecture 14 15
Transmission-Gate XOR
A AB’+A’B
B
10/20/05 ELEC 5970-001/6970-001 Lecture 14 16
Synthesis of PTL
A B C Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Shannon’s expansion:
Z = AB + BC + AC = A(B+BC+C) + A’(BC) = A(B+C) + A’BC = A[B+B’C] + A’[BC]
A 1 0
1 0 1 0B
C C1 0
Z
10/20/05 ELEC 5970-001/6970-001 Lecture 14 17
Pass-Transistor Cell
10/20/05 ELEC 5970-001/6970-001 Lecture 14 18
Synthesis of Z = A’B’ + BC’ + A’C
B
0A
C
Z
10/20/05 ELEC 5970-001/6970-001 Lecture 14 19
Synthesis of Z = A’ + BC’ + B’C0
B
B’
A
A’
C C’
Z
10/20/05 ELEC 5970-001/6970-001 Lecture 14 20
Synthesis of Z = AB’C’ + A’B’C
B
B’
A’
A
C’ C 1
Z
10/20/05 ELEC 5970-001/6970-001 Lecture 14 21
CPL: Complementary Pass-Transistor Logic
• Every signal and its complement is generated.
• Gates are static, because the output is connected to either VDD or GND.
• Design is modular; same cell can produce various gates by simply permuting the input signals.
• Also called differential pass-transistor logic (DPL)
10/20/05 ELEC 5970-001/6970-001 Lecture 14 22
A CPL Cell
10/20/05 ELEC 5970-001/6970-001 Lecture 14 23
CPL Cell Used As AND/NAND
A
B
A’
B’
B B’
Z = AB
Z=(AB)’
10/20/05 ELEC 5970-001/6970-001 Lecture 14 24
CPL Cell Used As OR/NOR
A
B
A’
B’
B’ B
Z = A+B
Z=(A+B)’
10/20/05 ELEC 5970-001/6970-001 Lecture 14 25
CPL Cell Used As XOR/XNOR
A
A’
A’
A
B’ B
Z = AB’+A’B
Z= AB+A’B’
10/20/05 ELEC 5970-001/6970-001 Lecture 14 26
References• G. R. Cho and T. Chen, “On the Impact of
Technology Scaling on Mixed PTL/Static Logic,” Proc. IEEE Int. Conf. Computer Design, 2002.
• R. Zimmermann and W. Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.
