10-1 Introduction Chapter #7: Sequential Logic Case Studies.

10-1

Introduction

Chapter #7: Sequential Logic Case Studies

10-2

IntroductionMotivation

• Flipflops: most primitive "packaged" sequential circuits

• More complex sequential building blocks:

Storage registers, Shift registers, Counters Available as components in the TTL Catalog

• How to represent and design simple sequential circuits: counters

• Problems and pitfalls when working with counters:

Start-up States Asynchronous vs. Synchronous logic

10-3

IntroductionChapter Overview

Examine Real Sequential Logic Circuits Available as Components

• Registers for storage and shifting

• Random Access Memories

• Counters

Counter Design Procedure

• Simple but useful finite state machine

• State Diagram, State Transition Table, Next State Functions

• Excitation Tables for implementation with alternative flipflop types

Synchronous vs. Asynchronous Counters

• Ripple vs. Synchronous Counters

• Asynchronous vs. Synchronous Clears and Loads

10-4

IntroductionKinds of Registers and CountersStorage Register

Group of storage elements read/written as a unit

4-bit register constructed from 4 D FFsShared clock and clear lines

TTL 74171 Quad D-type FF with Clear(Small numbers represent pin #s on package)

Schematic Shape

Q1

CLR

D3D2D1D0

171

Q1

Q0Q0

CLK Q3Q3Q2Q2

11

109

5

67

43

2

14

13

151

12

+

Clr

D3

D2

D1

D0

Clk

Q3S

R

Q2

Q1

Q0

10-5

IntroductionKinds of Registers and CountersInput/Output Variations

Selective Load CapabilityTri-state or Open Collector OutputsTrue and Complementary Outputs

74377 Octal D-type FFswith input enable

74374 Octal D-type FFswith output enable

EN enabled low andlo-to-hi clock transition

to load new data intoregister

OE asserted lowpresents FF state to

output pins; otherwisehigh impedence

D3

D6Q5

Q2

377

Q1Q0

Q3

EN CLK

Q6

Q4

Q7

D5

D2D1D0

D4

D7

1

3478

13141718

11

256912151619

HGFEDCBA

QHQGQFQEQDQCQBQA

OE

37411

1

3478

13141718

256912151619

CLK

10-6

IntroductionKinds of Registers and CountersRegister Files

Two dimensional array of flipflopsAddress used as index to a particular wordWord contents read or written

74670 4x4 Register File withTri-state Outputs

Separate Read and Write EnablesSeparate Read and Write AddressData Input, Q Outputs

Contains 16 D-ffs, organized asfour rows (words) of four elements (bits)

670

Q4

D1

D4D3D2

Q3Q2Q1

WE

WAWB

RE

RARB

54

11

1413

12

15123

10976

10-7

IntroductionKinds of Registers and CountersShift Registers

Storage + ability to circulate data among storage elements

Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal

Wrap around from rightmost element to leftmost element

Master Slave FFs: sample inputs while clock is high; change outputs on falling edge

Q 1 1 0 0 0

Q 2 0 1 0 0

Q 3 0 0 1 0

Q 4 0 0 0 1

Shift

Shift

Shift

Shift Direction\Reset

\ResetShift

CLK CLK CLK CLK

+

+

10-8

IntroductionKinds of Registers and Counters

Shift Register I/O

Serial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. Right

74194 4-bit UniversalShift Register

Serial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered Devices

S1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold state

Multiplexing logic on input to each FF!

Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications

10

7

6

5

4

3

2

11

1

9S1

S0

LSI

D

C

B

A

RSI

CLK

CLR

12

13

14

QD

QC

QA

QB

15

194

10-9

IntroductionKinds of Registers and CountersShift Register Application: Parallel to Serial Conversion

ParallelInputs

Serialtransmission

ParallelOutputs

10

76543

2

11

1

9S1S0LSIDCBA

RSI

CLK

CLR

QD

QC

QA

QB

19410

76543

2

11

1

9S1S0LSIDCBA

RSI

CLK

CLR

QD

QC

QA

QB

194

10

76543

2

11

1

9S1S0LSIDCBA

RSI

CLK

CLR

QD

QC

QA

QB

19410

76543

2

11

1

9S1S0LSIDCBA

RSI

CLK

CLR

QD

QC

QA

QB

194

Clock

D7

D6D5

D4

D7

D6D5

D4

D3

D2D1

D0

D3

D2D1

D0

10-10

IntroductionKinds of Registers and CountersCounters

Proceed through a well-defined sequence of states in response to count signal

3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...

3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...

Gray Code Counter : 000, 001, 011, 010, 110, 100, 101, 111, ...

Binary vs. BCD vs. Gray Code Counters

A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output

A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output

10-11

IntroductionKinds of Registers and Counters

Ring Counter

1000, 0100, 0010, 0001, 1000, ...

Shift Direction\Reset

\ResetShift

CLK CLK CLK CLK

+

+

J

K

Q

/Q

10-12

IntroductionKinds of Registers and CountersJohnson (Mobius) Counter

End-Around

8 possible states, single bit change per state, useful for avoiding glitches

J CLK K

S

R

Q

Q

+

+

+ +

0 1

Shift

Q 1 Q 2 Q 3 Q 4

\Reset

J

K

S

R

Q

Q

J

K

S

R

Q

Q

J

K

S

R

Q

Q CLK CLK CLK

1

0

0

0

1

1

0

0

1

1

1

0

1

1

1

1

0

1

1

1

0

0

1

1

0

0

0

1

0

0

0

0

Shift

Q 1

Q 2

Q 3

Q 4

100

10-13

IntroductionKinds of Registers and CountersCatalog Counter

74163 Synchronous4-Bit Upcounter

Synchronous Load and Clear Inputs

Positive Edge Triggered FFs

Parallel Load Data from D, C, B, A

P, T Enable Inputs: both must be asserted to enable counting

RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output"

74161: similar in function, asynchronous load and reset

QAQBQCQD

163RCO

PT

ABCD

LOAD

CLR

CLK2

710

15

9

1

3456

14

1211

13

10-14

IntroductionKinds of Registers and Counters74163 Detailed Timing Diagram

CLK

A

B

C

D

LOAD

CLR

P

T

Q A

Q B

Q C

Q D

RCO 12 13 14 15 0 1 2

Clear Load Count Inhibit

10-15

IntroductionCounter Design ProcedureIntroduction

This procedure can be generalized to implement ANY finite state machine

Counters are a very simple way to start: no decisions on what state to advance to next current state is the output

Example: 3-bit Binary Upcounter

Decide to implement withToggle Flipflops

What inputs must bepresented to the T FFsto get them to change

to the desired state bit?

This is called"Remapping the Next

State Function"State TransitionTable

FlipflopInput Table

PresentState

NextState

FlipflopInputs

110

111

001

010

011

101

100

State TransitionDigram

000

10-16

IntroductionCounter Design ProcedureIntroduction

This procedure can be generalized to implement ANY finite state machine

Counters are a very simple way to start: no decisions on what state to advance to next current state is the output

Example: 3-bit Binary Upcounter

Decide to implement withToggle Flipflops

What inputs must bepresented to the T FFsto get them to change

to the desired state bit?

This is called"Remapping the Next

State Function"

State TransitionTable

FlipflopInput Table

PresentState

NextState

FlipflopInputs

110

111

001

010

011

101

100

State TransitionDigram

000

10-17

IntroductionCounter Design ProcedureExample Continued

K-maps for Toggle Inputs:

Resulting Logic Circuit:

CB00 01 11 10A

0

1

TA =

CB00 01 11 10A

0

1

TB =

CB00 01 11 10A

0

1

TC =

10-18

Introduction

Count

\Reset

Q C

Q B

Q A

100

Counter Design ProcedureExample Continued

K-maps for Toggle Inputs:

Resulting Logic Circuit:

Timing Diagram:

T

CLK

\Reset

Q

Q

S

R

QAT

CLK

Q

Q

S

R

QBT

CLK

Q

Q

S

R

QC

Count

+

TB = A

TC = A • B

T A = 1

CB A

C

00 01 11 10

0

1

B

1 1 1 1

1 1 1 1

CB

A

C

00 01 11 10

0

1

B

0 0 0 0

1 1 1 1

CB A

C

B

00 01 11 10

0

1

0 0 0 0

0 1 1 0

10-19

IntroductionCounter Design Procedure

More Complex Count Sequence

Step 1: Derive the State Transition Diagram

Count sequence: 000, 010, 011, 101, 110

Step 2: State Transition Table

PresentState

NextState

10-20



Step 1: Derive the State Transition Diagram

Count sequence: 000, 010, 011, 101, 110

Step 2: State Transition Table

Note the Don't Care conditions

PresentState

NextState

10-21



Step 3: K-Maps for Next State Functions

CB00 01 11 10A

0

1

C+ =

CB00 01 11 10A

0

1

A+ =

CB00 01 11 10A

0

1

B+ =

10-22



Step 3: K-Maps for Next State Functions

CB00 01 11 10A

0

1

0

1X1X

X00

C

B

C+

CB00 01 11 10A

0

1

1

1X0X

X01

C

B

B+

CB00 01 11 10A

0

1

0

0X1X

X01

C

B

A+

10-23


More Complex Counter Sequencing

Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions

Toggle ExcitationTable

Remapped Next StateFunctions

PresentState

ToggleInputs

10-24



Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions

Toggle ExcitationTable

Remapped Next StateFunctions

PresentState

ToggleInputs

10-25


More Complex CounterSequencing

Remapped K-Maps

TC =

TB =

TA =

CB00 01 11 10A

0

1

TC

CB00 01 11 10A

0

1

TA

CB00 01 11 10A

0

1

TB

10-26


More Complex CounterSequencing

Remapped K-Maps

TC = A C + A C = A xor C

TB = A + B + C

TA = A B C + B C

B

C

00 01 11 10A

0

1

0 0 X1

X 1 X 0

CB

B

TC

00 01 11 10A

0

1

1 0 X1

X 1 X 1

CB C

B

TB

00 01 11 10

0

1

0 X0

X 0 X 1

CB C

1A

10-27



Resulting Logic:

Timing Waveform:

5 Gates13 Input Literals + Flipflop connections

0

0

0

0

0

0

0

1

0

0

1

1

1

0

1

1

1

0

0

0

0

100

Count

\Reset

C

B

A

TCT

CLK

Q

Q

S

RCount

T

CLK

Q

Q

S

R

TBC

\C

B A

\B \A

TAT

CLK

Q

Q

S

R

\Reset 1

0

TA

AC

A/BC

TC /AB/C

TB /B

C

10-28

IntroductionSelf-Starting CountersStart-Up States

At power-up, counter may be in possible state

Designer must guarantee that it (eventually) enters a valid state

Especially a problem for counters that validly use a subset of states

Self-Starting Solution:Design counter so that even the invalid states eventually transition to valid state

Two Self-Starting State Transition Diagrams for the Example Counter

Implementationin Previous

Slide!110

111

000

010

001 011 100

101

110

111

000

010

001 011 100

101

10-29

IntroductionSelf-Starting CountersDeriving State Transition Table from Don't Care Assignment

Present State

Next State

C+ 0 1 0 1 0 1 0 1

B+ 1 1 1 0 1 1 0 0

A+ 0 1 1 1 1 0 0 1

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

State Transition Table

00 01 11 10A

0

1

0 0 11

1 1 0 0

CB

B

TC

Input to Toggle Flip-Flops

c

00 01 11 10A

0

1

1 0 11

1 1 1 1

CB

B

TB

c

00 01 11 10A

0

1

0 1 10

0 0 0 1

CB

B

TA

c

00 01 11 10A

0

1

0 0 00

1 1 1 1

CB

B

C+

c

00 01 11 10A

0

1

1 1 10

1 0 0 1

CB

B

B+

c

00 01 11 10A

0

1

0 1 10

1 1 1 0

CB

B

A+

c

State Changes

10-30

IntroductionSelf-Srarting Counters

Counter Reset

Usual to have a distinguished starting state for the counter or finite state

machine

Desirable to include additional hardware to reset the counter to this state

Use reset signal to place flipflops in the desired starting state

10-31

IntroductionImplementation with Different Kinds of FFs

Toggle - natural

D - compatible with CAD software such as espresso

JK - fewest gates in usual

As the level of integration continues to increase saving a gate here orthere becomes less of an use

10-32

IntroductionImplementation with Different Kinds of FFsR-S Flipflops

Continuing with the 000, 010, 011, 101, 110, 000, ... counter example

RS Exitation Table

Q+ = S + R Q

Remapped Next State Functions

PresentState

NextState Remapped Next State

10-33

IntroductionImplementation with Different Kinds of FFsRS FFs Continued

RC =

SC =

RB =

SB =

RA =

SA =

CB00 01 11 10A

0

1

RC

CB00 01 11 10A

0

1

RA

CB00 01 11 10A

0

1

RB

CB00 01 11 10A

0

1

SC

CB00 01 11 10A

0

1

SA

CB00 01 11 10A

0

1

SB

10-34

IntroductionImplementation with Different Kinds of FFsRS FFs Continued

RC = A

SC = A

RB = A B + B C

SB = B

RA = C

SA = B C

B

00 01 11 10

0

1

X X1

X 0 X 0

CB C

XA

B

00 01 11 10

0

1

0 X0

X 1 X X

CB C

0A

B

00 01 11 10

0

1

0 X1

X 1 X 0

CB C

0A

B

00 01 11 10

0

1

X XX

X 0 X 1

CB C

0A

B

00 01 11 10

0

1

1 X0

X 0 X 1

CB C

XA

B

00 01 11 10

0

1

0 X0

X X X 0

CB C

1A

RC

RB

RA

SC

SB

SA

10-35

IntroductionImplementation With Different Kinds of FFsRS FFs Continued

Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections

CLK CLK CLK

\ A R

S A

C

\ C

Q

Q

RB

\ B

R

S

Q

Q \ B

B C

SA

R

S

A

\A

B

A C B

\C RB SA

Q

Q

Count

10-36

IntroductionImplementation with Different FF TypesJ-K FFs

J-K Excitation Table

Q+ = J Q + K Q

Remapped Next State Functions

PresentState

NextState Remapped Next State

10-37

IntroductionImplementation with Different FF TypesJ-K FFs Continued

JC =

KC =

JB =

KB =

JA =

KA =

CB00 01 11 10A

0

1

JC

CB00 01 11 10A

0

1

JA

CB00 01 11 10A

0

1

JB

CB00 01 11 10A

0

1

KC

CB00 01 11 10A

0

1

KA

CB00 01 11 10A

0

1

KB

10-38


JC = A

KC = A

JB = 1

KB = A + C

JA = B C

KA = C

B

00 01 11 10

0

1

0 XX

X 1 X X

CB C

0A

B

00 01 11 10

0

1

X X1

X X X 0

CB C

XA

B

00 01 11 10

0

1

1 XX

X X X 1

CB C

XA

B

00 01 11 10

0

1

0 X0

X X X X

CB C

1A

B

00 01 11 10

0

1

X X1

X 1 X X

CB C

0A

B

00 01 11 10

0

1

X XX

X 0 X 1

CB C

XA

JC

JB

JA

KC

KB

KA

10-39


Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections

CLK CLK CLK J

K

Q

Q

A

\ A

C

\ C KB

J

K

Q

Q

B

\ B

+

J

K

Q

Q

JA

C

A

\ A

B \ C

Count

A C KB JA

10-40

IntroductionImplementation with Different FF TypesD FFs

Simplest Design Procedure: No remapping needed!

DC = A

DB = A C + B

DA = B C

Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections

CLK CLK

D Q

Q

A

\ A

D Q

Q

DA DB B

\ B CLK

D Q

Q

A C

\ C Count

\ C \ A

\ B

B \ C DA DB

10-41

IntroductionImplementation with Different FF TypesComparison

• T FFs well suited for straightforward binary counters

But yielded worst gate and literal count for this example!

• No reason to choose R-S over J-K FFs: it is a proper subset of J-K

R-S FFs don't really exist anyway

J-K FFs yielded lowest gate count

Tend to yield best choice for packaged logic where gate count is key

• D FFs yield simplest design procedure

Best literal count

D storage devices very transistor efficient in VLSI

Best choice where area/literal count is the key

10-42

IntroductionAsynchronous vs. Synchronous CountersRipple Counters

Deceptively attractive alternative to synchronous design style

Count signal ripples from left to right

State transitions are not sharp!

Can lead to "spiked outputs" from combinational logic decoding the counter's state

Can lead to "spiked outputs" from combinational logic decoding the counter's state

T

Count

Q

QA

T Q

QB

T

CLK

Q

QC

CLK CLK

10-43

IntroductionAsynchronous vs. Synchronous CountersCascaded Synchronous Counters with Ripple Carry Outputs

First stage RCOenables second stage

for counting

RCO assertedsoon after stageenters state 1111

also a functionof the T Enable

Downstream stageslag in their 1111 to

0000 transitions

Affects Count periodand decoding logic (1) Low order 4-bits = 1111

(2) RCO goes high

(3) High order 4-bits are incremented

10-44

Introduction

Clock

Load

D

C

B

A

100

Asynchronous vs. Synchronous CountersThe Power of Synchronous Clear and Load

Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...

Use RCO signal to trigger Load of a new state

Since 74163 Load is synchronous, state changes only on the next rising clock edge

0110is the state

to be loaded

L O A D

C L R

C L K

R C O

P T

Q A

Q B

Q C

Q D1

6 3

Load

D C B A

0 1++

D C B A

10-45

IntroductionAsynchronous vs. Synchronous CountersOffset Counters Continued

Ending Offset Counter: e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

Decode state todetermine when to

reset to 0000

Clear signal takes effect on the rising count edge

Replace '163 with '161, Counter with Async ClearClear takes effect immediately!

C L R

L O A D

C L KP T

1 6 3

R C O

Q Q Q Q D C B A

CLR

D C B A

1 0

D C B A

+

10-46

IntroductionRandom Access MemoriesStatic RAM

Transistor efficient methods for implementing storage elements

Small RAM: 256 words by 4-bit

Large RAM: 4 million words by 1-bit

We will discuss a 1024 x 4 organization

Data Data

Word Enablei

j j

Static RAM Cell

Static RAM CellStatic RAM Cell

Words = Rows

Columns = Bits (Double Rail Encoded)

use MOS small # easy to implement

10-47

IntroductionRandom Access Memories

Static RAM Organization

Chip Select Line (active lo)

Write Enable Line (active lo)

10 Address Lines

4 Bidirectional Data Lines

1024 x 4 SRAM

A0A1A2A3A4A5A6A7A8A9WECS

IO0IO1IO2IO3

10-48


RAM Organization

Long thin layouts are not the best organization for a RAM

Address Buffers

Row Decoders

A9

A8

A7

A6

A5

A4

Storage ArrayStorage Matrix

64 x 16 64 x 16 64 x 16 64 x 16

Sense Amplifiers

Address Buffers

Column Decoders

A3

A2

A1

A0

Data BuffersCS

WE

I/O0 I/O1 I/O2 I/O3

64 x 64SquareArray

Amplifers &Mux/Demux

Some Addrbits select

row

Some Addrbits selectwithin row

10-49

IntroductionRandom Access MemoriesRAM Timing

Simplified Read Timing

Simplified Write Timing

WE

CS

Address

Data Out Data Out

V alid Address

Access T ime

Input Data

V alid Address

Data In

Address

WE

CS

Memory Cycle T ime

10-50


Dynamic RAMs

Word Line

Bit Line

1 Transistor (+ capacitor) memory element

Read: Assert Word Line, Sense Bit Line

Write: Drive Bit Line, Assert Word Line

Destructive Read-Out

Need for Refresh Cycles: storage decay in ms

Internal circuits read word and write back

10-51


DRAM Organization

Row Decoders

Storage Matrix

64 x 64

Column Latches, Multiplexers/Demultiplexers

Control Logic

A11

WE

. . .

A0

RAS

CAS

DIN

Row AddressColumn Address & Control Signals

DOUT

Long rows to simplify refresh

Two new signals: RAS, CAS

Row Address Strobe

Column Address Strobe

replace Chip Select

10-52

IntroductionRandom Access Memory

RAS, CAS Addressing

Even to read 1 bit, an entire 64-bit row is read!

Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits!

Address RAS CAS Dout Valid

Col AddressRow Address

Read Cycle

Read RowRow Address Latched

Read Bit Within RowColumn Address Latched

Tri-stateOutputs

10-53

IntroductionRandom Access MemoryWrite Cycle Timing

Address RAS CAS WE Din Valid

Col AddressRow Address

(1) Latch Row Address Read Row

(2) WE low

(3) CAS low: replace data bit

(4) RAS high: write back the modified row

(5) CAS high to complete the memory cycle

10-54


RAM Refresh

Refresh Frequency:

4096 word RAM -- refresh each word once every 4 ms

Assume 120ns memory access cycle

This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!

But RAM is really organized into 64 rows

This is one refresh cycle every 62.5 s (1 in 500 DRAM accesses)

Large capacity DRAMs have 256 rows, refresh once every 8 s 512 rows, refresh once every 16 s

RAS-only Refresh (RAS cycling, no CAS cycling)

External controller remembers last refreshed row

Some memory chips maintain refresh row pointer

CAS before RAS refresh: if CAS goes low before RAS, then refresh

4ms

ns x 64

x 4

250 s 500 s

10-55

IntroductionRandom Access MemoryDRAM Variations

Page Mode DRAM:

read/write bit within last accessed row without RAS cycle

RAS, CAS, CAS, . . ., CAS, RAS, CAS, ...

New column address for each CAS cycle

Static Column DRAM:

like page mode, except address bit changes signal new cyclesrather than CAS cycling

on writes, deselect chip or CAS while address lines are changing

Nibble Mode DRAM:

like page mode, except that CAS cycling implies next columnaddress in sequence -- no need to specify column address afterfirst CAS

Works for 4 bits at a time (hence "nibble")RAS, CAS, CAS, CAS, CAS, RAS, CAS, CAS, CAS, CAS, . . .

10-56


Detailed SRAM Timing

Read Cycle

Access time : takes for an address change to cause new data to appear at the outputCycle time : between the start of one read operation and a subsequent read

SRAM : access time = cycle timeSRAM : access time < cycle time

10-57

IntroductionChapter Summary

# The Variety of Sequential Circuit Packages Registers, Shifters, Counters, RAMs

# Counters as Simple Finite State Machines

# Counter Design Procedure 1. Derive State Diagram 2. Derive State Transition Table 3. Determine Next State Functions 4. Remap Next State Functions for Target FF Types Using Excitation Tables; Implement Logic

# Different FF Types in Counters J-K best for reducing gate count in packaged logic D is easiest design plus best for reducing wiring and area in VLSI

# Asynchronous vs. Synchronous Counters Avoid Ripple Counters! State transitions are not sharp Beware of potential problems when cascading synchronous counters Offset counters: easy to design with synchronous load and clear Never use counters with asynchronous clear for this kind of application

10-1 Introduction Chapter #7: Sequential Logic Case Studies.

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Transcript of 10-1 Introduction Chapter #7: Sequential Logic Case Studies.