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Tuesday, July 04, 2006

"Programs expand to fill the memory available to hold

them."

- Modified Parkinson’s Law.

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Contiguous allocation

Suffers from external fragmentationCompaction is time consumingUsed in earlier batch systemsWhat if a process needs to grow beyond the

partition allocated to it?

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Paging

Permit address space of processes to be non-contiguous.

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Paging – Hardware support

Pages and framesPage number and offsetInternal fragmentation

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Address Translation Architecture

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Why are page sizes powers of two?

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Every memory access has to go through the page table.

Hardware page table Limited number of entries

Paging increases context switch time

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Implementation of Page Table

Page table is kept in main memory.Page-table base register (PTBR) points

to the page table.Context switch time compared to

hardware page table.

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Implementation of Page Table

In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.

Solution: fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs).

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Paging Hardware With TLB

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TLB

Context switchAddress space IDs

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Effective Access Time

Associative Lookup = time unitAssume memory cycle time is 1 microsecondHit ratio – percentage of times that a page

number is found in the associative registers; ration related to number of associative registers.

Hit ratio =

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Effective Access Time

Associative Lookup = time unitHit ratio = Effective Access Time (EAT)

EAT = (1 + ) + (2 + )(1 – )

= 2 + –

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Page Table Size

Internal fragmentationUnused program in memoryPage table size

Hardware page table

Transfers to and from disk

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Memory Protection

Memory protection implemented by associating protection bit with each frame.

Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the

process’ logical address space, and is thus a legal page.

“invalid” indicates that the page is not in the process’ logical address space.

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Valid (v) or Invalid (i) Bit In A Page Table

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Two-Level Paging ExampleA logical address (on 32-bit machine with 4K page size) is divided into:

a page number consisting of 20 bits. a page offset consisting of 12 bits.

Since the page table is paged, the page number is further divided into: a 10-bit page number. a 10-bit page offset.

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Two-Level Paging ExampleThus, a logical address is as follows:

where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table.

page number page offset

pi p2 d

10 10 12

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Address-Translation Scheme

Address-translation scheme for a two-level 32-bit paging architecture

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Inverted Page Table

One entry for each real page of memory.Entry consists of the virtual address of the

page stored in that real memory location, with information about the process that owns that page.

Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.

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Inverted Page Table Architecture

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Hashed Page Tables

Common in address spaces > 32 bits.

The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.

Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

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Hashed Page Table

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Shared Pages Example

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Virtual Memory That is Larger Than Physical Memory

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Transfer of a Paged Memory to Disk Space

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Valid-Invalid Bit

With each page table entry a valid–invalid bit is associated(1 in-memory, 0 not-in-memory)

Initially valid–invalid bit is set to 0 on all entries.

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Valid-Invalid BitExample of a page table snapshot.

During address translation, if valid–invalid bit in page table entry is 0 page fault.

111

1

0

00

Frame # valid-invalid bit

page table

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Page Table When Some Pages Are Not in Main Memory