1 MAVEN PFP SWIA Electrical Pre-CDR Peer Review MAVEN SWIA Electrical Pre-CDR Peer Review May 11,...

1MAVEN PFP SWIA Electrical Pre-CDR Peer Review

MAVEN SWIA Electrical Pre-CDR Peer Review

May 11, 2011

E. Taylor

Space Science Laboratory

University of California - Berkeley


SWIA Electrical Team

• Jasper Halekas (Instrument Lead)• Ellen Taylor (Digital Electronics, Preamp Board, Anode Board)• Dorothy Gordon (FPGA)• Peter Berg (MCPHV Power Supply)• Selda Heavner (LVPS Power Supply Board)• Chris Tiu (Sweep HV Power Supply Board)• Peter Harvey (FSW [PFDPU])• Dave Curtis (System Interfaces) • Tim Quinn (GSE)• Jorg Fischer (QA) • AnLoc Le (Parts Lead)


Overview

• Block Diagram• For each board (Digital, Pre-amp, Anode):

– Functional and Interface Requirements– EM Verification/Status– Changes since PDR– Changes for Flight

Note: HVPS/LVPS boards and FPGAs are covered in separate peer reviews.

• EM Integrated Electronics Test Results• Parts Stress Analysis, Parts Status and Issues• Review of Responses to PDR Actions/Recommendations


Electrical Requirements and Interfaces

• REQUIREMENTS and SPECIFICATIONS– MAVEN-PF-SWIA-001i SWIA Instrument Specification

• Functional and Performance Requirements • Resource Allocations (board size, power budget)• Environmental Requirements (thermal, vibration, radiation)

– MAVEN-PF-QA-002 UCB Mission Assurance Implementation Plan• Parts Level, Burn-In, Derating

– MAVEN-PF-SYS-003 Power Converter Requirements • Power voltages, current, ripple, transients

– MAVEN-PF-SWIA-012 FPGA Specification• PFDPU CLK/TLM/CMD Interface• HV Enable (RAW and MCP) and DAC Control (Sweep and Fixed)• Pre-amp Input, Test Pulser Output• Housekeeping and Memory (external SRAM) I/F

• INTERFACES (electrical only)– MAVEN-PF-SYS-004 PFIDPU ICD

• PFDPU Serial I/F and power description– MAVEN-PF-SYS-016 Pinouts

• Connector Description and Pin-outs– MAV-RQ-09-0015 Particle and Fields to Spacecraft ICD

• Heater, Thermistor and Cover Actuator Interface


SWIA Electrical Block Diagram


SWIA Interconnect (Requirements)

• Modular design for easy board-to-board assembly/disassembly (SWIA-017)

• Connectors organized to minimize signal paths across and between boards (SWIA-024, -027)

• HV routed safely from lower boards to deflectors and MCP through coax cables (SWIA-019)

• Airborn WTAX stackable board-to-board connectors used when possible (SWIA-025)

• Signal connectors between Anode-Preamp are Hypertronics KA-17 (SWIA-025)

• Survival heaters and thermistors are redundantly controlled by the spacecraft (SWIA-010, -011), routed through connector and winchesters

• Wiring to deflectors, actuator signals, etc. routes along housing on the anti-sunward side (+X), opposite the solar wind direction (SWIA-122, -123)

SENSOR

S W I -J 1

S W I -J 8

P ig t a ils

S W I A E N C L O S U R E

W I N -4A TTN

S W I -J 1 2

S W I -J 6 PFDPU

A NODE

TH E R M

F R O M S / C

S W I -J 7

H TR

C O V E R

W TA X3 6

D B 9 M

W TA X2 0

W I N -3

SW P/DEF HV PS

S W I -J 5

D B 9 FH V E N AB L EP L U G

F R O MP F D P U

S W I -J 4

S W I -J 1 4

S W I -J 1 1

S W I -J 1 3

S W I -J 9

LV PS

W I N -2

M C P _ H V

S W I -J 1 0

W I N -1

S W I -J 1 5

S W I -J 3

C O AX

S W P

PRE-A MP andMCP SUPPLY

S W I -J 2

H D 1 5 M

D B 9 M

H D -1 5 F

D E F 2

a n ti -s u n

D E F 1

DIGITA L

a n ti -s u n

TO PFIDPU


SWIA Interconnect Changes since PDR

Only very minor changes since PDR

• HVPS Enable Plug moved from Digital Board to LVPS Board (easier mechanical access)

• Attenuator signal comes into separate connector (SWI-J4) on the SWIA “dog-house” instead of being routed through Digital Board connector

TO PFIDPU

PDR Revision (MAVEN-PF-SWI-SCH-005 rev 4)


SWIA Interconnect EM Verification

• Bare boards have been fully integrated and fit-checked in mechanical chassis

• Basic stack-up assembly/disassembly verified

• Minor issue with digital board-to-shield clearance. 2 parts on the bottom of board do not meet minimum dynamic clearance requirements. May require custom stand-off between board and shield.

• Next step is to integrate loaded boards, check grounding scheme and noise environment (part of SWIA calibration)


Anode Board Design (Requirements)

Anode board routes signals from and HV to MCPs • Consists of 10 x 4.5 and 14 x 22.5 degree discrete

charge collection anodes centered around anti-sunward direction (SWIA-501)

• Metallization is directly on the board, with window between spacers exposing the anode pads to the MCP output face (SWIA-504)

• Mounts on a circular board with same outer diameter as E-box (SWIA-503)

• Signal routed through a surge resistor (51 ohms) to provide a DC path for anode current (SWIA-507)

• Drain resistor (1 Mohm) bleeds off charge and prevent discharge (SWIA-507)

• Two diodes provide a bipolar voltage clamp to suppress voltage spikes (SWIA-508)

• Signal connections have short path length to reduce capacitance, and are routed to avoid cross-talk and noise (SWIA-511)

• Board has internal ground plane shielding anodes from each other (SWIA-512) MCP Contact

Large Anode Pad

Small Anode Pads


SWIA Anode Board Schematics

Ground ReturnResistor Sets MCP OutputVoltage

24 anodes split 12 to each connector10 small plus 2 large anodes12 remaining large anodes

Removed HV Capacitor (adequate keep-out zone difficult to maintain)

PDR Slide

Changed from custom HV capacitor rated at 3kV to standard 200V


SWIA Anode Schematic Details

Drain resistorprovides DCcurrent path

Surge limitresistor

Clamp diodes suppressvoltage spikes

PDR Slide


Anode Board Design EM Verification

• Anode board fabricated, tested, integrated with SWIA EM MCPs and currently being used for MCP calibration

• No change to layout for flight except removing HV capacitor (EM testing is being conducted without capacitor on board)


Digital Board Design (Requirements)

• Command/Data Interface to PFDPU (SWIA-912)

• Accumulate counts from each of the 24 anodes (SWIA-909)

• Bin data and generate data products for transfer to PFDPU (SWIA-907)

• Enable HVPS and control MCP high voltage (SWIA-916)

• Control voltage sweeps for analyzer inner hemisphere and deflectors (SWIA-902)

• Provide programmable threshold for anode pulse amplifiers (SWIA-911)

• SRAM for storing lookup tables and accumulators (SWIA-918)

• Generate test pulses (SWIA-908)• Control ADC and MUX to read instrument

housekeeping monitors (SWIA-910)

• Note: Digital board does not control heaters (S/C), cover actuators (S/C), or attenuators (PFDPU)


SWIA Digital Board Interfaces

• FPGA Interface– SWIA-012B FPGA Specification

• Power on Reset • PFIDPU CLK/TLM/CMD• HV Enable (RAW and MCP)• DAC control (Sweep and Fixed)• Test Pulser Output, Anode Input• Housekeeping I/F• Memory I/F (external SRAM)

• PFDPU Interface– SYS-004B PFDPU ICD, Serial I/F– SYS-013E Harness, J2 Pin-out

• LVPS Board Interface– SYS-003C Power Converter Req.

• HVPS Board Interface– RAW, SWEEP, DEF1/2 power,

control and housekeeping• Pre-amp/MCP Board Interface

– MCP power/control/hsk, test pulser, anode pulses


SWIA Digital Schematics (FPGA)

Pre-amp Inputs

5V to 3.3V TranslatorsPower-on Reset

128K x 8 SRAM

HSK I/F

DAC I/F

Test and Spares

Decoupling Caps

Test Pulse

HV EnablePDR Slide

PFDPU I/F


SWIA Digital Schematics (Sweep DACs)

Deflector supply controls are multipliers based on Sweep voltage to increase dynamic range

On-going discussion about correct multiplier to avoid saturation

16-bit DAC provides sufficient accuracy over full dynamic range

PDR Slide


Digital Board Verification

Digital Board Test per MAVEN-SWI-PROC-001a verifies:• TLM/CMD connectivity with MISG• Power distribution to test points• Power consumption by service• Power generation (+/-4V reference

voltage for DACs)• Polarity on all polarized capacitors• Analog (raw and converted) and digital

housekeeping • Test pulser generation and frequency• High voltage allow, arm, enable• Fixed DAC control (MCP and Threshold)• Sweep DAC control (Sweep Raw,

Deflector 1 and 2) in diagnostic mode• Sweep DAC control by LUT• Anode Count Products (message receipt)• Soft Reset


FPGA Design and Test

SWIA FPGA is RTSX72SU-CQ208E• Heritage: STEREO SWEA (SIF FPGA) implemented in RTSX32S• System Clock = 1MHz – (CMDCLK received from DCB)• Estimated Power

– 75mW (28mA on 2.5V; 1.5mA on 3.3V) typical– 80mW (30mA on 2.5V; 1.8mA on 3.3V) at 70C

• Utilization Estimate– 75% (SWIA is worstcase) modules; ~100 I/Os

TEST VERIFICATION:• REV 0 initially tested on board• REV 1 fixed polarity on housekeeping enable• Pending REV 2 version:

– Fix LUT Write problem (missing one pointer bit for BUF1)– Fix P2 Product Symmetry (telemetry readout)– Fix P2 Product Bounding problem (EUPPER/LOWER, DUPPER/LOWER)– Add memory test mode– Add LUT checksum module


FPGA Block Diagram (module verification)

(TMKP)Timekeeper

(MCTL)Memory Control TCTL_PMRQ/ADR

HCTL_DHERRCLR

(CMIF)Command I/F &

Reset Conditioner TCTL_TLMDAT

Overall Block DiagramSWIA FPGA

05 MAY 2010

CMIF_PARMS

(SDAC)Sweep DAC Control

SLUT BufSelSDAC DiagMode[2:0]ENBSWEEPDACREGVALS (Diag)

SDAC_MEMRQ/ADR

TMKP_TSTBS

TMKP_TSTBS

MCTL_SDACDN

MCTL_SRAMADR/CNTL

SRAMDAT

SDAC_MEMRQ/ADR

SRAMDAT

CMDDAT

TMKP_CCNTS

CMIF_RST

TMKP_TSTBS

HCTL_DHERRCLR

MCTL_CMDIFDN

MCTL_CMDIFDNCMIF_MRQ/ADR

CMIF_MDATA

CMIF_ERRS

CMIF_TK4S

CMIF_PARMSTMKP_TSTBS

EVTOINTl[2:0]EVCONVLUT[15:0]ALLOWSTPFFASTRATEMODEMLUTBUFSEL[1:0]MassBiasOffsets, MassBinThresholdAnode Bin ThresholdsEvent Decimation Control/EnbAnodePulses[23:0]

TMKP_CCNTS

HWRSTIN

CMIF_TK4S

(FDAC)Fixed DAC Control

Fixed DAC Values (MCP, RAW,PreAmpThreshold[1:0])

FDAC_FD AC(CK, LD, CLR, DAT, CS)

SDAC _SWDAC(CK, LD, CLR, DAT)

SDAC_SWDACC S[2:1]

TMKP_TSTBS

TMKP_CCNTS

CMIF_PARMS

(HCTL)Housekeeping Control

HCTL_TDAT

HKADCDAT[15:0]

CMIF_ERRS

SWHSKPCHSEL

HCTL_ADCCNTL

HCTL_MUXADRSEL

(CKSM)LUT Checksummer

CKSM_LMRQ

TMKP_TSTBS

CKSM_LMRQ MCTL_LMDN

MCTL_LMDN

SRAMDAT

CKSM_TDAT

ACNT_AMRQ/ADR

MCTL_AMDN

SRAMDAT

MCTL_PRODDN

(TCTL)Telemetry Control

TLMENBS

HCTL_LASTCVCH

(TPGN)Test PulserGenerator

TPENB

TPGN_TPULSE

EXTERNAL_STATUS

LVPSCKTBKRSTAT, OCSTAT, ETC.

(ACNT)Anode Count Processing &

Product Accumulator

ACNT_AMRQ/ADR

CMIF_OCCTLOCSTAT

P2ELower[6:0], P2EUpper[6:0]P2DLower[4:0], P2DUpper[4:0]P2AnodeMask[23:0]P2EOffset[5:0]P2DOffset[3:0]P1 Mode (Lock versus Wrap)

ACNT_P2LASTEMAX[6:0]ACNT_P2LASTDMAX[4:0]ACNT_P2LASTAMAX[4:0]

SCLK

RST

Global

NOTE: SCLK = CMDCLK

INTERNAL SIGNALSEXTERNAL I/O

CommandableParameters

NOTE: RST = CMIF_RST

MCTL_AMDN

CKSM_TDAT

TMKP_CCNTS

CMIF_PARMS

CMIF_HVENB

CMIF_HVENB

CMIF_HVENB

CMIF_MRQ/ADRCMIF_MDATA

ACNT_P2LASTEMAX[6:0]ACNT_P2LASTDMAX[4:0]ACNT_P2LASTAMAX[4:0]

SRAMDAT

MCTL_PRODDN

TCTL_PMRQ/ADR

TMKP_TSTBS

TMKP_CCNTS

CMIF_PARMS

HCTL_TDAT

HCTL_LASTCVCH

CMIF_PARMS

TMKP_TSTBS

TMKP_CCNTS

MCTL_SDACDN

CMIF_PARMS

TMKP_TSTBS

verified

verified

verified

verified

verified

verifiedverified

verified

Pending Rev 2

Pending Rev 2


FPGA Data Product Verification

Pseudo Data Products

3-d Sky Plot

Energy Spectra

• SWIA Product Generation Options (selectively enabled/disabled) – P0: Raw Counts

• Outputs 24 16-bit counter values every 4 accumulation intervals (message generated every ~7ms)

– P1: Counts Accumulated over Anodes, Deflector Step (Acc. Interval) and Energy

• 10 NFOV Anodes summed into 2 bins => 16 Anode Counts

• 16 Anode Counts are integrated over two Energy Steps

• Outputs one 64 word message every other Energy Step (~83ms)

– P2: Peak Energy Capture• Operates like a logic analyzer – storing a

buffer and telemetering a programmable window around the peak

• All Data Products Verified


Pre-amp Board Design (Requirements)

• Amplify and transfer detector signals to digital board for accumulation

• Capable of counting at 2 MHz to prevent saturation in the solar wind (SWIA-608)– Drove selection of A121s

• Provide programmable threshold of 1e5-2e6 electrons (SWIA-609)– Two thresholds for two size anodes

• Test pulser inputs to allow for ground testing without High Voltage powered on (SWIA-606)

• Counter divides the test pulser into different rates for different anodes (SWIA-606)

• Sweep HV routed via a coax to the anode board, staying far from the preamp inputs (SWIA-610)

• MCP HV routed through the board, away from preamp inputs (SWIA-611)

• Preamp inputs will be located away from any high voltages or sources of noises (SWIA-612)

anode

MCP


SWIA Preamp Schematics

Test PulseDivider

Caps for noise suppression

Con

nect

or fr

om A

node

Connector to D

igitalPDR Slide


SWIA Preamp Schematic Details

Test Pulse InputCapacitively Coupled

Preamp InputAC-Coupled

ThresholdAdjust

Dead TimeSet to 100 ns

Pulse WidthSet to 50 ns

5V DigitalOutput

Resistor values for dead time and pulse width still needs to be finalized for flight

PDR Slide


Preamp Board Verification

Pre-amp crosstalk testing per MAVEN-SWI-PROC-005 verifies:• Threshold voltage level by anode group• Noise level with pulser off• Cross talk between all anodes

Pre-amp threshold testing per MAVEN-SWI-PROC-006 calculates:• Optimum threshold setting for each anode• Noise floor for each anode

Pre-amp characterization (using test board) Per MAVEN-SWI-PROC-007 verifies:• Dead time for different thresholds• Pulse width for different thresholds• Counts for different thresholds• Determines optimal threshold


Integrated DCB/Preamp Test Set-up

• Digital Board and Pre-amp boards integrated and tested


PFDPU Integration and Test

PFDPU integration per MAVEN-PF-TP-004 tested:• Safe-to-Mate• Command Test• Telemetry Test• Timing Test (not completed)• Aperture Test (not completed)• Power In-Rush Test

LVPSDCB

Preamp


Voltage Temperature Margin (VTM) Test

Voltage Temperature Margin Test per MAVEN-SWI-PROC-004:• Completed on the integrated SWIA Digital and Pre-amp ETU Boards in a thermal

chamber (Tenny ID 9009, Silver RM 180)• Operating voltages (+5VA, -5VA, 5VD, +3.3VD, and +2.5VD) are varied by +/-10%• Voltage margin test at room temp,

maximum cold (-45C = Limit -15C), andmaximum hot (+65C = Limit +15C) temperatures

Two issues noticed during this test:• Analog HSK not completely linear. Tracked this down to a solder bridge at the Actel

Socket between HSKDAT8 and HSKDAT9. Fixed and re-test shows Analog HSK very well behaved for nominal voltages +/-10%.

• Noticed 7-second “in-rush” current (additional 10-15mA current on +5VA line). Tracked this down to the time it takes the FPGA to set the thresholds to ½ scale on power up. Thresholds are 0.0V for 7 seconds and then get set to ~1/2 scale (~2V) by the FPGA. At zero threshold the preamps will count any noise and draw up to a few mA extra apiece. No change required.


Electronic Parts

• Electronic Part Status:– Flight BOMs provided to Parts Engineer– Active parts provided by GSFC– With very little exception, flight active parts being used on EM– Issue with lead time on HV capacitor on anode board resolved. Part removed

from design with no impact.

• Electronic Part Stress Analysis, using GSFC spreadsheet:– All capacitors meet 50% derating guidelines at maximum voltage– CDR capacitors are rated at 50V, which does not meet the requirement to use

100V rating for low voltage applications, requires additional part lot testing– All resistors meet derating guidelines, no changes required – All microcircuits meet derating guidelines– Have not completed spreadsheets for diodes, connectors, transistors

• Need to verify FETs (2N7389) are being used in safe operation region per request from GSFC Parts Control Board


SWIA Power Budget

Measured: ~ 55mW• ETU FPGA only 8mA on 2.5V (20mW).

Flight FPGA power will be ~ 3x this.• Calculated power using RT54SX72

power calculator for expected utilization is 75mW

• Overall digital board power may come down slightly

Measured: ~ 500mW, depends on counts• 96mA @ 5VA no counts• 125mA @ 5VA full counting

PDR Table


Digital Board PDR Peer RFAs (Back-up)

• PDR Schematics went through very detailed design review• Very little change from PDR Schematics to EM layout and build (all changes documented in

detailed revision logs)• Very little change from EM unit to FM unit

1 MAVEN PFP SWIA Electrical Pre-CDR Peer Review MAVEN SWIA Electrical Pre-CDR Peer Review May 11,...

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