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1 Day 1 Introduction to VLSI Physical Design Session Speaker Ajaya Kumar.s

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  • 1. Day 1Introduction to VLSI Physical DesignSession SpeakerAjaya Kumar.s 1

2. PEMP VSD531Session ObjectivesTo understand the Physical design flowTo understand the need for Physical designTo know about the tools used for physical designTo understand the concepts of CMOS process parametersTo know the issues of scaling and its effects M.S.Ramaiah School Of Advanced Studies 2 3. PEMP VSD531Session Topics Technology Evolution Scaling Issues Design Principles Verification and Simulation Detailed Physical Design Flow Foundry Files, Parameters, Rules and GuidelinesM.S.Ramaiah School Of Advanced Studies 3 4. PEMP VSD531Technology Evolution: Cost and IntegrationDrivers Moores Law is about cost Increased integration, decreased cost more possibilities for semiconductor-based products Pentium 4 die shot: 2.2cm M.S.Ramaiah School Of Advanced Studies 4 5. PEMP VSD531Sense of Scale (Scaling)What fits on a VLSI Chip today?State of the art logic chip 0.13mm (2 l) 20mm on a side (400mm2) 0.13mm drawn gate length 0.5m wire pitch 8-level metalFor comparison 32b RISC processor8K l x 16Kl 0.5mm SRAM(8 l)about 32l x 32l per bit8K x 16K is 128Kb, 16KB DRAM64b FP8l x 16l per bit Processor8K x16K is 1Mb, 128KB20mm32b RISC(40,000 wire pitches)Processor 320,000 lM.S.Ramaiah School Of Advanced Studies5 6. PEMP VSD531MOS Transistor Scaling (1974 to present)S=0.7 Met Poly[0.5x per 2 nodes]al Pitc Pitc hh (Typical (Typical DRAM) MPU/ASIC)Decreased transistor/feature sizesIncreased variability (tox, BEOL, DFM, SEU, etc.)Short channel effect, leakage powerM.S.Ramaiah School Of Advanced Studies 6 7. PEMP VSD531 SEMATECH Prototype BEOL stack, 2000 Passivation Wire Dielectric Etch Stop Layer Via Global (up to 5) Dielectric Capping Layer Copper Conductor with Barrier/NucleationIntermediate (up to 4) LayerLocal (2)Pre Metal DielectricTungsten Contact PlugReverse-scaled global interconnects Growing interconnect complexity Performance critical global interconnectsM.S.Ramaiah School Of Advanced Studies7 8. PEMP VSD531 Intel 130nm BEOL Stack Intel 6LM 130nm process with vias shown (connecting layers)Aspect ratio = thickness / minimum width M.S.Ramaiah School Of Advanced Studies 8 9. PEMP VSD531 Interconnect Capacitance: Parallel Plate ModelILD = interlevel dielectric LWTHILDBottom plate of SiO2cap can beanother metal Substratelayer Cint = eox * (W*L / tox) M.S.Ramaiah School Of Advanced Studies9 10. PEMP VSD531Line Dimensions and Fringing CapacitanceLateral capw SCapacitive coupling Crosstalk effect Signal integrityM.S.Ramaiah School Of Advanced Studies10 11. PEMP VSD531Interconnect Evolution and Modeling Needs Before 1990, wires were thick and wide while devices were big and slowLarge wiring capacitances and device resistancesWiring resistance gate input capacitance Better predictionInterconnect resistance no longer ignorable Better modeling: distributed R(L)C network, AWE, etc. Effective capacitance < total load capacitanceInterconnect delay > gate delay for sub-micron technologiesM.S.Ramaiah School Of Advanced Studies12 13. PEMP VSD531Sub-Wavelength Optical Lithography M.S.Ramaiah School Of Advanced Studies13 14. PEMP VSD531Complexity of PhotomasksHow many wafers, on average, are printed with a mask set? M.S.Ramaiah School Of Advanced Studies14 15. PEMP VSD531Summary of Technology ScalingScaling of 0.7x every three (two?) years .25u.18u.13u .10u.07u .05u 199719992002 20052008 2011 5LM 6LM 7LM7LM 8LM9LMInterconnect delay dominates system performance consumes up to 70% of clock cycleCross coupling capacitance is dominating cross capacitance 100%, ground capacitance 0% ground capacitance is 90% in .18u huge signal integrity implications (e.g., guardbands in static analysis approaches)Multiple clock cycles required to cross chip whether 3 or 15 not as important as fact of multiple > 1 M.S.Ramaiah School Of Advanced Studies15 16. PEMP VSD531New Materials Implications Lower dielectric permittivityreduces total capacitancedoesnt change cross-coupled / grounded capacitance proportions Copper metallizationreduces RC delayavoids electromigration (factor of 4-5 ?)thinner deposition reduces cross cap Multiple layers of routingenabled by planarization; 10% extra cost per layerreverse-scaled top-level interconnectsrelative routing pitch may increaseroom for shielding M.S.Ramaiah School Of Advanced Studies 16 17. PEMP VSD531Technical Issues Manufacturability (chip cant be built) antenna rules minimum area rules for stacked vias CMP (chemical mechanical polishing) area fill rules layout corrections for optical proximity effects in subwavelength lithography; associated verification issues Signal integrity (failure to meet timing targets) crosstalk induced errors timing dependence on crosstalk IR drop on power supplies Reliability (design failures in the field) electromigration on power supplies hot electron effects on devices wire self heat effects on clocks and signals M.S.Ramaiah School Of Advanced Studies17 18. NoiseAnalog design concerns are due to physical noise sourcesbecause of discreteness of electronic charge andstochastic nature of electronic transport processesexample: thermal noise, flicker noise, shot noiseDigital circuits due to large, abrupt voltage swings, create deterministicnoise which is several orders of magnitude higher than stochastic physicalnoisestill digital circuits are prevalent because they areinherently immune to noiseTechnology scaling and performance demands make noisiness of digitalcircuits a big problem 19. PEMP VSD531Silicon Complexity Challenges Silicon Complexity = impact of process scaling, new materials, new device/interconnect architectures Non-ideal scaling (leakage, power management, circuit/device innovation, current delivery) Coupled high-frequency devices and interconnects (signal integrity analysis and management) Manufacturing variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools) Scaling of global interconnect performance (communication, synchronization) Decreased reliability (soft error uncertainty, gate insulator tunneling and breakdown, joule heating and electromigration) Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost) M.S.Ramaiah School Of Advanced Studies19 20. PEMP VSD531In a PDA Reference Design: personal digital assistant (PDA) Composed of CPU, DSP, peripheral I/O, and memoryM.S.Ramaiah School Of Advanced Studies20 21. PEMP VSD531Implemented With an SoC 0.18um / 400MHz / 470mW (typical)MM Application MP3 PWRCPGProcessor Area JPEG PWM RTC Simple Moving PictureFICP SSP CPU 6.5MTrs.SoundI2CGPIO I-cache D-cache Max 400MHz USB32KB32KB USB OSTSpecification MMCDMA controllerMMC I2SAvailable TimeMEM LCD 6-10HrKEYUART AC97Cnt.Cnt. Data Transfer AreaPeripheral Area SDRAMFlash LCD100MHz 64MB32MB 4 48MHzM.S.Ramaiah School Of Advanced Studies 21 22. PEMP VSD531Design Principles (Traditional) Partition the problem (hirarchical design) Different abstraction levels: RTL, gate-level, switch-level, transistor-level Orthogonize concerns Abstraction vs. implementationLogic vs. timing Constrain the design space to simplify the design processBalance between design complexity and performanceE.g., standard-cell methodology M.S.Ramaiah School Of Advanced Studies22 23. PEMP VSD531Design Principles(State of the Art) Integrate the problem (design closure) Back-annotation, predictability Balance design metrics Area/timing/power/signal integrity/reliability Explore the design space Balance between design complexity and performance Platform-based SoC designM.S.Ramaiah School Of Advanced Studies23 24. PEMP VSD531Design Methodologies (+ business models) Full-Custom (high effort, leading-edge performance, high-volume) Semi-Custom (strong infrastructure, economical in lower volumes) ASIC (Application-Specific Integrated Circuit) Standard Cell/Gate Array/Via Programmable/Structured ASIC FPGA Special Analog (custom layout, I/Os and sense amps) Mixed-Signal / RF (unique to each process, no scaling) System-on-Chip (System-in-Package) Various components: IP blocks, ASIC, FPGA, memory, uP, RF, etc. Define implementation platform, hardware-software co-design Performance vs. complexityM.S.Ramaiah School Of Advanced Studies 24 25. PEMP VSD531 Flow Wire ModelStandard Cell Library Device model r,s, mSchematic Entry 3-D RLCLayers CellModeling Tool Layout rulesCharacterizationLayout Entry Synthesis Library (Timing/Power/Area)Parasitic Extraction Library Place & Route Library (Ports)C-ModelVerilogStructural GlobalSynthesisBlock Layout P & RBehavioralModelLayoutModel VerilogFloorplan FloorplanStructural RTL P&R DRC/ERC/LVS Static/Dynamic Timing w/extract Functional Functional Power/Area Scan/TestabilityStatic TimingClock Routing/Analysis M.S.Ramaiah School Of Advanced Studies 25 26. PEMP VSD531Traditional Taxonomy Behavioral Level DesignIO Pad Placement Front End Logic Design and Power/Ground Simulation Stripes, Rings Routing Logic SynthesisLogic PartitioningDie Planning Global Placement Detail PlacementSimulation Floorplanning Clock Tree Synthesis and RoutingDesign VerificationTiming VerificationExtraction and Delay Calc. TimingGlobal RoutingVerification Test GenerationLVSDRCDetail Routing Back End ERC M.S.Ramaiah School Of Advanced Studies26 27. PEMP VSD531Generic Flow Steps Library preparation Physical design Library data preparationPhysical floorplanning Design data preparationPlace and route Logic designRC extraction Specification to RTLFormal verification RTL simulationPhysical verification Hierarchical floorplanningRelease to manufacturing SynthesisDesign for test Formal verificationEngineering change order Gate level simulation Static timing analysisM.S.Ramaiah School Of Advanced Studies27 28. PEMP VSD531Library and Design Data Models and technology data required to execute the design flow Power, timing: ALF, DCL, OLA, .lib, STAMP Layout: LEF, DEF, GDSII Delays and path timing, parasitics: SDF, GCF, SDC, DSPF, RSPF, SPEF, SPICE Layout rules: Dracula, Calibre deck M.S.Ramaiah School Of Advanced Studies 28 29. PEMP VSD531High-Level Synthesis (BehaviorRTL)SchedulingAssignment of each operation to a time slot corresponding to a clockcycle or time intervalResource allocationSelection of the types of hardware components and the number foreach type to be included in the final implementationModule bindingAssignment of operation to the allocated hardware componentsController synthesisDesign of control style and clocking schemeCompilationof the input specification language to the internal representationParallelism extractionusually via data flow analysis techniquesM.S.Ramaiah School Of Advanced Studies 29 30. PEMP VSD531Architecture Level FloorplanningDefines the basic chip layout architectureDefine the standard cell rows and I/O placement locationsPlace RAMs and other macrosSeparate gate array, memory, analog, RF blocksDefine power distribution structures such as rings and stripesAllow space for clock, major buses, etc.Rules of thumb for cell density are used to initially calculate design sizeM.S.Ramaiah School Of Advanced Studies30 31. PEMP VSD531Logic Synthesis Conversion of RTL to gate-level netlist Targeted to a foundry-specific library Can be performed hierarchically (block by block) Timing-drivenClock informationPrimary input arrival times, primary output required timesInput driving cells, output loadingFalse paths, multi-cycle paths Interconnect delay may be calculated based on a wireload model which uses fanout to estimate delay Clock parameters (insertion delay, skew, jitter, etc.) are assumed to be attainable later in place and routeM.S.Ramaiah School Of Advanced Studies31 32. PEMP VSD531Formal Verification RTL description and gate level netlist are compared to verify functional equivalence, thereby verifying the synthesis results Formal methods Graph isomorphism Binary Decision Diagram (BDD) Emerging technology that supplements the more traditional gate-level simulation approach FV also performed after place-and-route (if gate netlist changes) M.S.Ramaiah School Of Advanced Studies 32 33. PEMP VSD531RTL Simulation RTL code, written in Verilog, VHDL or a combination of both, is simulated to verify functional correctness Testbenches apply input stimulus to the design Several methods are used to verify the outputs Self-checking testbenches automatically verify output correctness and report mismatches Results can be stored in a file and compared to previous results Waveform displays can be used to interactively verify the outputsM.S.Ramaiah School Of Advanced Studies 33 34. PEMP VSD531Gate-Level Simulation Covers both functionality and timing Correctness is only as good as the test vectors used Especially critical for non-synchronous designs, verification of false path and multi-cycle path constraints Cell timing is included in the simulation models and interconnect delay is passed from the synthesis run Worst case PVT conditions are used to analyze for setup violations, and best case PVT conditions are used to analyze for hold violations PVT = Process, Voltage, Temperature M.S.Ramaiah School Of Advanced Studies34 35. PEMP VSD531Static Timing Analysis Verifies that design operates at desired frequencyImplicitly assumes correct timing constraints (!), e.g., boundaryconditions Timing constraints are similar to those used by logic synthesis Verifies setup and hold times at FF inputs; can also check timing from and to PIs and POs; can also check point-to-point delay values (with blocking of pins, etc.) As with gate-level simulation, both best- and worst-case analysis is performed Typically performed on full-chip (not block) basisMay require modified constraints for inter-block issues: multiple clockdomains, multi-cycle paths, etc. For compatibility with timing-driven layout flow, helps to have simple / single set of constraintsOther issues: incremental analysis, M.S.Ramaiah School Of Advanced Studies 35 36. PEMP VSD531Block-Level Physical FloorplanningReconcile logical and physical hierarchiesCells that are interconnected want to be close togetherTake advantage of RTL hierarchyGenerate a physical hierarchyRTL hierarchy = best physical hierarchyOften bundled within the same cockpit as the place and route toolGive placement some initial clues to reduce complexityM.S.Ramaiah School Of Advanced Studies36 37. PEMP VSD531Place and RouteAutomatically place the standard cellsGenerate clock treesAdd any remaining power bus connectionsRoute clock linesRoute signal interconnectsDesign rule checks on the routes and cell placementsTiming driven toolsRequire timing constraints and analysis algorithms similar to those usedduring the static timing analysis stepM.S.Ramaiah School Of Advanced Studies 37 38. PEMP VSD531RC(L) Extraction Calculate resistance and capacitance (and inductance) of interconnects Based on placement of cells Routing segments Calculate capacitive (inductive) effects of adjacent segments Extract capacitance between metal segments RC(L) data transferred back to Static timing analysis (back annotation) Gate level simulation Replaces wire load model used in synthesis Drive delay calculation, signal integrity analysis (crosstalk, other noise), static timing Q: How do parasitics and noise affect performance?M.S.Ramaiah School Of Advanced Studies38 39. PEMP VSD531Physical Verification DRC Design Rule CheckSpacing, min dimension rules LVS Layout Versus SchematicVerifies that layout and netlist are equivalent at the transistor level Electrical Rule Check Dangling nets, floating nodes GDSII (Stream Format)Final merge of layout, routing and placement data for maskproductionM.S.Ramaiah School Of Advanced Studies39 40. PEMP VSD531Release to ManufacturingFinal edits to the layout are madeMetal fill and metal stress relief rules are checkedManufacturing information such as scribe lanes, seal rings, mask shop data,part numbers, logos and pin 1 identification information for assembly arealso addedDRC and LVS are run to verify the correctness of the modified databaseTapeout documentation is prepared prior to release of the GDSII to thefoundryPad location information is prepared, typically in a spreadsheetCadences Virtuoso is used for custom-manual edits of the mask layersManufacturing steps generation of masks silicon processing wafer testing assembly and packaging manufacturing test M.S.Ramaiah School Of Advanced Studies 40 41. PEMP VSD531More Design Metrics and TechniquesCost minimization AreaSynthesis (technology mapping)Cell areaWirelengthPlacement, routing Timing Performance optimizationGateInterconnectLogic transformation, transistor sizing PowerBuffering, re-routingDynamicStaticPower minimizationLeakageGating (sleep transistors), variant Vdd Signal IntegrityProcess optimizationCrosstalk (capacitive, inductive)Dual-VthSupply voltage drop (IR drop,LdI/dt) Signal Integrity ReliabilitySizing, net ordering, shieldingVariation (Vdd, thermal, processvariation (tox, BEOL))P/G design, placement, synthesisElectromigrationReliabilityHot electron effect (SEU) Statistical design optimizationDesign marginM.S.Ramaiah School Of Advanced Studies 41 42. PEMP VSD531Wireload Model Helps delay estimation at synthesis stage Gate delay = f(input slew, load cap)Cap Wire cap = f(fanout number) Empirical2 51015 Different for each technology, library, tool,#Pins design, and design stage Statistical (from library), custom (multiple iterations), structural (look at adjacent15 nets) 10 Large deviation remains% Est Error 5 Routing obstacles (hard IP blocks, macros, 0 etc.) 05 1015-5 Routing algorithms/implementations (timing -10 driven, net ordering, details) DesignM.S.Ramaiah School Of Advanced Studies 42 43. PEMP VSD531Interconnect StatisticsLocal InterconnectSLocal = S TechnologySGlobal = S DieGlobal Interconnect What are some implications? M.S.Ramaiah School Of Advanced Studies 43 44. PEMP VSD531Constructive Interconnect Prediction Statistical models have their limitations Critical paths and the law of small numbersStatistics properties, e.g., average wirelengthExtreme statistics properties, e.g., critical path length Implementation detailsRouting congestion, e.g., horizontal effectTiming optimization, e.g., layer assignmentVia blockage, pin accessability, wrong way routing, etc. Predict by construction (physical synthesis)try a fast (global) router M.S.Ramaiah School Of Advanced Studies44 45. PEMP VSD531Goal: Design Convergence What must converge?logic, timing, power, SI, reliability in a physical embeddingsupport front-end signoff with a predictable back-end Achieve Convergence through Predictabilitycorrect by construction (assume, then enforce)constraints and assumptions passed downstream; not much goesupstreamignores concerns via guardbandingseparates concerns as able (e.g., FE logic/timing vs. BE spatialembedding)construct by correction (tight loops)logic-layout unification; synthesis-analysis unification, concurrentoptimizationelimination of concernsreduced degrees of freedom, pre-emptive design techniquese.g., power distribution, layer assignment / repeater rules M.S.Ramaiah School Of Advanced Studies 45 46. PEMP VSD531Physical Prototyping PhilosophyRTLPrototype delivers accurate physical dataFunctionality known Levels of accuracy GatesPlacement-acknowledgeablesynthesis (PKS)Including global route Physical Prototype Post-detailed-route (In-PlaceTiming / routability knownOptimization, i.e., IPO) Hierarchical timing budgeting:Floorplan / Placement Chip-level CTS, top-level routeand IPO, power analysis and griddesignRoutingBlock-level synthesis, placement,IPO, routing Handoff with enough physical information to ensure correct results M.S.Ramaiah School Of Advanced Studies 46 47. PEMP VSD531Pictures of the Pieces Place Full Chip PowerDetailed Trial Route Timing Planning RC ExtractionClosure Delay Calc / STAIPO Power IR Drop Hierarchical ClockAnalysisFull Chip Tree SynthesisPhysical100psskew 150ps130ps skew skewPrototype50ps skew 50ps120ps skew skew Block-Level Partition Optimization Tape Out Every Day M.S.Ramaiah School Of Advanced Studies47 48. PEMP VSD531 Session SummaryAfter completing this session, students will be able Technology and interconnect evolutions are the major sets for thephysical design New materials with respect to scaling are the key issues for thephysical design ASIC design flow like front end and backend with necessary inputsfrom the foundry are the constraints involved in the process M.S.Ramaiah School Of Advanced Studies48