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![Page 1: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/1.jpg)
1
Hardware synthesis 2.0
Byron Cook and Satnam Singhwith Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis
![Page 2: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/2.jpg)
2
Explosion of advances in program verification
Impossible 10 years ago, standard today SLAM, SpaceInvader, ARMC, Thor, RGSep, TERMINATOR, etc WP synthesis, WLP synthesis,
Challenges in automatic program verification Concurrency Data structures Scalability/precision Productization New applications
![Page 3: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/3.jpg)
3
Beyond proving correctness
Can we use these techniques elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
![Page 4: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/4.jpg)
Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
4
Beyond proving correctness
![Page 5: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/5.jpg)
Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
5
Beyond proving correctness
![Page 6: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/6.jpg)
Can we use these tools elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
6
Beyond proving correctness
![Page 7: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/7.jpg)
Can we use these techniques elsewhere? Compilers ? Operating systems? Language runtimes?
Current focus: hardware synthesis Synthesis for heap-based programs using techniques from
termination provers Automatically parallelize circuits, and localize memories on
chip using techniques from heap analysis Aggressive unrolling of loops during synthesis using
complexity analysis
7
Beyond proving correctness
![Page 8: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/8.jpg)
8
Hardware synthesis
Cfile
HardwareSynthesis
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9
Hardware synthesis
Cfile
HardwareSynthesis
![Page 10: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/10.jpg)
10
Hardware synthesis
Cfile
HardwareSynthesis
![Page 11: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/11.jpg)
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Hardware synthesis
Cfile
HardwareSynthesis
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Hardware synthesis
HardwareSynthesis
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Hardware synthesis
HardwareSynthesis
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Hardware synthesis
HardwareSynthesis
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15
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
HardwareSynthesis
![Page 16: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/16.jpg)
16
Hardware synthesis
Cfile
![Page 17: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/17.jpg)
17
Hardware synthesis
Cfile
ShapeAnalysis α filepass
error
XX
![Page 18: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/18.jpg)
18
Hardware synthesis
Cfile
ShapeAnalysis α filepass
error
XX
![Page 19: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/19.jpg)
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Hardware synthesisXX
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20
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
![Page 21: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/21.jpg)
21
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
![Page 22: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/22.jpg)
22
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
![Page 23: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/23.jpg)
23
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
![Page 24: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/24.jpg)
24
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
![Page 25: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/25.jpg)
25
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
![Page 26: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/26.jpg)
26
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
![Page 27: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/27.jpg)
27
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
pass
![Page 28: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/28.jpg)
28
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
HardwareSynthesis
![Page 29: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/29.jpg)
29
Hardware synthesis
Cfile
ShapeAnalysis α filepass Termination
Analysis
error
pass
XX
error
XX
BoundsSynthesis
XXfailure
HardwareSynthesis
![Page 30: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/30.jpg)
30
Hardware synthesis
pass
error
pass
XX
error
XX
XXfailure
α fileShapeAnalysis
TerminationAnalysis
BoundsSynthesis
HardwareSynthesis
Cfile
![Page 31: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/31.jpg)
31
α file
failure
Hardware synthesis
ShapeAnalysis
pass TerminationAnalysis
error
pass
error
BoundsSynthesis
XX
XX
Cfile
PreconditionSynthesis
XX
![Page 32: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/32.jpg)
32
α file
failure
Hardware synthesis
ShapeAnalysis
pass TerminationAnalysis
error
pass
error
BoundsSynthesis
XX
XX
Cfile
PreconditionSynthesis
XX
![Page 33: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/33.jpg)
Altera DE2 FPGA Board
33
![Page 34: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/34.jpg)
Altera synthesis/implementation tools
34
![Page 35: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/35.jpg)
Synthesized logic
35
![Page 36: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/36.jpg)
VHDL simulation of prio netlist
36
![Page 37: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/37.jpg)
Logic analyzer output
37
![Page 38: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/38.jpg)
38
Conclusion
Big advances in formal verification, analysis, understanding
Alternative uses for these new techniques? Compiling for embedded systems or hardware? Automatic parallelization? Speculative execution and rollback? Mixed static/dynamic property checking in runtimes? Runtime verification of progress (i.e. termination)?
Current project Solving open problems in hardware synthesis Further blurring the line between hardware and software Demo: first-known synthesis tool supporting dynamic heap
![Page 39: 1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint.](https://reader035.fdocuments.net/reader035/viewer/2022070407/56649e115503460f94afcb2f/html5/thumbnails/39.jpg)
39
Conclusion
Big advances in formal verification, analysis, understanding
Alternative uses for these new techniques? Compiling for embedded systems or hardware? Automatic parallelization? Speculative execution and rollback? Mixed static/dynamic property checking in runtimes? Runtime verification of progress (i.e. termination)?
Current project Solving open problems in hardware synthesis Further blurring the line between hardware and software Demo: first-known synthesis tool supporting dynamic heap