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Generalized Buffering of PTL Generalized Buffering of PTL Logic Stages using Boolean Logic Stages using Boolean

Division and Don’t CaresDivision and Don’t Cares

Rajesh GargRajesh Garg

Sunil P. KhatriSunil P. KhatriDepartment of Electrical and Computer Engineering,Department of Electrical and Computer Engineering,

Texas A&M University,Texas A&M University,

College Station, TX 77843College Station, TX 77843

22

OutlineOutlineIntroductionIntroductionObjectiveObjectivePrevious WorkPrevious WorkCODCs and ACODCsCODCs and ACODCsGeneralized Buffering With CODCsGeneralized Buffering With CODCsResultsResultsConclusionsConclusions

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IntroductionIntroduction Pass Transistor Logic (PTL) typically used for specific Pass Transistor Logic (PTL) typically used for specific

circuit implementations, like barrel shifterscircuit implementations, like barrel shifters No widely accepted PTL design methodologyNo widely accepted PTL design methodology There exists a direct mapping between an ROBDD node There exists a direct mapping between an ROBDD node

and a PTL muxand a PTL mux

v

f

fv fv’

f

fv fv’

v01

v v’

f

fv fv’

ROBDD Node MUX PTL based MUX

Hence ROBDDs can be used to perform PTL based Hence ROBDDs can be used to perform PTL based synthesis for general circuitssynthesis for general circuits

44

Problems with direct mappingProblems with direct mapping Body EffectBody Effect

Cannot connect more than 4-5 devices in seriesCannot connect more than 4-5 devices in series Monolithic ROBDDsMonolithic ROBDDs

Worst-case exponential size in number of the inputs (large)Worst-case exponential size in number of the inputs (large)Memory explosion can occur during ROBDD constructionMemory explosion can occur during ROBDD construction

Introduction (contd)Introduction (contd)

Partitioned ROBDDsPartitioned ROBDDs Avoids memory explosion of monolithic ROBDDsAvoids memory explosion of monolithic ROBDDs Output of each PTL structure needs to be bufferedOutput of each PTL structure needs to be buffered Regenerate electrical drive capability after 4 or 5 levels Regenerate electrical drive capability after 4 or 5 levels

using a pair of inverters (avoid body effect problems)using a pair of inverters (avoid body effect problems)

55

ObjectiveObjective New PTL Synthesis ApproachNew PTL Synthesis Approach

Use partitioned ROBDDsUse partitioned ROBDDsAvoid memory explosionAvoid memory explosionGuarantee no more than 4-5 series devicesGuarantee no more than 4-5 series devices

Use generalized buffering Use generalized buffering Buffers can be complex logic gates in general (not simple Buffers can be complex logic gates in general (not simple

inverters/ buffers)inverters/ buffers)Use ACODCs or CODCs to improve the extraction of Use ACODCs or CODCs to improve the extraction of

generalized buffersgeneralized buffersSimplifies the logic function of the PTL blockSimplifies the logic function of the PTL block

Boolean Division based formulationBoolean Division based formulationElegant, powerful formulation to extract generalized buffersElegant, powerful formulation to extract generalized buffersAugmented with CODC / ACODCsAugmented with CODC / ACODCs

Reduces total circuit delay and areaReduces total circuit delay and area

66

Previous WorkPrevious Work Buch et. al, “Logic synthesis for large pass transistor circuits”, Buch et. al, “Logic synthesis for large pass transistor circuits”,

in Proceedings, in Proceedings, IEEE/ACM ICCADIEEE/ACM ICCAD, Nov 1997, pp 663-670, Nov 1997, pp 663-670

Lai et. al, “BDD decomposition for mixed CMOS/PTL logic Lai et. al, “BDD decomposition for mixed CMOS/PTL logic circuit synthesis”, in Proceedings, circuit synthesis”, in Proceedings, IEEE ISCASIEEE ISCAS, May 2005, pp. , May 2005, pp. 5649-56525649-5652

Yamashita et. al, “Pass-transistor/CMOS collaborated logic: Yamashita et. al, “Pass-transistor/CMOS collaborated logic: The best of both worlds”, in Digest of Technical Papers, The best of both worlds”, in Digest of Technical Papers, Symposium on VLSI CircuitsSymposium on VLSI Circuits, June 1997, pp. 31-32, June 1997, pp. 31-32..

Garg et. al, “Generalized buffering of PTL logic stages using Garg et. al, “Generalized buffering of PTL logic stages using Boolean division”, in Proceedings, Boolean division”, in Proceedings, IEEE ISCASIEEE ISCAS, May 2006., May 2006.

77

CODCsCODCs

Observability Don’t Cares (ODCs)

ODCs used to minimize the logic function of a node Need to re-compute the ODCs of the other nodes

after optimization

Compatible Observability Don’t Cares Can simultaneously change the function of all nodes Subset of ODCs full_simplify is used to compute CODCs in SIS ROBDD based computation to compute CODCs

}|)(|)(..{ 10 jj ykyk

njk xzxztsBxODC

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CODCs (contd.)CODCs (contd.)

Memory intensive Memory intensive Computation is possible only for small and medium Computation is possible only for small and medium

sized circuitssized circuits Approximate CODCs by Saluja et. alApproximate CODCs by Saluja et. al

30X faster than full CODCs30X faster than full CODCs Requires 30X less memory than full CODCsRequires 30X less memory than full CODCs Literal count reduction is about 80% of that obtained by Literal count reduction is about 80% of that obtained by

full CODCsfull CODCs Can compute ACODCs for arbitrarily large circuitsCan compute ACODCs for arbitrarily large circuits

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PTL with Generalized Buffering PTL with Generalized Buffering

Primary Inputs

Primary Output Primary Output

Primary Inputs

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Boolean DivisionBoolean Division

Definition 1: g is a Boolean divisor of f if h and r exist such that

f = gh + r

where, gh ≠ Ø

Definition 2: g is a Boolean factor of f if, g is a Boolean divisor of f, and in addition,

r = Ø , i.e. f = ghTheorem: If fg ≠ Ø, then g is a Boolean divisor of f.

1111

ROBDD DivisionROBDD Division Consider a (partitioned) ROBDD Consider a (partitioned) ROBDD ff of a node of a node n n in the networkin the network Let d represent the CODCs of node n Consider a library gate Consider a library gate g g ≡ ≡ G G Division of Division of f f by by gg can be represented by following equations: can be represented by following equations:

// Upper bound of f// Upper bound of f

//Lower bound of f//Lower bound of f

Therefore, quotient Therefore, quotient remainder remainder Finally,Finally,

gffGL

gfgdfGU

gfxdfGf

gffgf

)(

)( gxwhere

gdfhf gfr

rGhf

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Generalized Buffering with CODCsGeneralized Buffering with CODCs

Synthesize partitioned PTL blocks withSynthesize partitioned PTL blocks with Maximum depth of 5Maximum depth of 5 No more than 5 transistors in seriesNo more than 5 transistors in series

Optimize and decompose networkOptimize and decompose network Using only 2-input gates and invertersUsing only 2-input gates and inverters PTL structure will grow in predictable mannerPTL structure will grow in predictable manner Initially any ROBBD can have maximum 8 variablesInitially any ROBBD can have maximum 8 variables If division fails, we can make one of the fanins a If division fails, we can make one of the fanins a

ROBDD variable -- ROBDD variable -- back-trackback-track

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Algorithm: Generalized Buffering with CODCsAlgorithm: Generalized Buffering with CODCsAA = dfs_and_levelize_nodes( = dfs_and_levelize_nodes(ηη**))ii =1 =1whilewhile ii ≤ size( ≤ size(AA) ) dodo

nn = array_fetch( = array_fetch(A,iA,i))f f = ntbdd_node_to_bdd(= ntbdd_node_to_bdd(nn) ) //creates ROBDD of node n//creates ROBDD of node nifif bdd_depth( bdd_depth(ff) ≥ 5 ) ≥ 5 thenthen

forfor gg ≡ ≡ GG Gate Library Gate Library dodod = compute_dc(n)ff = test_division( = test_division(f,g,d,Gf,g,d,G))end forend forifif bdd_depth( bdd_depth(ff) > 5 ) > 5 then then back-trackback-trackelseelsebdd_create_variable(bdd_create_variable(nn) ) continuecontinueend ifend if

elseelsecontinuecontinue

end ifend ifend whileend while

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test_division with CODCstest_division with CODCstest_division(f,d,g,G) {

if fg ≠ 0 then

Z = bdd_between(L,U)

Z* = bdd_smooth(Z,gvars)

R = bdd_compose(Z*,G,g)

if f R f + d && bdd_depth(Z*) < bdd_depth(f) then

return(success, Z*)

end if

else

return fail

end if

}

))((

))((

GggffGL

GggdgfdGfGU

Qd

GgdQ

V )(

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back-trackback-track

d

a

c

n-2 n-2

n-1

nnNeeds

back-track

Make ‘c’ a variable

Re-process bb

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Experimental SetupExperimental Setup

Implemented in SISImplemented in SIS Process Technology- 100nm BPTMProcess Technology- 100nm BPTM Gate LibraryGate Library

AND2, AND3, AND4 AND2, AND3, AND4 OR2, OR3, OR4OR2, OR3, OR4

A set of benchmark circuits were synthesizedA set of benchmark circuits were synthesized Compared with traditional method Compared with traditional method

Inverters for bufferingInverters for buffering Similar to method reported by Buch. et. alSimilar to method reported by Buch. et. al

Also compared with generalized buffering without don’t Also compared with generalized buffering without don’t cares cares

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Gate Delay and AreaGate Delay and Area

Gate Delay (ps) Area (2)

MUX 18 0.08

INV 10.26 0.08

Buffer 20.5 0.16

AND2 30.20 0.28

AND3 37.76 0.44

AND4 47.39 0.64

OR2 38.70 0.36

OR3 46.08 0.68

OR4 68.28 1.12

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DelayDelay

Ckt Traditional

Buffering (ps)

Generalized Buffering (ps)

Without CODCs With ACODCs With CODCs

alu2 1927.26 0.53 0.55 0.54

alu4 3458.88 0.45 0.43 -

apex6 819.72 0.73 0.75 0.75

C432 2302.38 0.86 0.79 0.76

C880 1248.8 0.70 0.53 0.54

C1908 1336.14 0.74 0.67 0.68

C3540 2104.56 0.71 0.53 -

i8 940.68 0.69 0.62 0.60

C6288 5971.5 0.94 0.86 -

… … … … …

AVG 0.756 0.710 -

1919

AreaArea

Ckt Traditional

Buffering (2)

Generalized Buffering (2)

Without CODCs With ACODCs With CODCs

alu2 164.32 0.87 0.86 0.83

alu4 963.68 1.12 1.12 -

apex6 305.52 0.95 0.93 0.93

C432 87.12 1.02 0.93 1.10

C880 136.16 0.80 0.79 0.79

C1908 152.24 0.97 0.93 0.93

C3540 532.88 1.01 0.98 -

i8 520.48 0.75 0.72 0.70

C6288 1220.48 1.10 1.06 -

… … … … …

AVG 0.970 0.950 -

2020

MultiplexersMultiplexers

Ckt Traditional

Buffering

Generalized BufferingGeneralized Buffering

Without CODCs With ACODCs With CODCs

alu2 718 0.60 0.577 0.532

alu4 4188 0.704 0.689 -

apex6 1337 0.737 0.719 0.718

C432 404 0.995 0.795 0.834

C880 594 0.731 0.702 0.712

C1908 660 0.858 0.806 0.792

C3540 2362 0.732 0672 -

i8 2418 0.483 0.449 0.439

C6288 5393 0.917 0.834 -

… … … … …

AVG 0.770 0.729 -

2121

Run-timeRun-time

Ckt Generalized Buffering (s)

Without CODCs With ACODCs With CODCs

alu2 0.38 11.48 435.32

alu4 8.99 54.52 -

apex6 1.49 4.6 117.23

C432 0.46 13.82 236.82

C880 0.24 2.41 70.0

C1908 0.790 8.08 362.12

C3540 5.01 41.56 -

i8 1.63 28.73 2651.48

C6288 10.79 151.49 -

… … … …

AVG 4.837 33.55 -

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ConclusionsConclusions

Generalized buffering with ACODCs results in delay Generalized buffering with ACODCs results in delay reduction byreduction by 29% over traditional buffering29% over traditional buffering 5% over generalized buffering without don’t cares5% over generalized buffering without don’t cares

Area reduction obtained by generalized buffering with Area reduction obtained by generalized buffering with ACODCs is ACODCs is 5% compared to traditional buffering5% compared to traditional buffering 2% compared to generalized buffering without don’t cares2% compared to generalized buffering without don’t cares

Multiplexers also reduced by Multiplexers also reduced by 27% compared to traditional buffering27% compared to traditional buffering 4% compared to generalized buffering without don’t cares4% compared to generalized buffering without don’t cares

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Conclusions (contd)Conclusions (contd)

A large number of divisions were obtained for each A large number of divisions were obtained for each circuitcircuit

Little advantage of using CODCs over ACODCsLittle advantage of using CODCs over ACODCs Delay reduction is less than 1% Delay reduction is less than 1% Area increases by 1%Area increases by 1% Run-time is 76X slowerRun-time is 76X slower

Can synthesize arbitrary sized circuits using partitioned Can synthesize arbitrary sized circuits using partitioned ROBDDs and ACODC based divisionROBDDs and ACODC based division

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Thank You!!Thank You!!

Questions?Questions?