1. General description - NXP Semiconductors · 2020. 9. 3. · 1. General description The PCA9634...

1. General description

The PCA9634 is an I2C-bus controlled 8-bit LED driver optimized for Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) Group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its Individual PWM controller value or at both Individual and Group PWM controller values. The LED output driver is programmed to be either open-drain with a 25 mA current sink capability at 5 V or totem-pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9634 operates with a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external drivers and a minimum amount of discrete components for larger current or higher voltage LEDs.

The PCA9634 is one of the first LED controller devices in a new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF).

The active LOW Output Enable input pin (OE) allows asynchronous control of the LED outputs and can be used to set all the outputs to a defined I2C-bus programmable logic state. The OE can also be used to externally PWM the outputs, which is useful when multiple devices need to be dimmed or blinked together using software control.

Software programmable LED Group and three Sub Call I2C-bus addresses allow all or defined groups of PCA9634 devices to respond to a common I2C-bus address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands. Seven hardware address pins allow up to 126 devices on the same bus.

The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9634 through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the outputs to be set HIGH (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.

PCA96348-bit Fm+ I2C-bus LED driverRev. 7.1 — 18 December 2017 Product data sheet

NXP Semiconductors PCA96348-bit Fm+ I2C-bus LED driver

2. Features and benefits

8 LED drivers. Each output programmable at:

Off

On

Programmable LED brightness

Programmable group dimming/blinking mixed with individual LED brightness

1 MHz Fast-mode Plus compatible I2C-bus interface with 30 mA high drive capability on SDA output for driving high capacitive buses

256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 97 kHz PWM signal

256-step group brightness control allows general dimming (using a 190 Hz PWM signal) from fully off to maximum brightness (default)

256-step group blinking with frequency programmable from 24 Hz to 10.73 s and duty cycle from 0 % to 99.6 %

Eight totem-pole outputs (sink 25 mA and source 10 mA at 5 V) with software programmable open-drain LED outputs selection (default at totem-pole). No input function.

Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).

Active LOW Output Enable (OE) input pin. LED outputs programmable to 1 (default at power-up), 0 or ‘high-impedance’ when OE is HIGH, thus allowing hardware blinking and dimming of the LEDs.

7 hardware address pins allow 126 devices to be connected to the same I2C-bus

4 software programmable I2C-bus addresses (one LED Group Call address and three LED Sub Call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for ‘All Call’ so that all the PCA9634s on the I2C-bus can be addressed at the same time and the second register used for three different addresses so that 13 of all devices on the bus can be addressed at the same time in a group). Software enable and disable for I2C-bus address.

Software Reset feature (SWRST Call) allows the device to be reset through the I2C-bus

25 MHz internal oscillator requires no external components

Internal power-on reset

Noise filter on SDA/SCL inputs

Edge rate control on outputs

No glitch on power-up

Supports hot insertion

Low standby current

Operating power supply voltage range of 2.3 V to 5.5 V

5.5 V tolerant inputs

40 C to +85 C operation

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO20, TSSOP20, HVQFN20

PCA9634 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.

Product data sheet Rev. 7.1 — 18 December 2017 2 of 39


3. Applications

RGB or RGBA LED drivers

LED status information

LED displays

LCD backlights

Keypad backlights for cellular phones or handheld devices

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Topside mark

Package

Name Description Version

PCA9634D PCA9634D SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

PCA9634PW PCA9634 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

PCA9634BS 9634 HVQFN20 plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 5 0.85 mm

SOT662-1

Table 2. Ordering options

Type number Orderable part number

Package Packing method Minimum order quantity

Temperature range

PCA9634D PCA9634D,118 SO20 Reel 13” Q1/T1 *Standard mark SMD

2000 Tamb = 40 C to +85 C

PCA9634PW PCA9634PW,118 TSSOP20 Reel 13” Q1/T1 *Standard mark SMD

2500 Tamb = 40 C to +85 C

PCA9634BS PCA9634BS,118 HVQFN20 Reel 13” Q1/T1 *Standard mark SMD

6000 Tamb = 40 C to +85 C




5. Block diagram

Remark: Only one LED output shown for clarity.

Fig 1. Block diagram of PCA9634

A0 A1 A2 A3 A4 A5 A6

002aac135

I2C-BUSCONTROL

INPUT FILTER

PCA9634

POWER-ONRESET

SCL

SDA

VDD

VSSLED

STATESELECT

REGISTER

PWMREGISTER XBRIGHTNESS

CONTROL

GRPFREQREGISTER

GRPPWMREGISTER

MUX/CONTROL

OE

'0' – permanently OFF'1' – permanently ON

VDD

LEDn

190 Hz

24.3 kHz97 kHz

25 MHzOSCILLATOR




6. Pinning information

6.1 Pinning

Fig 2. Pin configuration for SO20 Fig 3. Pin configuration for TSSOP20

Fig 4. Pin configuration for HVQFN20

PCA9634D

A0 VDD

A1 SDA

A2 SCL

A3 A6

A4 A5

LED0 OE

LED1 LED7

LED2 LED6

LED3 LED5

VSS LED4

002aac131

1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

VDD

SDA

SCL

A6

A5

OE

LED7

LED6

LED5

LED4

A0

A1

A2

A3

A4

LED0

LED1

LED2

LED3

VSS

PCA9634PW

002aac132

1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

002aac133

PCA9634BS

Transparent top view

LED6

LED0

LED1

LED7

A4

A3 A5

A2 A6

LED

2

LED

3

VS

S

LED

4

LED

5

A1

A0

VD

D

SD

A

SC

L

5 11

4 12

3 13

2 14

1 15

6 7 8 9 10

20 19 18 17 16

terminal 1index area

OE




6.2 Pin description

[1] HVQFN20 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.

Table 3. Pin description

Symbol Pin Type Description

SO20, TSSOP20 HVQFN20

A0 1 19 I address input 0





LED0 6 4 O LED driver 0




VSS 10 8[1] power supply supply ground





OE 15 13 I active LOW output enable



SCL 18 16 I serial clock line

SDA 19 17 I/O serial data line

VDD 20 18 power supply supply voltage




7. Functional description

Refer to Figure 1 “Block diagram of PCA9634”.

7.1 Device addresses

Following a START condition, the bus master must output the address of the slave it is accessing.

There are a maximum of 128 possible programmable addresses using the 7 hardware address pins. Two of these addresses, Software Reset and LED All Call, cannot be used because their default power-up state is ON, leaving a maximum of 126 addresses. Using other reserved addresses, as well as any other Sub Call address, will reduce the total number of possible addresses even further.

7.1.1 Regular I2C-bus slave address

The I2C-bus slave address of the PCA9634 is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.

Remark: Using reserved I2C-bus addresses will interfere with other devices, but only if the devices are on the bus and/or the bus will be open to other I2C-bus systems at some later date. In a closed system where the designer controls the address assignment these addresses can be used since the PCA9634 treats them like any other address. The LED All Call, Software Rest and PCA9564 or PCA9665 slave address (if on the bus) can never be used for individual device addresses.

• PCA9634 LED All Call address (1110 000) and Software Reset (0000 0110) which are active on start-up

• PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on start-up

• ‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)

• slave devices that use the 10-bit addressing scheme (1111 0XX)

• slave devices that are designed to respond to the General Call address (0000 000)

• High-speed mode (Hs-mode) master code (0000 1XX).

The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation.

Fig 5. Slave address

R/W

002aab319

A6 A5 A4 A3 A2 A1 A0

hardware selectable

slave address




7.1.2 LED All Call I2C-bus address

• Default power-up value (ALLCALLADR register): E0h or 1110 000X

• Programmable through I2C-bus (volatile programming)

• At power-up, LED All Call I2C-bus address is enabled. PCA9634 sends an ACK when E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.

See Section 7.3.8 “ALLCALLADR: LED All Call I2C-bus address” for more detail.

Remark: The default LED All Call I2C-bus address (E0h or 1110 000X) must not be used as a regular I2C-bus slave address since this address is enabled at power-up. All the PCA9634s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.

7.1.3 LED Sub Call I2C-bus addresses

• 3 different I2C-bus addresses can be used

• Default power-up values:

– SUBADR1 register: E2h or 1110 001X



• Programmable through I2C-bus (volatile programming)

• At power-up, Sub Call I2C-bus addresses are disabled. PCA9634 does not send an ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.

See Section 7.3.7 “SUBADR1 to SUBADR3: I2C-bus subaddress 1 to 3” for more detail.

Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus slave addresses as long as they are disabled.

7.1.4 Software Reset I2C-bus address

The address shown in Figure 6 is used when a reset of the PCA9634 needs to be performed by the master. The Software Reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the PCA9634 does not acknowledge the SWRST. See Section 7.6 “Software Reset” for more detail.

Remark: The Software Reset I2C-bus address is a reserved address and cannot be used as a regular I2C-bus slave address or as an LED All Call or LED Sub Call address.

Fig 6. Software Reset address

0

002aab416

0 0 0 0 0 1 1

R/W




7.2 Control register

Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCA9634, which will be stored in the Control register.

The lowest 5 bits are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options (AI[2:0]).

When the Auto-Increment flag is set (AI2 = 1), the five low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values.

Remark: Other combinations not shown in Table 4 (AI[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation.

AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C-bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I2C-bus communication, for example, changing color setting to another color setting.

reset state = 80h

Remark: The Control register does not apply to the Software Reset I2C-bus address.

Fig 7. Control register

Table 4. Auto-Increment options

AI2 AI1 AI0 Function

0 0 0 no Auto-Increment

1 0 0 Auto-Increment for all registers. D[4:0] roll over to ‘0 0000’ after the last register (1 0001) is accessed.

1 0 1 Auto-Increment for individual brightness registers only. D[4:0] roll over to ‘0 0010’ after the last register (0 1001) is accessed.

1 1 0 Auto-Increment for global control registers only. D[4:0] roll over to ‘0 1010’ after the last register (0 1011) is accessed.

1 1 1 Auto-Increment for individual and global control registers only. D[4:0] roll over to ‘0 0010’ after the last register (0 1011) is accessed.

002aac140

AI2 AI1 AI0 D4 D3 D2 D1 D0

Auto-Increment flag

register address

Auto-Increment options




AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I2C-bus communication, for example, global brightness or blinking change.

AI[2:0] = 111 is used when individual and global changes must be performed during the same I2C-bus communication, for example, changing a color and global brightness at the same time.

Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[4:0] is the first register that will be addressed (read or write operation), and can be anywhere between 0 0000 and 1 0001 (as defined in Table 5). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the register increment stops and goes to the next one is determined by AI[2:0]. See Table 4 for rollover values. For example, if the Control register = 1110 1100 (ECh), then the register addressing sequence will be (in hex): 0C … 11 00 … 0B 02 … 0B 02 … 0B 02 … as long as the master keeps sending or reading data.

7.3 Register definitions

Table 5. Register summaryOnly D[4:0] = 0 0000 to 1 0001 are allowed and will be acknowledged.D[4:0] = 1 0010 to 1 1111 are reserved and will not be acknowledged.

Register number (hex) D4 D3 D2 D1 D0 Name Type Function

00 0 0 0 0 0 MODE1 read/write Mode register 1

01 0 0 0 0 1 MODE2 read/write Mode register 2

02 0 0 0 1 0 PWM0 read/write brightness control LED0








0A 0 1 0 1 0 GRPPWM read/write group duty cycle control

0B 0 1 0 1 1 GRPFREQ read/write group frequency

0C 0 1 1 0 0 LEDOUT0 read/write LED output state 0

0D 0 1 1 0 1 LEDOUT1 read/write LED output state 1

0E 0 1 1 1 0 SUBADR1 read/write I2C-bus subaddress 1

0F 0 1 1 1 1 SUBADR2 read/write I2C-bus subaddress 2

10 1 0 0 0 0 SUBADR3 read/write I2C-bus subaddress 3

11 1 0 0 0 1 ALLCALLADR read/write LED All Call I2C-bus address




7.3.1 Mode register 1, MODE1

[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.

[2] When the oscillator is off (Sleep mode) the LED outputs cannot be turned on, off or dimmed/blinked.

7.3.2 Mode register 2, MODE2

Table 6. MODE1 - Mode register 1 (address 00h) bit descriptionLegend: * default value.

Bit Symbol Access Value Description

7 AI2 read only 0 register Auto-Increment disabled

1* register Auto-Increment enabled

6 AI1 read only 0* Auto-Increment bit 1 = 0

1 Auto-Increment bit 1 = 1

5 AI0 read only 0* Auto-Increment bit 0 = 0

1 Auto-Increment bit 0 = 1

4 SLEEP R/W 0 Normal mode[1]

1* Low power mode; oscillator off[2]

3 SUB1 R/W 0* PCA9634 does not respond to I2C-bus subaddress 1

1 PCA9634 responds to I2C-bus subaddress 1





0 ALLCALL R/W 0 PCA9634 does not respond to LED All Call I2C-bus address

1* PCA9634 responds to LED All Call I2C-bus address

Table 7. MODE2 - Mode register 2 (address 01h) bit descriptionLegend: * default value.


7 - read only 0* reserved

6 - read only 0* reserved

5 DMBLNK R/W 0* Group control = dimming

1 Group control = blinking

4 INVRT[1] R/W 0* output logic state not inverted; value to use when no external driver used; applicable when OE = 0

1 output logic state inverted; value to use when external driver used; applicable when OE = 0

3 OCH R/W 0* outputs change on STOP command[2]

1 outputs change on ACK

2 OUTDRV[1] R/W 0 the 8 LED outputs are configured with an open-drain structure

1* the 8 LED outputs are configured with a totem-pole structure




[1] See Section 7.7 “Using the PCA9634 with and without external drivers” for more details. Normal LEDs can be driven directly in either mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI and protect the LEDs, and these must be driven only in the open-drain mode to prevent overheating the IC.

[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9634. Applicable to registers from 02h (PWM0) to 0Dh (LEDOUT) only.

[3] See Section 7.4 “Active LOW output enable input” for more details.

7.3.3 PWM0 to PWM7: Individual brightness control

A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).

(1)

1 to 0 OUTNE[1:0][3] R/W 00 when OE = 1 (output drivers not enabled), LEDn = 0

01* when OE = 1 (output drivers not enabled):

LEDn = 1 when OUTDRV = 1

LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)

10 when OE = 1 (output drivers not enabled), LEDn = high-impedance

11 reserved

Table 7. MODE2 - Mode register 2 (address 01h) bit description …continuedLegend: * default value.


Table 8. PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit descriptionLegend: * default value.

Address Register Bit Symbol Access Value Description

02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle








duty cycle IDC 7:0 256

------------------------=




7.3.4 GRPPWM: Group duty cycle control

When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 8 outputs is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

(2)

7.3.5 GRPFREQ: Group frequency

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).

(3)

Table 9. GRPPWM - Group duty cycle control register (address 0Ah) bit descriptionLegend: * default value.


0Ah GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register

duty cycle GDC 7:0 256

--------------------------=

Table 10. GRPFREQ - Group Frequency register (address 0Bh) bit descriptionLegend: * default value.


0Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register

global blinking periodGFRQ 7:0 1+

24---------------------------------------- in ondssec =




7.3.6 LEDOUT0 and LEDOUT1: LED driver output state

LDRx = 00 — LED driver x is off (default power-up state).

LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled).

LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register.

LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.

7.3.7 SUBADR1 to SUBADR3: I2C-bus subaddress 1 to 3

Subaddresses are programmable through the I2C-bus. Default power-up values are E2h, E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0).

Once subaddresses have been programmed to their right values, SUBx bits need to be set to 1 in order to have the device acknowledging these addresses (MODE1 register).

Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx register is a read-only bit (0).

When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either an I2C-bus read or write sequence.

Table 11. LEDOUT0 and LEDOUT1- LED driver output state registers (address 0Ch and 0Dh) bit description

Legend: * default value.


0Ch LEDOUT0 7:6 LDR3 R/W 00* LED3 output state control

5:4 LDR2 R/W 00* LED2 output state control



0Dh LEDOUT1 7:6 LDR7 R/W 00* LED7 output state control




Table 12. SUBADR1 to SUBADR3 - I2C-bus subaddress registers 1 to 3 (address 0Eh to 10h) bit description



0Eh SUBADR1 7:1 A1[7:1] R/W 1110 001* I2C-bus subaddress 1

0 A1[0] R only 0* reserved

0Fh SUBADR2 7:1 A2[7:1] R/W 1110 010* I2C-bus subaddress 2


10h SUBADR3 7:1 A3[7:1] R/W 1110 100* I2C-bus subaddress 3





7.3.8 ALLCALLADR: LED All Call I2C-bus address

The LED All Call I2C-bus address allows all the PCA9634s on the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default state)). This address is programmable through the I2C-bus and can be used during either an I2C-bus read or write sequence. The register address can also be programmed as a Sub Call.

Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.

7.4 Active LOW output enable input

The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at the same time.

• When a LOW level is applied to OE pin, all the LED outputs are enabled and follow the output state defined in the LEDOUT register with the polarity defined by INVRT bit (MODE2 register).

• When a HIGH level is applied to OE pin, all the LED outputs are programmed to the value that is defined by OUTNE[1:0] in the MODE2 register.

The OE pin can be used as a synchronization signal to switch on/off several PCA9634 devices at the same time. This requires an external clock reference that provides blinking period and the duty cycle.

The OE pin can also be used as an external dimming control signal. The frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the LEDs.

Remark: Do not use OE as an external blinking control signal when internal global blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined blinking pattern. Do not use OE as an external dimming control signal when internal global dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined dimming pattern.

Table 13. ALLCALLADR - LED All Call I2C-bus address register (address 11h) bit description



11h ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2C-bus address register

0 AC[0] R only 0* reserved

Table 14. LED outputs when OE = 1

OUTNE1 OUTNE0 LED outputs

0 0 0

0 1 1 if OUTDRV = 1, high-impedance if OUTDRV = 0

1 0 high-impedance

1 1 reserved




7.5 Power-on reset

When power is applied to VDD, an internal power-on reset holds the PCA9634 in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9634 registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device.

7.6 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus.

The SWRST Call function is defined as the following:

1. A START command is sent by the I2C-bus master.

2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is sent by the I2C-bus master.

3. The PCA9634 device(s) acknowledge(s) after seeing the SWRST Call address ‘0000 0110’ (06h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to the I2C-bus master.

4. Once the SWRST Call address has been sent and acknowledged, the master sends 2 bytes with 2 specific values (SWRST data byte 1 and byte 2):

a. Byte 1 = A5h: the PCA9634 acknowledges this value only. If byte 1 is not equal to A5h, the PCA9634 does not acknowledge it.

b. Byte 2 = 5Ah: the PCA9634 acknowledges this value only. If byte 2 is not equal to 5Ah, then the PCA9634 does not acknowledge it.

If more than 2 bytes of data are sent, the PCA9634 does not acknowledge any more.

5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a STOP command to end the SWRST Call: the PCA9634 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (tBUF).

The I2C-bus master must interpret a non-acknowledge from the PCA9634 (at any time) as a ‘SWRST Call Abort’. The PCA9634 does not initiate a reset of its registers. This happens only when the format of the SWRST Call sequence is not correct.




7.7 Using the PCA9634 with and without external drivers

The PCA9634 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.

If the device needs to drive LEDs to a higher voltage and/or higher current, use of an external driver is required.

• INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the same (PWMx and GRPPWM values directly calculated from their respective formulas and the LED output state determined by LEDOUT register value) independently of the type of external driver. This bit allows LED output polarity inversion/non-inversion only when OE = 0.

• OUTDRV bit (MODE2 register) allows minimizing the amount of external components required to control the external driver (N-type or P-type device).

[1] Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).

[2] Optimum configuration when external P-type (PNP, PMOS) driver used.

[3] Optimum configuration when external N-type (NPN, NMOS) driver used.

Table 15. Use of INVRT and OUTDRV based on connection to the LEDn outputs when OE = 0When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).

INVRT OUTDRV Direct connection to LEDn External N-type driver External P-type driver

Firmware External pull-up resistor



0 0 formulas and LED output state values apply[1]

LED current limiting R[1]

formulas and LED output state values inverted

required formulas and LED output state values apply

required

0 1 formulas and LED output state values apply[1]

LED current limiting R[1]


not required formulas and LED output state values apply[2]

not required[2]

1 0 formulas and LED output state values inverted

LED current limiting R

formulas and LED output state values apply

required formulas and LED output state values inverted

required

1 1 formulas and LED output state values inverted

LED current limiting R

formulas and LED output state values apply[3]

not required[3]


not required




[1] External pull-up or LED current limiting resistor connects LEDn to VDD.

Table 16. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when OE = 0When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).

LEDOUT INVRT OUTDRV Upper transistor (VDD to LEDn)

Lower transistor (LEDn to VSS)

LEDn state

00

LED driver off

0 0 off off high-Z[1]

0 1 on off VDD

1 0 off on VSS

1 1 off on VSS

01

LED driver on

0 0 off on VSS

0 1 off on VSS

1 0 off off high-Z[1]

1 1 on off VDD

10

Individual brightness control

0 0 off Individual PWM (non-inverted)

VSS or high-Z[1] = PWMx value

0 1 Individual PWM (non-inverted)

Individual PWM (non-inverted)

VSS or VDD = PWMx value

1 0 off Individual PWM (inverted)

high-Z[1] or VSS = 1 PWMx value

1 1 Individual PWM (inverted)

Individual PWM (inverted)

VDD or VSS = 1 PWMx value

11

Individual + Group dimming/blinking

0 0 off Individual + Group PWM (non-inverted)

VSS or high-Z[1] = PWMx or GRPPWM values

0 1 Individual PWM (non-inverted)

Individual PWM (non-inverted)

VSS or VDD = PWMx or GRPPWM values

1 0 off Individual + Group PWM (inverted)

high-Z[1] or VSS = (1 PWMx) or (1 GRPPWM) values

1 1 Individual PWM (inverted)

Individual PWM (inverted)

VDD or VSS = (1 PWMx) or (1 GRPPWM) values




7.8 Individual brightness control with group dimming/blinking

A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs):

• A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control.

• A programmable frequency signal from 24 Hz to 110.73 Hz (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control.

Minimum pulse width for LEDn Brightness Control is 40 ns.

Minimum pulse width for Group Dimming is 20.48 s.

When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses of the LED Brightness Control signal (pulse width = N 40 ns, with ‘N’ defined in PWMx register).

This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).

Fig 8. Brightness + Group Dimming signals

1 2 3 4 5 6 7 8 9 10 11 12 507508

509510

511512

1 2 3 4 5 6 7 8 9 10 11

Brightness Control signal (LEDn)

M × 256 × 2 × 40 nswith M = (0 to 255)

(GRPPWM Register)

N × 40 nswith N = (0 to 255)(PWMx Register)

256 × 40 ns = 10.24 μs(97.6 kHz)

1 2 3 4 5 6 7 81 2 3 4 5 6 7 8

Group Dimming signal

resulting Brightness + Group Dimming signal

256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)

002aab417




8. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9).

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10).

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 11).

Fig 9. Bit transfer

mba607

data linestable;

data valid

changeof dataallowed

SDA

SCL

Fig 10. Definition of START and STOP conditions

mba608

SDA

SCLP

STOP condition

S

START condition




8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

Fig 11. System configuration

002aaa966

MASTERTRANSMITTER/

RECEIVER

SLAVERECEIVER

SLAVETRANSMITTER/

RECEIVER

MASTERTRANSMITTER

MASTERTRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUSMULTIPLEXER

SLAVE

Fig 12. Acknowledgement on the I2C-bus

002aaa987

S

STARTcondition

9821

clock pulse foracknowledgement

not acknowledge

acknowledge

data outputby transmitter

data outputby receiver

SCL from master




9. Bus transactions

(1) See Table 5 for register definition.

Fig 13. Write to a specific register

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W

acknowledgefrom slave

002aac141

data for register D[4:0](1)

X X D4 D3 D2 D1 D0X

control register

Auto-Increment flag

Auto-Increment options

A


A


P

STOPcondition

Fig 14. Write to all registers using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W


002aac142

MODE1 register

0 0 0 0 0 0 01

control register

Auto-Increment on

Auto-Incrementon all registers

A


A


P

STOPcondition

(cont.)

(cont.)

MODE1registerselection

MODE2 register

A


SUBADR3 register

A


ALLCALLADR register

A


Fig 15. Multiple writes to Individual Brightness registers only using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W


002aac143

PWM0 register

0 1 0 0 0 1 01

control register

Auto-Increment on

incrementon Individual brightness registers only

A


A


P

STOPcondition

(cont.)

(cont.)

PWM0registerselection

PWM1 register

A


PWM6 register

A


PWM7 register

A


PWM0 register

A


PWMx register

A





Fig 16. Read all registers using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W


002aac144

0 0 0 0 0 0 01

control register

Auto-Increment on

Auto-Incrementon all registers

A


(cont.)

(cont.)

MODE1registerselection

data from MODE1 register

A

acknowledgefrom master

Sr

ReSTARTcondition

A5 A4 A3 A2 A1 A0 1 AA6

slave address

R/W


data from MODE2 register

A


data from PWM0

A


data fromALLCALLADR register

A


data fromMODE1 register

A


(cont.)

(cont.)

data from last read byte

A

not acknowledgefrom master

P

STOPcondition

(1) In this example, several PCA9634s are used and the same sequence (A) (above) is sent to each of them.

(2) ALLCALL bit in MODE1 register is equal to 1 for this example.

(3) OCH bit in MODE2 register is equal to 1 for this example.

Fig 17. LED All Call I2C-bus address programming and LED All Call sequence example

A5 A4 A3 A2 A1 A0 0 AS A6

slave address(1)

START condition R/W


002aac145

X X 1 0 0 0 1X

control register

Auto-Increment on

A


ALLCALLADRregister selection

0 1 0 1 0 1 X1

new LED All Call I2C address(2)

P

STOPcondition

A


0 1 0 1 0 1 0 AS 1

LED All Call I2C address

START condition R/W

acknowledgefrom the

4 devices

X X 0 1 0 0 0X

control register

A

acknowledgefrom the4 devices

LEDOUTregister selection

1 0 1 0 1 0 10

LEDOUT register (LED fully ON)

P

STOPcondition

A

acknowledgefrom the

4 devices

the 16 LEDs are on at the acknowledge(3)

sequence (A)

sequence (B)




10. Application design-in information

Question 1: What kind of edge rate control is there on the outputs?

• The typical edge rates depend on the output configuration, supply voltage, and the applied load. The outputs can be configured as either open-drain NMOS or totem-pole outputs. If the customer is using the part to directly drive LEDs, they should be using it in an open-drain NMOS, if they are concerned about the maximum ISS and ground bounce. The edge rate control was designed primarily to slow down the turn-on of the output device; it turns off rather quickly (~1.5 ns). In simulation, the typical turn-on time for the open-drain NMOS was ~14 ns (VDD = 3.6 V; CL = 50 pF; RPU = 500 ).

Question 2: Is ground bounce possible?

• Ground bounce is a possibility, especially if all 16 outputs are changed at full current (25 mA each). There is a fair amount of decoupling capacitance on chip (~50 pF), which is intended to suppress some of the ground bounce. The customer will need to determine if additional decoupling capacitance externally placed as close as physically possible to the device is required.

I2C-bus address = 0010 101X.

All of the 8 LEDn outputs configurable as either open-drain or totem pole. Mixing of configurations is not possible.

(1) OE requires pull-up resistor if control signal from the master is open-drain.

Fig 18. Typical application

PCA9634

LED0

LED1

SDA

SCL

OE

VDD = 2.5 V, 3.3 V or 5.0 V

I2C-BUS/SMBusMASTER

002aac137

SDA

SCL

10 kΩ

OE

10 kΩ

LED2

LED3

A0

A1

A2

VDD

A3

A4

A5

A6

VSS

5 V

10 kΩ(1)

12 V

LED4

LED5

LED6

LED7

5 V 12 V




Question 3: Can I really sink 400 mA through the single ground pin on the package and will this cause any ground bounce problem due to the PWM of the LEDs?

• Yes, you can sink 400 mA through a single ground pin on the package. Although the package only has one ground pin, there are two ground pads on the die itself connected to this one pin. Although some ground bounce is likely, it will not disrupt the operation of the part and would be reduced by the external decoupling capacitance.

Question 4: I can’t turn the LEDs on or off, but their registers are set properly. Why?

• Check the Mode Register 1 bit 4 SLEEP setting. The value needs to be 0 so that the OSC is turn on. If the OSC is turned off, the LEDs cannot be turned on or off and also can’t be dimmed or blinked.

Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot. Why?

• The IC outputs can be set to either open-drain or push-pull and default to push-pull outputs. In this application with the Zener diodes, they need to be set to open-drain since in the push-pull architecture there is a low resistance path to ground through the Zener and this is causing the IC to overheat. The PCA9632/33/34/35 ICs all power-up in the push-pull output mode and with the logic state HIGH, so one of the first things that need to be done is to set the outputs to open-drain.

11. Limiting values

Table 17. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.0 V

VI/O voltage on an input/output pin VSS 0.5 5.5 V

IO(LEDn) output current on pin LEDn - 25 mA

ISS ground supply current - 200 mA

Ptot total power dissipation - 400 mW

Tstg storage temperature 65 +150 C

Tamb ambient temperature operating 40 +85 C

Tj junction temperature 40 +125 C




12. Static characteristics

Table 18. Static characteristicsVDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 2.3 - 5.5 V

IDD supply current Operating mode; VDD = 2.3 V; no load; fSCL = 1 MHz

- 2.5 10 mA

Operating mode; VDD = 3.3 V; no load; fSCL = 1 MHz

- 2.5 10 mA

Operating mode; VDD = 5.5 V; no load; fSCL = 1 MHz

- 2.5 10 mA

Istb standby current VDD = 2.3 V; no load; fSCL = 0 Hz; I/O = inputs; VI = VDD

- 2.3 11 A

VDD = 3.3 V; no load; fSCL = 0 Hz; I/O = inputs; VI = VDD

- 2.9 12 A

VDD = 5.5 V; no load; fSCL = 0 Hz; I/O = inputs; VI = VDD

- 3.8 15.5 A

VPOR power-on reset voltage no load; VI = VDD or VSS[1] - 1.5 2.0 V

Input SCL; input/output SDA

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

IOL LOW-level output current VOL = 0.4 V; VDD = 2.3 V 20 - - mA

VOL = 0.4 V; VDD = 5.0 V 30 - - mA

IL leakage current VI = VDD or VSS 1 - +1 A

Ci input capacitance VI = VSS - 6 10 pF

LED driver outputs

IOL LOW-level output current VOL = 0.5 V; VDD = 2.3 V [2] 12 - - mA

VOL = 0.5 V; VDD = 3.0 V [2] 17 - - mA

VOL = 0.5 V; VDD = 4.5 V [2] 25 - - mA

IOL(tot) total LOW-level output current VOL = 0.5 V; VDD = 4.5 V [2] - - 200 mA

IOH HIGH-level output current open-drain; VOH = VDD 50 - +50 A

VOH HIGH-level output voltage IOH = 10 mA; VDD = 2.3 V 1.6 - - V

IOH = 10 mA; VDD = 3.0 V 2.3 - - V

IOH = 10 mA; VDD = 4.5 V 4.0 - - V

Co output capacitance - 2.5 5 pF

OE input

VIL LOW-level input voltage 0.5 - +0.8 V

VIH HIGH-level input voltage 2 - 5.5 V

ILI input leakage current 1 - +1 A

Ci input capacitance - 3.7 5 pF




[1] VDD must be lowered to 0.2 V in order to reset part.

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.

13. Dynamic characteristics

[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge.

Address inputs

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

ILI input leakage current 1 - +1 A

Ci input capacitance - 3.7 5 pF

Table 18. Static characteristics …continuedVDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Table 19. Dynamic characteristics

Symbol Parameter Conditions Standard-mode I2C-bus

Fast-mode I2C-bus

Fast-mode Plus I2C-bus

Unit

Min Max Min Max Min Max

fSCL SCL clock frequency [1] 0 100 0 400 0 1000 kHz

tBUF bus free time between a STOP and START condition

4.7 - 1.3 - 0.5 - s

tHD;STA hold time (repeated) START condition

4.0 - 0.6 - 0.26 - s

tSU;STA set-up time for a repeated START condition

4.7 - 0.6 - 0.26 - s

tSU;STO set-up time for STOP condition

4.0 - 0.6 - 0.26 - s

tHD;DAT data hold time 0 - 0 - 0 - ns

tVD;ACK data valid acknowledge time [2] 0.3 3.45 0.1 0.9 0.05 0.45 s

tVD;DAT data valid time [3] 0.3 3.45 0.1 0.9 0.05 0.45 s

tSU;DAT data set-up time 250 - 100 - 50 - ns

tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - s

tHIGH HIGH period of the SCL clock

4.0 - 0.6 - 0.26 - s

tf fall time of both SDA and SCL signals

[4][5] - 300 20 + 0.1Cb[6] 300 - 120 ns

tr rise time of both SDA and SCL signals

- 1000 20 + 0.1Cb[6] 300 - 120 ns

tSP pulse width of spikes that must be suppressed by the input filter

[7] - 50 - 50 - 50 ns




[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[6] Cb = total capacitance of one bus line in pF.

[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Fig 19. Definition of timing

tSPtBUF

tHD;STAPP S

tLOW

tr

tHD;DAT

tf

tHIGH tSU;DATtSU;STA

Sr

tHD;STA

tSU;STO

SDA

SCL

002aaa986

0.7 × VDD

0.3 × VDD

0.7 × VDD

0.3 × VDD

Rise and fall times refer to VIL and VIH.

Fig 20. I2C-bus timing diagram

SCL

SDA

tHD;STA tSU;DAT tHD;DAT

tftBUF

tSU;STA tLOW tHIGH

tVD;ACK

002aab285

tSU;STO

protocolSTART

condition(S)

bit 7MSB(A7)

bit 6(A6)

bit 1(D1)

bit 0(D0)

1 / fSCL

tr

tVD;DAT

acknowledge(A)

STOPcondition

(P)

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD




14. Test information

RL = Load resistor for LEDn. RL for SDA and SCL > 1 k (3 mA or less current).

CL = Load capacitance includes jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.

Fig 21. Test circuitry for switching times

PULSEGENERATOR

VO

CL50 pF

RL500 Ω

002aab284

RT

VI

VDD

DUT

VDDopenGND




15. Package outline

Fig 22. Package outline SOT163-1 (SO20)

UNITA

max. A1 A2 A3 bp c D (1) E (1) (1)e HE L Lp Q Zywv θ

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm

inches

2.65 0.30.1

2.452.25

0.490.36

0.320.23

13.012.6

7.67.4 1.27

10.6510.00

1.11.0

0.90.4 8

0

o

o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.10.4

SOT163-1

10

20

w Mbp

detail X

Z

e

11

1

D

y

0.25

075E04 MS-013

pin 1 index

0.1 0.0120.004

0.0960.089

0.0190.014

0.0130.009

0.510.49

0.300.29 0.05

1.4

0.0550.4190.394

0.0430.039

0.0350.016

0.01

0.25

0.01 0.0040.0430.0160.01

0 5 10 mm

scale

X

θ

AA1

A2

HE

Lp

Q

E

c

L

v M A

(A )3

A

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-2703-02-19




Fig 23. Package outline SOT360-1 (TSSOP20)

UNIT A1 A2 A3 bp c D (1) E (2) (1)e HE L Lp Q Zywv θ



IEC JEDEC JEITA

mm 0.150.05

0.950.80

0.300.19

0.20.1

6.66.4

4.54.3

0.656.66.2

0.40.3

0.50.2

80

o

o0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.750.50

SOT360-1 MO-15399-12-2703-02-19

w Mbp

D

Z

e

0.25

1 10

20 11

pin 1 index

θ

AA1

A2

Lp

Q

detail X

L

(A )3

HE

E

c

v M A

XA

y

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

Amax.

1.1




Fig 24. Package outline SOT662-1 (HVQFN20)

0.651

A1 EhbUNIT ye

0.2

c



IEC JEDEC JEITA

mm 5.14.9

Dh

3.252.95

y1

5.14.9

3.252.95

e1

2.6

e2

2.60.380.23

0.050.00

0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT662-1 MO-220- - - - - -

0.750.50

L

0.1

v

0.05

w

0 2.5 5 mm

scale

SOT662-1HVQFN20: plastic thermal enhanced very thin quad flat package; no leads;20 terminals; body 5 x 5 x 0.85 mm

A(1)

max.

AA1

c

detail X

yy1 Ce

L

Eh

Dh

e

e1

b

6 10

20 16

15

115

1

X

D

E

C

B A

e2



01-08-0802-10-22

ACC

Bv M

w M

E(1)D(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.




16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:




• Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave

• Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 20 and 21

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25.

Table 20. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350

< 2.5 235 220

2.5 220 220

Table 21. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245




For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature= minimum soldering temperature

maximum peak temperature= MSL limit, damage level

peak temperature

Table 22. Abbreviations

Acronym Description

CDM Charged-Device Model

DUT Device Under Test

EMI ElectroMagnetic Interference

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

IC Integrated Circuit

LCD Liquid Crystal Display

LED Light Emitting Diode

LSB Least Significant Bit

MM Machine Model

MSB Most Significant Bit

PCB Printed-Circuit Board

PWM Pulse Width Modulation

RGB Red/Green/Blue

RGBA Red/Green/Blue/Amber

SMBus System Management Bus




19. Revision history

Table 23. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9634 v.7.1 20171218 Product data sheet - PCA9634_7

Modifications: • Corrected typo in Section 2 “Features and benefits” from “LED outputs programmable to 1, 0 or ‘high-impedance’ (default at power-up)...” to “LED outputs programmable to 1 (default at power-up), 0 or ‘high-impedance’....”

PCA9634_7 20141010 Product data sheet - PCA9634_6

Modifications: • Table 17 “Limiting values”: added Tj junction temperature





PCA9634_2 20060713 Objective data sheet - PCA9634_1

PCA9634_1 20060411 Objective data sheet - -




20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.



http://www.nxp.com

http://www.nxp.com/profile/terms


Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

20.4 TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I2C-bus — logo is a trademark of NXP Semiconductors N.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]




22. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 56.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 77.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 77.1.1 Regular I2C-bus slave address. . . . . . . . . . . . . 77.1.2 LED All Call I2C-bus address . . . . . . . . . . . . . . 87.1.3 LED Sub Call I2C-bus addresses . . . . . . . . . . . 87.1.4 Software Reset I2C-bus address . . . . . . . . . . . 87.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 97.3 Register definitions . . . . . . . . . . . . . . . . . . . . . 107.3.1 Mode register 1, MODE1 . . . . . . . . . . . . . . . . 117.3.2 Mode register 2, MODE2 . . . . . . . . . . . . . . . . 117.3.3 PWM0 to PWM7: Individual brightness control 127.3.4 GRPPWM: Group duty cycle control . . . . . . . 137.3.5 GRPFREQ: Group frequency . . . . . . . . . . . . . 137.3.6 LEDOUT0 and LEDOUT1: LED driver output

state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147.3.7 SUBADR1 to SUBADR3: I2C-bus subaddress

1 to 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147.3.8 ALLCALLADR: LED All Call I2C-bus address. 157.4 Active LOW output enable input . . . . . . . . . . . 157.5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 167.6 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 167.7 Using the PCA9634 with and without external

drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177.8 Individual brightness control with group

dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 19

8 Characteristics of the I2C-bus . . . . . . . . . . . . 208.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 208.1.1 START and STOP conditions . . . . . . . . . . . . . 208.2 System configuration . . . . . . . . . . . . . . . . . . . 208.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 22

10 Application design-in information . . . . . . . . . 24

11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25

12 Static characteristics. . . . . . . . . . . . . . . . . . . . 26

13 Dynamic characteristics . . . . . . . . . . . . . . . . . 27

14 Test information. . . . . . . . . . . . . . . . . . . . . . . . 29

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30

16 Handling information . . . . . . . . . . . . . . . . . . . 33

17 Soldering of SMD packages. . . . . . . . . . . . . . 3317.1 Introduction to soldering. . . . . . . . . . . . . . . . . 3317.2 Wave and reflow soldering. . . . . . . . . . . . . . . 3317.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 3317.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 34

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35

19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 36

20 Legal information . . . . . . . . . . . . . . . . . . . . . . 3720.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 3720.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3720.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 3720.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38

21 Contact information . . . . . . . . . . . . . . . . . . . . 38

22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

© NXP Semiconductors N.V. 2017. All rights reserved.

For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 18 December 2017

Document identifier: PCA9634

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

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