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G53SRP: Hardware interfacing

Chris GreenhalghChris Greenhalgh

G53SRPG53SRP

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Contents• PC/bus architecturePC/bus architecture• Device registersDevice registers

– I/O instructionsI/O instructions– High-level language supportHigh-level language support– Device register interactionDevice register interaction– Bit-wise operators (review)Bit-wise operators (review)

• InterruptsInterrupts– High-level language supportHigh-level language support

• Java, RTSJ Java and CJava, RTSJ Java and C

• Book: Burns & Wellings 15.1, 15.2, 15.5, 15.7, Book: Burns & Wellings 15.1, 15.2, 15.5, 15.7, Wellings 15 intro & 15.3, plus a few extra bits :-)Wellings 15 intro & 15.3, plus a few extra bits :-)

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Typical PC architecture

CPU

memory Disc controller

disc

Keyboardcontroller

GeneralI/O

Controller?

VDU controller

Other hardware…

Businterface/

bridge

System bus

Expansion bus (e.g. PCI, ISA,…)

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Buses

• Def.Def.– "Common set of electrical connections""Common set of electrical connections"

• Standard interfaceStandard interface– control signalscontrol signals– address signalsaddress signals– data signalsdata signals

• Standard protocol (rules)Standard protocol (rules)– read cycleread cycle– write cyclewrite cycle– interrupt cycle (see notes on device programming)interrupt cycle (see notes on device programming)

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Example: CPU read cycle

Address(from CPU)

0x394 (e.g.)

Control: “read memory”(from CPU)

Data(from memory)

0x45 (e.g.)

Time

Memory retrieves requested data

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Device registers

• "Look" like memory"Look" like memory– status registers (read)status registers (read)– control registers (write)control registers (write)– data buffer registers (read/write)data buffer registers (read/write)

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I/O instructions

• Memory mapped Memory mapped – (same physical & logical bus)(same physical & logical bus)– normal read/write instructionsnormal read/write instructions– E.g. Motorola 68000E.g. Motorola 68000

MOVE.L reg,addressMOVE.L reg,address

• Separate I/O space Separate I/O space – (separate physical or logical bus)(separate physical or logical bus)– dedicated I/O instructionsdedicated I/O instructions– E.g. Intel x86:E.g. Intel x86:

IN reg, portIN reg, portOUT reg, portOUT reg, port

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HLL register access

• Requires either HLL functions which wrap Requires either HLL functions which wrap these low-level operationsthese low-level operations

E.g. E.g. – Linux kernel helper routines: Linux kernel helper routines: void outb(unsigned char byte, void outb(unsigned char byte, unsigned int port); unsigned int port);unsigned char inb(unsigned int port);unsigned char inb(unsigned int port);

– RTJava RTJava RawMemoryAccessRawMemoryAccess class class • see over and memory areas notessee over and memory areas notes

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RawMemoryAccess class

package javax.realtime;package javax.realtime;

public class public class RawMemoryAccessRawMemoryAccess { {

public RawMemoryAccess(public RawMemoryAccess(

Object type,Object type,

long base,long base,

long size);long size);

… …

public byte getByte(long offset);public byte getByte(long offset);

public int getInt(long offset);public int getInt(long offset);

public void setByte(long offset, byte value);public void setByte(long offset, byte value);

public void setInt(long offset, int value);public void setInt(long offset, int value);

… …

}}

As for Physical memory areas

Raw memory bytes

Byte order platform dependent…

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HLL register access (2)

• Or Ability to mix HLL and assembly languageOr Ability to mix HLL and assembly language

E.g. C/C++E.g. C/C++– gcc: gcc: /*C…*//*C…*/asm("movl %ecx %eax"); asm("movl %ecx %eax"); /*C…*//*C…*/

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Register value manipulation (1)

• The same location may have different The same location may have different functionsfunctions– Setting other bits/registers may determine what Setting other bits/registers may determine what

register/function it actually has when accessedregister/function it actually has when accessed– Reading and writing may have different Reading and writing may have different

functionsfunctions• Reading a status register vs writing to a completely Reading a status register vs writing to a completely

different control register from/to same locationdifferent control register from/to same location

=> May need to maintain “shadow” control register => May need to maintain “shadow” control register values in code since cannot rely on reading values values in code since cannot rely on reading values backback

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Register value manipulation (2)

• Registers often contain packed binary dataRegisters often contain packed binary data– Minimise number of addresses requiredMinimise number of addresses required– Minimise rounds of communicationMinimise rounds of communication

• Requires extensive use of bit-manipulation Requires extensive use of bit-manipulation operations in the driver…operations in the driver…

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Java integer types

TypeType BitsBits

bytebyte 88

(char)(char) 16 (unicode)16 (unicode)

shortshort 1616

intint 3232

longlong 6464

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C (default) integer types

TypeType BitsBits

[unsigned] char[unsigned] char 88

wcharwchar 16 (unicode)16 (unicode)

[unsigned] short[unsigned] short 1616

[unsigned] int[unsigned] int 32 (may be 16)32 (may be 16)

[unsigned] long[unsigned] long 3232

[unsigned] long long[unsigned] long long 6464

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Hexadecimal (0x…)HexHex BinaryBinary

0x00x0 00000000

0x10x1 00010001

0x20x2 00100010

0x30x3 00110011

0x40x4 01000100

0x50x5 01010101

0x60x6 01100110

0x70x7 01110111

0x80x8 10001000

0x90x9 10011001

0xA0xA 10101010

0xB0xB 10111011

0xC0xC 11001100

0xD0xD 11011101

0xE0xE 11101110

0xF0xF 11111111

NB. Exactly 4 bits/digit

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Octal (0…)OctalOctal BinaryBinary

0000 000000

0101 001001

0202 010010

0303 011011

0404 100100

0505 101101

0606 110110

0707 111111

NB. Exactly 3 bits/digit

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Unary Bit-wise operators

• ~ (bitwise complement)~ (bitwise complement)

NN 0x460F 0x460F 0100011000001111 0100011000001111

~N~N 0xB9F0 0xB9F0 1011100111110000 1011100111110000

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Bit-shift operators

• << (left shift)<< (left shift)– 0x1234 << 30x1234 << 30001001000110100 base 20001001000110100 base 2

– = 0x91A0= 0x91A01001000110100000 base 21001000110100000 base 2

• >> (right shift)>> (right shift)– 0x1234 >> 30x1234 >> 30001001000110100 base 20001001000110100 base 2

– = 0x0246= 0x02460000001001000110 base 20000001001000110 base 2

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Binary bit-wise operatorsOperatorOperator OperationOperation ExampleExample

&& And (true only if both arguments are true)And (true only if both arguments are true)(can be used to "select" bits from the first (can be used to "select" bits from the first argument argument and/or force bits to 0 in the result)and/or force bits to 0 in the result)

0x3E & 0x19 = 0x180x3E & 0x19 = 0x18001111100011111022 & &000110010001100122 = =000110000001100022

|| Or (true if either or both arguments are true)Or (true if either or both arguments are true)(can be used to force bits to 1 in the result)(can be used to force bits to 1 in the result)

0x3E | 0x19 = 0x3F0x3E | 0x19 = 0x3F001111100011111022 | |000110010001100122 = =001111110011111122

^̂ Exclusive Or (true if exactly one argument is Exclusive Or (true if exactly one argument is true)true)

0x3E ^ 0x19 = 0x270x3E ^ 0x19 = 0x27001111100011111022 ^ ^000110010001100122 = =001001110010011122

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Interrupts

• Device-initiatedDevice-initiated– I.e. asynchronous, external eventsI.e. asynchronous, external events

• Controlled by device control registersControlled by device control registers– E.g. individually enabled & disabledE.g. individually enabled & disabled

• Managed by CPUManaged by CPU– I.e. can be temporarily ignored under program I.e. can be temporarily ignored under program

control (See later notes)control (See later notes)

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Approaches to device control

• Status drivenStatus driven– CPU pollsCPU polls

• Interrupt driven, i.e. interrupt from device Interrupt driven, i.e. interrupt from device initiates…initiates…– CPU controlledCPU controlled

• All data transfer performed by (main) CPUAll data transfer performed by (main) CPU

– CPU initiated (Direct Memory Access)CPU initiated (Direct Memory Access)• Data transfer delegated to specialised helper unitData transfer delegated to specialised helper unit

– Channel controlledChannel controlled• Data transfer (perhaps also interrupt handling) delegated Data transfer (perhaps also interrupt handling) delegated

to specialised I/O processor (“channel”) (mainframe!)to specialised I/O processor (“channel”) (mainframe!)

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Note

• Interrupts and DMA/channel IO can result in Interrupts and DMA/channel IO can result in CPU cycles being “lost” or “stolen” from the CPU cycles being “lost” or “stolen” from the main process(es)main process(es)– Increases worst-case execution time(s)Increases worst-case execution time(s)– May make process sets unschedulableMay make process sets unschedulable– So interrupts are often disabled in safety critical So interrupts are often disabled in safety critical

systemssystems• Rely on guaranteed scheduled polling ratesRely on guaranteed scheduled polling rates

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HLL support for interrupts (1)

• Interrupt handler:Interrupt handler:– Can call suitable procedures directlyCan call suitable procedures directly

• E.g. C subroutine address registered as handler for low-E.g. C subroutine address registered as handler for low-level interruptlevel interrupt

– Or requires some other way to bind HLL process to Or requires some other way to bind HLL process to interruptinterrupt

• E.g. RTSJ E.g. RTSJ AsyncEventHandlerAsyncEventHandler for for AsyncEventAsyncEvent with interrupt bound to HW Interruptwith interrupt bound to HW Interrupt

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HLL support for interrupts (2)• Requires access to interrupt management Requires access to interrupt management

operationsoperations– (again) inclusion of relevant machine code (again) inclusion of relevant machine code

instructions instructions • E.g. to set/clear interrupt enable bitE.g. to set/clear interrupt enable bit

– Or wrapper functions in HLL giving access to theseOr wrapper functions in HLL giving access to these• E.g. Linux C helper functions (set/clear interrupt enable E.g. Linux C helper functions (set/clear interrupt enable

bit)bit)void sti(void);void sti(void);

void cli(void);void cli(void);

– Or other language-specific mechanismsOr other language-specific mechanisms• E.g. RTSJ priority-based scheduling of handlers, plus use E.g. RTSJ priority-based scheduling of handlers, plus use

of Java Synchronisationof Java Synchronisation

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High-level language facilities

• Assembly languageAssembly language– Low level!!Low level!!

• Java (non-RTSJ)…Java (non-RTSJ)…

• RTSJ Java…RTSJ Java…

• C…C…

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Non-RTSJ Java

• Con:Con:– No direct access to memoryNo direct access to memory– No bit field typesNo bit field types– No machine-specific I/O instructionsNo machine-specific I/O instructions– No link to hardware interruptsNo link to hardware interrupts– No access to interrupt managementNo access to interrupt management– Difficult machine code integrationDifficult machine code integration– Fixed method prologues/epiloguesFixed method prologues/epilogues– Unpredictable GCUnpredictable GC– Relatively heavy-weight classes/methodsRelatively heavy-weight classes/methods

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RTSJ Java

• Con:Con:– No bit field typesNo bit field types

– Difficult machine code integration (but shouldn’t need it?!)Difficult machine code integration (but shouldn’t need it?!)

– Fixed method prologues/epilogues (but shouldn’t matter?!)Fixed method prologues/epilogues (but shouldn’t matter?!)

– Relatively heavy-weight classes/methodsRelatively heavy-weight classes/methods

• Pro:Pro:– Direct access to memory via APIDirect access to memory via API

– Machine-specific I/O via APIMachine-specific I/O via API

– Link to hardware interrupts via async. eventsLink to hardware interrupts via async. events

– Access to interrupt management via schedulingAccess to interrupt management via scheduling

– Alternative memory management options to control GCAlternative memory management options to control GC

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C

• Pro:Pro:– Supports native pointersSupports native pointers– Includes bit fieldsIncludes bit fields– (Relatively) easy inclusion of assembly(Relatively) easy inclusion of assembly– C procedure = machine code subroutineC procedure = machine code subroutine– Customisable prologue/epilogueCustomisable prologue/epilogue

• Con:Con:– Lack of classes, GC, etc.Lack of classes, GC, etc.

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Some example devices

• simple joystick interface simple joystick interface – 2001 exam, Q2 2001 exam, Q2

• printer interfaceprinter interface– 2002 exam, Q1 2002 exam, Q1

• UART (serial line)UART (serial line)– appendix Aappendix A

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Summary (1)

• PC/bus architecture interfaces to hardware viaPC/bus architecture interfaces to hardware via– Registers = virtual memory locationsRegisters = virtual memory locations

– Interrupts = asynchronous notifications from deviceInterrupts = asynchronous notifications from device

• Device registers typicallyDevice registers typically– Status of device/interface – readStatus of device/interface – read

– Control of device – write Control of device – write

– Data input/output – read/writeData input/output – read/write

• Accessed via custom I/O instructions or mapped Accessed via custom I/O instructions or mapped memory accessmemory access– RTSJ access via RTSJ access via RawMemoryAccessRawMemoryAccess

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Summary (2)

• Interrupts allow more efficient/timely Interrupts allow more efficient/timely (non-polling) notification of CPU by (non-polling) notification of CPU by devicedevice– RTSJ support via RTSJ support via AsyncEvent AsyncEvent bound to bound to

interruptinterrupt– Management via RTSJ scheduling facilities Management via RTSJ scheduling facilities

and Java synchronizationand Java synchronization

• Non-RTSJ Java unsuitable for device Non-RTSJ Java unsuitable for device interfacinginterfacing– C suitable (e.g. Linux/UNIX device drivers)C suitable (e.g. Linux/UNIX device drivers)