1 Design of Synchronous Reference Frame Phase-Locked Loop … · 2016. 6. 28. · Phase-locked...

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1 Design of Synchronous Reference Frame Phase-Locked Loop with the Presence of DC Offsets in the Input Voltage Abhijit Kulkarni and Vinod John Department of Electrical Engineering, IISc Bangalore, India ( [email protected], [email protected]) Abstract A novel small-signal state-space model is formulated for the commonly used synchronous reference frame phase- locked loop (SRF-PLL). Using this model, the effect of dc offsets as a function of SRF-PLL design parameters is quantified. It is shown that the unit vectors produced by the PLL will have dc offsets when the input contains dc offsets. This can result in dc injection to the grid which is highly undesirable. A systematic design method is proposed which ensures that dc injection to the grid is within the prescribed grid interconnection standards. In this design, SRF-PLL bandwidth is analytically computed for different levels of dc offsets in the input. The proposed design is compared with conventional pre-filter based designs addressing the dc offset issue. The proposed design method results in fastest transient response for given worst-case input dc offset without changing the PLL structure. Such a design for the SRF-PLL is computationally less intensive and is preferable when low-end digital controllers are used. The analytical results have been verified experimentally. I. I NTRODUCTION Phase-locked loops (PLLs) are used in grid connected power converter topologies for synchronization with the grid voltage. PLLs are required to ensure proper power flow from the source of the power converter to the grid. PLLs used in power converters with renewable energy sources are reported in works such as [1]–[3]. PLLs can also be used for control and monitoring purposes [4], [5]. The PLLs are implemented in a digital controller along with the closed-loop control algorithm. Digital controllers used can be high-end floating-point digital signal processors (DSPs), field programmable gate arrays (FPGAs) or microcontrollers such as dsPIC depending on cost and required complexity of implementation. Synchronous reference frame phase-locked loop (SRF-PLL) is a commonly used three-phase PLL in grid- connected power converters. The SRF-PLL is used to estimate the frequency and phase of the grid voltage. Unit amplitude sine and cosine signals are output from the PLL using the estimated phase. These are called unit vectors. Page 1 of 26 IET Review Copy Only IET Power Electronics

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1

Design of Synchronous Reference Frame

Phase-Locked Loop with the Presence of DC

Offsets in the Input VoltageAbhijit Kulkarni∗ and Vinod John†

Department of Electrical Engineering,

IISc Bangalore, India

(∗[email protected], †[email protected])

Abstract

A novel small-signal state-space model is formulated for the commonly used synchronous reference frame phase-

locked loop (SRF-PLL). Using this model, the effect of dc offsets as a function of SRF-PLL design parameters is

quantified. It is shown that the unit vectors produced by the PLL will have dc offsets when the input contains dc

offsets. This can result in dc injection to the grid which is highly undesirable. A systematic design method is proposed

which ensures that dc injection to the grid is within the prescribed grid interconnection standards. In this design,

SRF-PLL bandwidth is analytically computed for different levels of dc offsets in the input. The proposed design

is compared with conventional pre-filter based designs addressing the dc offset issue. The proposed design method

results in fastest transient response for given worst-case input dc offset without changing the PLL structure. Such a

design for the SRF-PLL is computationally less intensive and is preferable when low-end digital controllers are used.

The analytical results have been verified experimentally.

I. INTRODUCTION

Phase-locked loops (PLLs) are used in grid connected power converter topologies for synchronization with the

grid voltage. PLLs are required to ensure proper power flow from the source of the power converter to the grid.

PLLs used in power converters with renewable energy sources are reported in works such as [1]–[3]. PLLs can also

be used for control and monitoring purposes [4], [5]. The PLLs are implemented in a digital controller along with

the closed-loop control algorithm. Digital controllers used can be high-end floating-point digital signal processors

(DSPs), field programmable gate arrays (FPGAs) or microcontrollers such as dsPIC depending on cost and required

complexity of implementation.

Synchronous reference frame phase-locked loop (SRF-PLL) is a commonly used three-phase PLL in grid-

connected power converters. The SRF-PLL is used to estimate the frequency and phase of the grid voltage. Unit

amplitude sine and cosine signals are output from the PLL using the estimated phase. These are called unit vectors.

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In the closed-loop control of grid-connected power converters, these unit vectors are used to generate reference

signals.

SRF-PLL is simple to implement and its qualitative design aspects are discussed in [6], [7]. The performance

of the PLL is affected by the presence of unbalance, harmonics and dc offsets in the input voltage. The impact of

unbalance and harmonics on the unit vectors is quantified in [8]. When the input contains dc offsets, the estimated

frequency and phase contain a sinusoidal ripple at the fundamental frequency [7]. In addition to this ripple, the unit

vectors produced by the PLL will contains dc offsets. This is stated in [1] but it has not been quantified. In this

paper, the occurrence of dc offsets in the unit vectors when the input contains dc offsets is proved mathematically.

The amount of dc offsets in the unit vectors is analytically quantified for a given amount of input dc offsets for SRF-

PLL. Conventionally, the inverter current controller has a low-pass configuration. Hence for the conventional current

controller designs, the gain of the closed-loop transfer function at dc is unity [9], [10]. Consequently, when the

unit vectors used as references contain dc offsets, there will be dc injection to the grid which is highly undesirable.

This is explained with reference to a grid connected inverter, shown in Fig. 1, with a distributed generation source

such as photovoltaic panels.

S1 S3

S2 S4

L

vDG

iDG

ia

C

SRF-PLL

Current

Controller

PWM

S5

S6

~~

~

ibic

Va

VbVc

id,ref

iq,ref

dq-abc

va,ref

vb,ref

vc,ref

S1 S6

Pulses toGate-driver

vavb

vc

VoltageSensor

abc-dq

ia

ib

ic

id

iq

Unit Vectors

vd,ref

vq,refCurrent

Controller

Fig. 1: A three-phase grid connected inverter and its closed-loop control implementation including SRF-PLL.

The closed-loop control for this inverter involves injecting sinusoidal current into the grid, often at unity power

factor [11], [12]. The current references are given in dq rotating reference frame. The voltage reference is generated

from vd,ref and vq,ref using the unit vectors as shown in Fig. 1. If the unit vectors contain dc offsets, then the

applied inverter voltage will contain dc offsets. This results in dc injection to the grid. Thus, the problem due to the

dc offsets to the input of PLL becomes severe because grid interconnection standards such as IEEE 1547-2003 [13],

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IEC 61727 [14] have stringent requirement on the dc injection to the grid.

The reasons for the presence of dc offsets in the input to the PLL are – dc offsets in the voltage sensors,

analog-to-digital converters (ADCs) and mismatch in semiconductor switches in practical grid-connected power

converters [15].

There are many advanced three-phase and single-phase PLLs proposed in literature [16]–[23] to improve the

performance of PLL during non-ideal grid voltages; and some PLL topologies specifically address the dc offset

problem [24]–[27]. However, the advantage of the SRF-PLL over the advanced PLLs is its simple implementation.

If any low-end digital controller is used for the implementation, SRF-PLL would save considerable digital resources

and reduce the computation time. Thus, it is necessary to have a detailed design for the basic SRF-PLL when the

input has dc offsets. The design objectives for the SRF-PLL can be stated as,

1) For a given worst-case dc offset input, the SRF-PLL should produce unit vectors which satisfy the grid

interconnection standards such as IEEE 1547-2003.

2) The response time for the SRF-PLL should be the least for given worst-case dc offset input.

In addition to these, the phase and magnitude error should be negligible when the frequency of the grid voltage

deviates from the nominal value.

The initial part of this paper is devoted for quantitative analysis of the impact of dc offsets on SRF-PLL. A novel

linear small-signal state-space model is formulated to evaluate the sinusoidal ripple in the estimated frequency and

phase. This model is useful for the following computations.

(a) For a known amount of input dc offset, the resulting dc offsets in the unit vectors can be computed.

(b) Variation of unit vector dc offset versus SRF-PLL bandwidth can be obtained for a given amount of dc offset

in the input.

(c) Effect of unbalance and harmonics can be quantified.

The new design method proposed in this paper uses points (a) and (b) mentioned above. The largest bandwidth that

limits the unit vector dc offsets to be within 0.5% is selected. This is because the dc current injection limit used is

0.5% as per [13]. Any bandwidth lower than this value would also be acceptable. However, the bandwidth chosen

from the proposed method gives the fastest settling time. The proposed method decouples the design of inverter

current controller and the SRF-PLL. Hence, with the proposed approach, the SRF-PLL unit vectors will not cause

the problem of dc injection to the grid for typical current controller design.

Conventionally pre-filters such as bandpass filter (BPF) and highpass filter (HPF) are used for removing the dc

offset from the sensed voltages [23], [28]. These pre-filters result in phase and magnitude error in the PLL when

the grid frequency deviates from nominal value. They also introduce additional delays affecting the overall transient

response of the PLL. The pre-filters will have to be frequency adaptive in order to eliminate magnitude and phase

errors which adds to complexity and computation time/resource utilization for the digital controller used.

The design proposed in this paper satisfies the design objectives stated earlier without modifying the basic

structure of the SRF-PLL. The performance of the proposed design is also compared with the pre-filter based

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designs. It is shown that the proposed design considering dc offsets does not have any magnitude or steady-state

phase error unlike the pre-filters based SRF-PLL. The performance of the SRF-PLL with the proposed bandwidth

tuning method is verified experimentally. Both steady-state and transient responses are validated in the experiments.

II. LINEAR SMALL-SIGNAL STATE-SPACE MODELLING OF SRF-PLL

The structure of the SRF-PLL is shown in Fig. 2. The input to the PLL are the three-phase sensed voltage

+

- ++

SineTable

Pre-filter

Pre-filter

Without pre-filter

Without pre-filter

S

Fig. 2: Structure of a three-phase SRF-PLL. The position of the switch S determines whether a dc blocking pre-filter

is included for vα and vβ .

signals va, vb and vc. These are converted two-phase stationary reference frame signals vα and vβ . This stationary

three-phase to two-phase frame transformation (abc− αβ) is given by,

vαvβ

=

23 − 1

3 − 13

0 1√3

− 1√3

va

vb

vc

(1)

For the basic SRF-PLL, the pre-filters are not used. Hence, the ‘switch’ S shown in Fig. 2 is kept in such a way

that vα and vβ are directly fed into the next block which is the αβ to dq rotating reference frame transformation

block. This transformation is given by,vdvq

=

cos θe sin θe

− sin θe cos θe

vαvβ

(2)

The PI controller used in the PLL ensures that vd = 0 in the steady state and the grid voltage vector is ideally

aligned along the q−axis. The outputs of the PLL are ωe, θe and the unit vectors sin θe, cos θe. The variables ωe

and θe are the estimated frequency and phase angle respectively. These can be taken as the state variables in this

system. This system is non-linear due to the stationary to rotating reference frame transformation.

From (2), the expression for vd is,

vd = vα cos θe + vβ sin θe (3)

The derivative of vd can be computed using (3) as,

vd = vα cos θe + vβ sin θe − vαωe sin θe + vβωe cos θe (4)

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In arriving at (4), the following equation is used

θe = ωe (5)

The estimated frequency ωe is given by

ωe = −kpvd − ki�vddt+ ωff (6)

Thus,

ωe = −kpvd − kivd (7)

Substituting (4) in (7),

ωe =(−kpvα − kpωevβ − kivα) cos θe + (−kpvβ + kpωevα − kivβ) sin θe

=p1 cos θe + p2 sin θe (8)

Where

p1 =− kpvα − kpωevβ − kivα (9)

p2 =− kpvβ + kpωevα − kivβ (10)

The state-space formulation for the SRF-PLL is given by the equations (5) and (8). Note that (8) is a non-

linear equation. The model can be linearized around an operating point. This is done to study the gain and phase

characteristics, the stability and transient responses.

The inputs and the state variables are defined as follows:

vα =vα0 + vα ; vβ = vβ0 + vβ

ωe =ω0 + ωe ; θe = θ0 + θe (11)

The SRF-PLL is assumed to operate normally with the state variable values being ω0, θ0 and inputs being vα0 and

vβ0. Any perturbation in the input causes perturbations in the state variables which are indicated as terms with tilde

in (11). The normal operation of SRF-PLL has vα and vβ to be quadrature signals with vβ lagging by 90◦. Thus,

vα0 = Vm sin θ ; vβ0 = −Vm cos θ (12)

In (12), the frequency of vα0 and vβ0 is same as the assumed steady frequency ω0 which is equal to 2π50 rad/s

in a 50Hz system. Thusdθ

dt= ω0 (13)

The variables defined in (11) and (12) are substituted in the original state equations of (5) and (8). They are

simplified to remove the large signal terms. The products of small signal terms are ignored and the resulting small

signal equations are determined. Final state-space equations are given in (14).

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˙ωe˙θe

=

−kpVm −kiVm

1 0

ωeθe

+

kpω0 sin θ0 − ki cos θ0 −kpω0 cos θ0 − ki sin θ0

0 0

vαvβ

+

−kp cos θ0 −kp sin θ0

0 0

˙vα

˙vβ

(14)

The detailed algebraic steps used for obtaining the final state equations are given in Appendix A.

The term θ0 is equal to ω0t and the PI controller parameters are known for a given design of the SRF-PLL.

Vm and ω0 are the nominal peak and frequency of the sensed grid voltage. The derived state-space model in (14)

is linear but time varying. However, for this model in (14), the time varying nature does not impede in solving

it analytically. The steady-state solution for the system for dc offsets in the input is obtained in Section III. To

quantify the impact of dc offsets, the input disturbances vα and vβ are taken as the dc offsets in (αβ) reference

frame. From the values of vα, vβ , and the PLL parameters, the steady-state ripple in estimated frequency and phase

(ωe and θe) can be determined. Evaluation of the dc offset and harmonic distortion in the unit vectors can be done

using the computed ωe and θe. This is explained in the Section III. The state equations in (14) can also be used

to compute the steady-state errors in estimated phase (θe) and frequency (ωe) when the input contains unbalance

and distortion. As this paper is concerned about the dc offset issue, the following section derives the expressions

for errors due to dc offsets only.

III. QUANTIFYING THE EFFECT OF THE DC OFFSETS ON SRF-PLL

Presence of dc offsets in va, vb, vc and hence vα, vβ results in sinusoidal ripple error in estimated frequency

and phase [7]. In this section, expressions are derived for computing these errors using the derived small-signal

state-space model. It is also shown that the unit vectors will get distorted and will have a dc offset. Expressions

are derived to compute the distortion and the amount of dc offsets in the unit vectors.

A. Derivation of the Error in Estimated Frequency and Phase

From the state equations derived in the previous section, it is possible to theoretically estimate the effect of dc

offsets in SRF-PLL. The dc offsets are normally small and hence can be considered as small signal inputs to the

state variables. Let the offset disturbances be vα0 and vβ0 which are dc quantities. The state-space model is to be

solved to get steady-state solutions for the ripple in estimated frequency and phase. Hence, the derivatives of the

dc offset disturbances vα0 and vβ0 are set to be zero for the steady-state solutions.

Using this, the first state equation in (14) for ωe is written as

˙ωe =− kpVmωe − kiVmθe + (kpω0 sin θ0 − ki cos θ0)vα0 − (kpω0 cos θ0 + ki sin θ0)vβ0 (15)

Let

x =(kpω0 sin θ0 − ki cos θ0)vα0 − (kpω0 cos θ0 + ki sin θ0)vβ0 (16)

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Then, using (15) and (16),

˙ωe + kpVmωe + kiVmθe = x (17)

By collecting the coefficients of sin θ0 and cos θ0, and simplifying; x can be written as,

x =�a2 + b2 sin(θ0 + φ0) (18)

Where,

a =kpω0vα0 − kivβ0 , b = −kivα0 − kpω0vβ0

φ0 =tan−1

�kivα0 + kpω0vβ0kivβ0 − kpω0vα0

�(19)

Using ˙θe = ωe, equation (17) can be rewritten in the variable θe only as,

¨θe + kpVm

˙θe + kiVmθe =

�a2 + b2 sin(θ0 + φ0) (20)

Equation (20) is a second order linear differential equation with sinusoidal excitation. The excitation input has a

frequency of ω0 since θ0 = ω0t. Thus, the dc offset in input voltage results in a ripple at the fundamental frequency

for the estimated phase.

Using θ0 = ω0t, the steady-state solution to the differential equation in (20) is,

θe = m�a2 + b2 sin(ω0t+ φ0 +mθ) (21)

The sinusoidal excitation to a linear system results in an amplitude change and a phase change in the output. The

amplitude change is given by the term m and the phase change is given by the angle mθ in (21). These can be

computed from the following expressions.

m =

����1

−ω20 + Vm(jkpω0 + ki)

����

mθ =− tan−1

�kpVmω0kiVm − ω2

0

�(22)

Thus, the ripple in the estimated angle can be computed using (21) and (22) for a known offset level in the

input represented by vα0 and vβ0. The offsets would be normally known in terms of the three phase voltages

(va0, vb0, vc0). They can be converted to the two phase α− β values using (1).

The error in the estimated frequency ωe can be computed by differentiating the solution in (21). The amplitude

of frequency error is given by

ωem = mω0�a2 + b2 (23)

Thus, given the PI controller parameters kp, ki and the dc offsets present in the input, the sinusoidal ripple in

estimated phase and frequency can be computed from (21), (22) and (23).

If any advanced SRF-PLL without any dc offset compensation is used, then the equations derived above can be

used to compute the error in estimation. This is because, from the dc offset perspective, the advanced SRF-PLL is

equivalent to the basic SRF-PLL.

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B. Derivation of the Distortion and DC Offsets in Unit Vectors

The sinusoidal ripple in the estimated phase angle has the effect of distorting the unit vectors and introducing a

dc offset in them. The occurrence of dc offset in the unit vectors is highly undesirable as explained in Section I.

The actual estimated phase angle by the PLL is given by

θe = ω0t+ θe (24)

In (24), θe is the ripple at fundamental frequency in the estimated phase. Its magnitude can be computed from

(22).

The sine unit vector is given by,

u1 =sin(ω0t+ θe)

≈ sinω0t+m�a2 + b2 sin(ω0t+ φ0 +mθ) cosω0t

=sinω0t+ 0.5m�a2 + b2 sin(2ω0t+ φ0 +mθ) + 0.5m

�a2 + b2 sin(φ0 +mθ) (25)

It can be seen from (25) that the unit vector contains a distortion at the second harmonic and it also contains a

dc offset term. The second harmonic amplitude is given by m√a2 + b2/2. The dc offset u10 is given by

u10 = 0.5m�a2 + b2 sin(φ0 +mθ) (26)

Similarly, the cosine unit vector can be computed to be,

u2 =cosω0t+ 0.5m�a2 + b2 cos(2ω0t+ φ0 +mθ)− 0.5m

�a2 + b2 cos(φ0 +mθ) (27)

The second harmonic amplitude for cosine unit vector is same as that of the sine unit vector. However, the dc offset

is different and it is given by

u20 = −0.5m�a2 + b2 cos(φ0 +mθ) (28)

The amount of dc offset in unit vectors, given the offset in input and the PLL parameters, can be computed using (26)

and (28). The PI controller parameters can be related to the SRF-PLL design bandwidth [6]. Thus, the expressions

for u10, u20 can be written in terms of design bandwidth. These expressions are provided in Appendix B.

IV. DESIGN OF SRF-PLL CONSIDERING THE DC OFFSETS IN THE INPUT

It is mentioned in [7] that a reduction in SRF-PLL bandwidth reduces the ripple in estimated phase and frequency.

However, there is no clear guideline in literature to arrive at an exact value of the bandwidth. In this paper, a design

method is proposed which can be used to compute an exact value of the required bandwidth assuming a known

worst-case dc offset level in the input.

Let the maximum expected dc offset magnitude in any of the three-phase voltages be y (%). Note that y is

taken as a positive quantity. If all the three-phase voltages have identical offsets, then they do not appear in vα and

vβ which can be verified from (1). Thus there are six different combinations for dc offsets possible depending on

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TABLE I: Six different polarity combinations of dc offsets in the three-phase input.

Combination Input dc offsets

1 + + −2 + − −3 + − +

4 − − +

5 − + +

6 − + −

positive and negative polarity. They are listed in Table I. Consider combination-1 which is represented as + + −in Table I. This means the three-phase inputs va, vb, vc have dc offsets of +y, + y, − y respectively.

The design steps are detailed in the following points.

1) For each ith combination of the dc offsets (i = 1, 2 . . . 6), compute the dc offsets in vα and vβ using (1).

2) Plot unit vector dc offset (u10, u20) versus the design bandwidth for each of the six combinations using (26),

(28) and (B.54).

3) For each of the ith case, let the highest bandwidth that results in min(u10, u20) ≤ 0.5% be ωbw,i.

4) The design bandwidth (ωbw) will be the minimum of all the six ωbw,i computed in Step - 3 above. That is,

ωbw = min(ωbw,i) for i = 1, 2 . . . 6.

5) Compute kp, ki for the SRF-PLL from ωbw as detailed in Appendix B.

This method is illustrated for assumed worst-case dc offsets of y = 2% in the input. Fig. 3(a) shows the unit

vector dc offset versus bandwidth for combination-1 of dc offsets. It can be observed that the bandwidth has to

be less than or equal to 25 Hz to limit unit vector offset to within 0.5%. The plots for combinations-2 and 3 are

shown in Fig. 3(b) and Fig. 3(c) respectively. It is observed that if combination i and j are complements of each

other, then their unit vector dc offset versus bandwidth plots are identical. Thus combination 1 and 4; 2 and 5; 3

and 6 give the same response. Hence, only three plots are shown in Fig. 3. It is observed that for combination 2

and 5, the required bandwidth is 22.4 Hz. Similarly, for combination 3 and 6, the required bandwidth is 20.4 Hz.

As the least of the three values has to be chosen, the required bandwidth for SRF-PLL is 20.4 Hz or 128 rad/s

when the input contains a worst case dc offset level of y = 2%.

The Fig. 3 shows the plots when the input dc offset magnitude y = 2%. Similar plots can be obtained for different

magnitude of dc offsets. The required bandwidth is determined for each. For dc offset value ranging from 1% to

8%, the required bandwidth is determined and shown in Fig. 4.

It can be observed that as the dc offset magnitude increases, the required bandwidth gets reduced considerably.

Normally, the dc offsets due to sensors, ADCs etc are compensated. But drift in offset value happens over time and

that results in dc offsets in the input to SRF-PLL. This drift will not result in very high dc offset. Thus, practically,

the expected dc offset may be set to be about 2%. In that case, the SRF-PLL bandwidth will have to be 20.4Hz

to ensure that unit vectors conform to grid interconnection standard.

The ripple in the estimated phase θe given by (21) does not result in steady-state phase error. However, there will

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Unit

vector

dc

offset

(%)

0

0.5

1

1.5

Bandwidth(Hz)

0 50 100 150 200 250 300

u10(%)

u20(%)

limit(%)

(a)

Unit

vector

dc

offset

(%)

0

0.5

1

1.5

Bandwidth (Hz)

0 50 100 150 200 250 300

u10(%)

u20(%)

limit(%)

(b)

Unit

vector

dc

offset

(%)

0

0.5

1

1.5

Bandwidth (Hz)

0 50 100 150 200 250 300

u10(%)

u20(%)

limit(%)

(c)

Fig. 3: Unit vector dc offset (%) versus bandwidth (Hz) for (a) Combination-1 (b) Combination-2, and (c)

Combination-3. The input dc offset magnitude y = 2%.

be instantaneous phase error. For y = 2% and combination-3, the peak instantaneous phase error is plotted versus

SRF-PLL bandwidth in Fig. 5. It can be observed that for the design bandwidth of 20.4 Hz, the peak instantaneous

phase-error is about 0.5◦.

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Required

bandwidth

(Hz)

0

10

20

30

40

50

60

70

Magnitude of dc offset (%)

1 2 3 4 5 6 7 8

Fig. 4: Required SRF-PLL bandwidth as a function of dc offset magnitude in the input.

Amplitude

of

phase

error

(deg.)

0

0.5

1

1.5

2

Bandwidth (Hz)

0 50 100 150 200 250 300

Fig. 5: Amplitude of instantaneous phase error versus SRF-PLL bandwidth when y = 2% for combination-3.

V. ANALYSIS OF THE EFFECT OF PRE-FILTERS ON SRF-PLL

One approach to reject the dc offset in the input is by using pre-filters, which can be bandpass filter (BPF) or

highpass filter (HPF) [23], [28]. The pre-filters can be placed after the three-phase to two-phase transformation.

This structure will be obtained by changing the position of the switch ‘S’ in Fig. 2.

A. Effect of bandpass filter (BPF)

The transfer function of BPF that can be used is given by,

GBPF =2kω0s

s2 + 2kω0s+ ω20

(29)

The use of this is suggested in an EPLL structure in [23]. As per [23], k can be chosen to be k = 1√2= 0.707.

The term ω0 in (29) has to be equal to nominal grid frequency. ω0 = 2π50 rad/s in a 50Hz system.

For grid frequency equal to ω0, the magnitude and phase shift given by this filter will be 1 and 0 respectively.

Thus there will be no magnitude or phase error. However, when the grid frequency deviates from the nominal value

of ω0, there will be unwanted non-unity gain and phase shifts. This results in magnitude and phase errors. These are

tabulated in Table II for frequency deviations of upto 5 Hz. It can be observed that the phase error is significant.

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The addition of filters affects the transient response time of the SRF-PLL. This additional settling time due to

the filter is also shown in Table II.

TABLE II: Comparison of Performance of BPF and HPF Pre-filtering Stages versus the Proposed SRF-PLL Design

BPF HPF Proposed SRF-PLL Design

Additional step response settling time 22.5ms 125ms − ∗

Maximum magnitude error

(For ±5Hz variation) −0.096dB −0.053dB 0

Maximum steady phase error

(For ±5Hz variation) 8.5◦ 6.3◦ 0◦

Attenuation to

high frequency harmonics Yes No Yes#

∗SRF-PLL with pre-filters has an additional step response settling time due to the filter dynamics in addition to that of the basic SRF-PLL.#Selection of bandwidth for dc offset constraint meets the harmonic distortion criteria based on [8]

The advantage of using BPF is that there will be additional harmonic attenuation. However, the BPF has no

impact when the input contains unbalance.

B. Effect of highpass filter (HPF)

First-order high-pass filters (HPF) can be used in the pre-filtering blocks to remove the dc. The transfer function

of HPF is given by,

GHPF =s/ωc

1 + s/ωc(30)

The corner frequency ωc is chosen such that the fundamental grid frequency appears to be high enough for the

HPF so that the magnitude and phase errors are small. Normally, ωc is chosen to be one decade less than the grid

nominal frequency. That is,

ωc =ω010

(31)

HPF also has the limitation of magnitude and phase error for frequency deviations. These values for upto 5 Hz

frequency deviation are shown in Table II. It can be observed that HPF has relatively lesser magnitude and phase

error compared to BPF. However, the settling time is considerably large. Also, the HPF does not give any attenuation

to harmonics.

The phase error in Table II can be compared with the plot in Fig. 5. The peak instantaneous phase error at the

designed bandwidth is 0.5◦ which is considerably smaller than that due to pre-filters. Also, for SRF-PLL without

pre-filters, the phase error does not change with the frequency deviation of the grid voltage. The SRF-PLL will not

have any phase error if the dc offsets are absent. However, the pre-filters will always have a phase error during

frequency deviations, irrespective of the presence of dc offsets.

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Thus the proposed design method for SRF-PLL satisfies grid interconnection standard and also does not result

in significant phase error when the dc offsets are present. The SRF-PLL with pre-filter needs relatively more

computation time/resources in digital controller.

VI. EXPERIMENTAL RESULTS

The performance of the SRF-PLL when the input contains dc offsets is verified experimentally. The PLL is

implemented in Altera Cyclone FPGA based digital controller board. The results are taken for a dc offset magnitude

of y = 2%.

A. Verification of analytical expressions for dc offset calculation

The analytical expressions derived in this paper for the unit vector dc offset calculation are verified using

simulation and experimental results. The input contains 2% offset with combination-2 as indicated in Table I.

The dc offset magnitude in unit vector u1 as defined in (25) is used for the verification. The dc offset amount is

verified for a bandwidth of 10 Hz to 100 Hz in steps of 10 Hz. The results of analytical expressions, simulation

and experimental result is provided in Table III. The SRF-PLL simulation is performed in MATLAB Simulink.

TABLE III: Comparison of unit vector dc offset value computed from analytical expressions with simulation and

experimental resultsDC Offset in u1

SRF-PLL Bandwidth (Hz) Analytical (%) Simulation (%) Experimental (%)

10 0.248 0.248 0.269

20 0.490 0.490 0.520

30 0.688 0.688 0.739

40 0.828 0.829 0.809

50 0.920 0.920 0.849

60 0.976 0.976 0.886

70 1.007 1.010 0.963

80 1.023 1.020 0.982

90 1.029 1.030 0.944

100 1.029 1.030 0.962

There is some deviation between experimental and analytical results. The error is mainly due to the limitation

in measuring very small dc offset from the oscilloscope data. The limitation is due to quantization errors from the

digital controller as well as from the data acquisition system of the oscilloscope. This difficulty is absent in the

simulation model and hence the results from small-signal state-space model have excellent match with simulation

results with an absolute maximum error between the analytical results and simulation results of 3.0× 10−5 p.u.

B. Steady-state and transient performance of the SRF-PLL with proposed design

The steady-state performance is compared with a high bandwidth design of SRF-PLL. This is done to show that

the ripple in the estimated frequency becomes negligible in the proposed design case.

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The input voltage va, in-phase unit vector (usin = −u1) and the estimated frequency are shown in Fig. 6(a)

for a higher design bandwidth of 200 Hz. The ripple in the estimated frequency can be observed. For the same

conditions, the waveforms when design bandwidth equals 20.4 Hz is shown in Fig. 6(b). The ripple in estimated

frequency can be observed to be negligible.

20ms/div

Va

ωest

uin_ph

(5V/div)

In-phase unit vector (1pu/div)

Va

ωest(2π20rad/s/div)

(a)

20ms/div

Va

ωest

uin_ph

(5V/div)Va

In-phase unit vector (1pu/div)

ωest(2π20rad/s/div)

(b)Fig. 6: Estimated frequency, input voltage va and in-phase unit vector uinph = −u1 for SRF-PLL with 2% dc

offset in the input. (a) Design bandwidth = 200 Hz, (b) Design bandwidth = 20.4 Hz.

Enable(En)En

ωest(2π20rad/s/div)(5V/div)Va

Va

ωest

uin_ph

In-phase unit vector (1pu/div)

20ms/div

Fig. 7: Estimated frequency, input voltage va and in-phase unit vector for SRF-PLL with 2% dc offset in the input.

A 60◦ phase shift is given to the three-phase input when the enable signal goes high.

In order to check the transient response of the SRF-PLL at the design bandwidth of 20.4Hz, a phase shift of

60◦ was introduced in all the three-phases. This causes a temporary error in frequency estimation. Fig. 7 shows

the result. When the enable signal (En) is made high, the phase shift is introduced which can be observed in va.

The error in frequency estimation is observed to die out within 30 ms which is 1.5 fundamental cycle in 50Hz

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system. The theoretically expected settling time is 4/ωbw. For ωbw = 2π20.4 Hz, the settling time is 31.2 ms

which matches with the experimentally observed settling time.

VII. CONCLUSION

SRF-PLL is a simple to implement PLL that is widely used in grid-connected power converters. The estimated

frequency and phase of this PLL will have sinusoidal ripple errors when the input contains unbalance, harmonics

and dc offsets. It is known in literature that reduction in SRF-PLL bandwidth can give better performance. In this

paper, a novel quantitative design guideline is proposed to select the SRF-PLL design parameters when the input

contains dc offsets.

A small-signal state-space model is derived for the SRF-PLL. It is shown that presence of dc offsets in the

input results in dc offsets in the unit vectors produced by the SRF-PLL in addition to the ripple error in estimated

frequency. The presence of dc offsets in unit vectors is undesirable as it can result in dc current injection to the

grid. The amount of dc offset in unit vectors can be quantified accurately using the derived state-space model. The

amount of dc offsets is related to the SRF-PLL design bandwidth which leads to the proposed design method of the

SRF-PLL. In this method, for a known worst-case dc offset amount in the input, SRF-PLL bandwidth is computed

which results in unit vector dc offset of less than 0.5%. This limit is from the grid interconnection standard IEEE

1547-2003. For the given worst-case input dc offset, the proposed design achieves fastest response while meeting

the grid interconnection standard. This design is compared with the performance of SRF-PLL with conventional

dc cancelling pre-filters. When there is upto 10% frequency deviation in the input, it is shown that there will be

significant phase error of > 6◦ with the use of common pre-filters. The proposed SRF-PLL design procedure has

ten times lower phase error and faster overall settling time.

The proposed design is verified experimentally. The analytical expressions computing the dc offset in the unit

vector are verified using simulation and experimental results. The SRF-PLL implementation takes considerably less

computation time compared to advanced PLLs. The proposed design method is especially useful when low and

medium performance digital controllers are used in cost sensitive applications.

APPENDIX A

DERIVATION OF SMALL-SIGNAL STATE-SPACE MODEL FOR SRF-PLL

The signals in state-equations are defined as a sum of steady operating large signal and a small signal disturbance

in (11). The equations for the large signals is given in (12) and (13).

The terms p1 and p2 in (8) are also expressed as the sum of an operating value and a perturbation. The product

of perturbation terms is ignored in the following expressions as they are negligible compared to the other terms.

p1 =− kp ˙vα − kpvβ0ωe − kpω0vβ − kivα − kivα0 − kp(vα0 + ω0vβ0)

=p1 + p10

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Note that the term −kp(vα0 + ω0vβ0) in the expression for p1 above equals zero. This can be verified from the

definitions of vα0, vβ0 given in (12) and using (13) as,

−kp(vα0 + ω0vβ0) = −kp(Vmω0 cos θ − ω0Vm cos θ) = 0 (A.32)

Thus the steady and perturbation parts in p1 are,

p10 =− kivα0

p1 =− kp ˙vα − kpvβ0ωe − kpω0vβ − kivα (A.33)

Similarly,

p2 =− kp ˙vβ + kpω0vα + kpvα0ωe − kivβ − kivβ0 + kp(−vβ0 + ω0vα0)

=p2 + p20

The term kp(−vβ0 + ω0vα0) can also be verified to be zero as done in (A.32). So,

p20 =− kivβ0

p2 =− kp ˙vβ + kpω0vα + kpvα0ωe − kivβ (A.34)

The small signal derivative of ωe is equal to the derivative of the state variable ωe. That is,

dωedt

=d(ω0 + ωe)

dt=dωedt

(A.35)

Thus using (8) and (A.35),

˙ωe = (p10 + p1) cos(θ0 + θe) + (p20 + p2) sin(θ0 + θe) (A.36)

The sine and cosine terms in (A.36) are expanded assuming θe to be small so that cos θe ≈ 1 and sin θe ≈ θe.Thus,

˙ωe = (p10 + p1)(cos θ0 − sin θ0 θe) + (p20 + p2)(sin θ0 + cos θ0 θe) (A.37)

The normal operating point term (or the large signal term) in the right hand side of (A.37) must go to zero as

the left hand side has only the derivative of the small signal perturbation term ωe. The large signal term in (A.37)

is given by

p10 cos θ0 + p20 sin θ0 = −ki(vα0 cos θ0 + vβ0 sin θ0) (A.38)

The term above is nothing but vd scaled by −ki. The normal operating value of vd is zero. This is ensured by

the PI controller used in the SRF-PLL. Thus the expression derived for ˙ωe in (A.36) is consistent from both large

signal and small signal perspective.

Extracting all the significant small signal terms in (A.37), the following expression can be derived.

˙ωe = p1 cos θ0 + p2 sin θ0 + (−p10 sin θ0 + p20 cos θ0)θe (A.39)

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Substituting for p1, p2, p10 and p20 using (A.33) and (A.34), and using the expressions for vα0, vβ0 from (12),

the derivative of ωe is obtained as,

˙ωe =kpVm cos(θ − θ0)ωe + kiVm cos(θ − θ0)θe + (kpω0 sin θ0 − ki cos θ0)vα

+ (−kpω0 cos θ0 − ki sin θ0)vβ − (kp cos θ0) ˙vα − (kp sin θ0) ˙vβ (A.40)

The small signal derivative of θe will be˙θe = ωe (A.41)

Equations (A.40) and (A.41) form the state equations for the SRF-PLL in small-signal around an operating point.

These can be represented in the matrix form as follows,˙ωe˙θe

=

kpVm cos(θ − θ0) kiVm cos(θ − θ0)

1 0

ωeθe

+

kpω0 sin θ0 − ki cos θ0 −kpω0 cos θ0 − ki sin θ0

0 0

vαvβ

+

−kp cos θ0 −kp sin θ0

0 0

˙vα

˙vβ

(A.42)

The characteristic matrix for the system is,

A =

kpVm cos(θ − θ0) kiVm cos(θ − θ0)

1 0

(A.43)

When the SRF-PLL is operating in synchronization, the PI controller ensures that vd = 0. The expression for vd

using (3) and (12) is given by

vd = Vm sin θ cos θ0 − Vm cos θ sin θ0 = Vm sin(θ − θ0) (A.44)

This value is zero in the steady operating point. Hence, θ − θ0 = nπ.

It can be verified that for odd n, the system poles will be stable. For even n, the system is unstable. Thus, in

normal operating conditions, the estimated phase and the grid phase angle will have a phase difference of π radians.

The characteristic equation of the system for stable conditions is

λ2 + kpVmλ+ kiVm = 0 (A.45)

The system eigen values are given by

λ1,2 = −0.5kpVm ± 0.5�

(kpVm)2 − 4kiVm (A.46)

The final state equations in matrix form are given in (14) by using the condition θ − θ0 = π in (A.42).

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APPENDIX B

OFFSET IN UNIT VECTORS AS A FUNCTION OF SRF-PLL BANDWIDTH

The PI controller parameters kp and ki in the SRF-PLL can be related to the design bandwidth ωbw as explained

in [6]. The design equations in [6] can be rewritten as,

kp =ωbwVm

(B.47)

ki = kpTsω2bw (B.48)

In (B.48), parameter Ts is the sampling time used in the digital implementation of the SRF-PLL. In (B.47), the

nominal sensed grid voltage peak is Vm.

The dc offsets in unit vectors u10 and u20 are given in (26) and (28) respectively. These offsets depend on the

parameters a, b, φ0, m and mθ. All these parameters were derived as a function of kp and ki. Now using (B.47)

and (B.48), they can be rewritten as a function of ωbw as follows.

a = ωbwω0vα0p − ω3bwTsvβ0p (B.49)

b = −ω3bwTsvα0p − ωbwω0vβ0p (B.50)

m =

����1

−ω20 + jωbwω0 + ω

3bwTs

���� (B.51)

mθ = − tan−1

�ω0

ω2bwTs − ω2

0/ωbw

�(B.52)

φ0 = tan−1

�ω2bwTsvα0p + ω0vβ0pω2bwTsvβ0p − ω0vα0p

�(B.53)

Note that vα0p and vβ0p are the dc offsets in vα and vβ as a fraction of nominal grid voltage peak Vm. That is

vα0p =vα0Vm

vβ0p =vβ0Vm

(B.54)

Substituting (B.49)–(B.54) in (26) and (28), the dc offsets in the unit vectors can be written completely as a function

of SRF-PLL design bandwidth.

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