1. Define the following terms. a. N -Doping (N -Material...

Design Automation Test #1 Spring 2000 Closed Book of 3

1. Define the following terms. a. N-Doping (N-Material) b. P-Doping (P-Material) c. PN junction d. MOSFET

2. Draw the transistor diagram of a two-input COS NAND gate.


3. Draw the layout of a two-Input CMOS NAND Gate.

4. Show the vertical constraint graph for the following channel. 3 2 0 1 3 2 1 6 3 1 6 4 3 2 6 5 3 6 5 0


5. Show the routing for the following channel. Use the left-edge algorithm. You may not need to use all the rows.

6. We want to partition the following circuit into two equally sized pieces. The initial partition is {1,2,3} {4,5,6} For each gate, show the gain. Show the gain for each pair of gates. Remember that the gain for a gate is the reduction in the total nets that will be cut if we move the gate from one set to the other. The gain for a pair is the reduction in total nets that are cut when we swap the pair of gates.

Gate Gain Pair Gain

1 1,4 2 1,5 3 1,6 4 2,4 5 2,5 6 2,6

3,4 3,5

3,6

1

2

3

4

5 6

6 1 4 0 08 0 2 4 5 5 0 10 3 0 3

0 7 0 07 1 4 8 0 9 6 2 0 5 9 10

Spring 2000 VLSI Design Automation Page 1 of 1 Test Number 2

1. What is the primary advantage that the Fiduccia-Mattheyses partitioning algorithm has over the Kernigan-Lin Algorithm. Fiduccia-Mattheyses has a problem that is not encountered by Kernigan-Lin. What is it?


2. Describe the process of Simulated Annealing. In this description, answer the following questions. What is a Neighbor function? What is a cooling schedule? What is a cost function? Why is a cooling schedule needed?


3. Define the term “Standard Cell Layout.” When using min-cut to partition a circuit with 128 gates into four rows, how many times must min-cut be used. What is the purpose of each cut?


4. In the following routing problem, it is necessary to route from A to B using the Lee algorithm. Show the vertices that would be visited by the Lee algorithm, and the paths and partial paths that would be created. Place a number in each vertex in the order it is visited by the Lee algorithm.

A

B


5. Redo the previous problem using line routing. Show all test lines, and the final route.

A

B

Design Automation Apr 27, 2000 Test 3

Page 1 of 1

1. Break the following routing area into channels. Number each channel. Show the order in which the channels would be routed.


Page 2 of 2

2. Show the channel connectivity graph for this system of channels, and show how the channel connectivity graph would be used to do the global-routing for nets A, B, and C.

A

A

B

B

C C


Page 3 of 3

3. Route the following channel using the left-edge algorithm.

1 5 9 0 6 0 6 2 7 0 10 8 10

4 6 0 5 1 2 7 9 3 8 10 4 3


Page 4 of 4

4. Route the following channel using the dog-leg (left-edge) algorithm.

1 5 7 9 7 14

8 13

2 3 6 11

12

6 4 4 10

2

2 0 8 1

4 13

14

7 5 11

4 10

12

12

6 12

3 9 1


Page 5 of 5

5. Give the steps for the greedy channel router, and explain what each does.


Page 6 of 6

6. Explain the difference between the following timing models, Zero-Delay, Unit-Delay, Multi-Delay.

VLSI Design Automation Test 1 100 Points 1 hour 15 min Open book/Open notes 5 Pages

Page 1

(Each Question is Worth 20 Points.) 1. Draw the layout of a 2-input NOR gate. This layout should consist of a collection of

rectangles using P and N diffusion, polysilicon, and metal. Identify the locations of the transistors. Don’t worry about proper spacing.


Page 2

2. Draw the transistor diagram for an AOI32 gate. This gate performs the same function as the following gate diagram.

ABC

D

E

Q


Page 3

3. Professor Gooms of the University of Florida has created the following layout as part of his new “wonder computer.” One of his students politely pointed out that he couldn’t put P and N diffusion right next to one another as he has done. Why not?

P-Diffusion N-Diffusion

Metal


Page 4

4. The following is an outline of the Kernigan-Lin MinCut algorithm. At various places in this algorithm you will find a blank with a number preceding it. Explain what is missing at each such point.

Repeat until (1)_______________. Repeat until all gates are locked For each unlocked pair of gates (2)______________ the gates. Compute (3)_______________. Restore the initial state. End For From all pairs examined in the preceding loop Lock and (4)_____________ the pair that gives (5)_________________. End Repeat From all locked pairs, select a sequence of pairs starting with (6)________________ and ending with (7)_________________. and (8)_____________________ each pair. Compute (9)___________________. If (10)________________________ then Make all changes permanent. Unlock all pairs of gates. End Repeat (1)_____________________________________________________ (2)_____________________________________________________ (3)_____________________________________________________ (4)_____________________________________________________ (5)_____________________________________________________ (6)_____________________________________________________ (7)_____________________________________________________ (8)_____________________________________________________ (9)_____________________________________________________ (10)____________________________________________________


Page 5

5. Describe the procedure used in force directed placement, and how it differs from simulated annealing.


Page 1

(Each Question is Worth 20 Points.) 1. Identify the channels in the following floor plan. Number the channels starting with 1,

and indicate the order in which the channels must be routed.


Page 2

2. Show the Vertical Constraint Graph for the following channel. Use the vertical constraint graph to route the channel. Show the position of the vertical and horizontal segments for each net. Use the left-edge algorithm.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

2

1

0

3

4

0

2

5

0

0

5

6

0

4

7

1 0

4 3

0

1

6

0

7

0

4

7

1


Page 3

3. Suppose that the LEE routuer is used to route the connection for Net A. Starting with the lower connection, show all vertices visited by the LEE algorithm. Write numbers in the vertices to show when each vertex was visited. The number should correspond to the distance from the starting vertex. Draw lines between the vertices to show how the LEE algorithm moves from one vertex to the next. The black circles represent occupied cells, which cannot be visited by the LEE router.

A

A


Page 4

4. Show the paths created by the river router for the following routing problem. Circle the corners that can be flipped to minimize net-length (if any).

1

1

2

23 3

4 4

5

5

7

7

6

6


Page 5

5. Show how the following Single Row Routing Problem can be routed.

1 12 23 34 45 56 67 7

VLSI Design Automation Test 3 100 Points 1 hour 15 min. Open book/Open notes 5 Pages

Page 1

(Each Question is Worth 20 Points.) 1. Route the following Clock Points, minimizing clock-skew between points.

Clock


Page 2

2. Show the Constraint Graph for horizontal grid-based compaction. The minimum distance between any two blocks is equal to twice the number of connections in the space between them, or one-unit, which ever is larger. Make a rough drawing of the compacted circuit. (Just the blocks, omit the connections.)

A

B

C

D

E

F

G

H

J

K

L

M


Page 3

3. For the following circuit, find the via candidates and the clusters. Nets 1, 2, and 3 are too close together to place a via between them. The same applies to all nets that are as close together as 1, 2, and 3. Make a tentative layer assignment, and find the cluster graph. If your tentative layer assignment is not minimal, minimize it (in terms of the number of vias.)

1 2 3

123

4

45 6 7

567

8 9 10

8910

11 12

11

12


Page 4

4. Show how the following channel can be routed using Over-The-Cell techniques.

1 1 22 3 34 4

5

5 77 66

1 22 345 77 66

0

0 00


Page 5

5. Levelize the following circuit. Show level numbers for each net and each gate. List the gates in the order in which they would be simulated using Levelized Compiled Code simulation.

A

B

CDE

FG

Q

I1

I2

I3

I4I5

X

Y

CDE

FG

I1

I2

I4I5 YG1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

1. Describe Fiduccia-Mattheyses partitioning and explain how it differs from Kernigan-Lin.

2. Describe partitioning by Simulated Annealing. How does it differ from FM and KL. 3. Describe the two types of standard-cell placement, Min-Cut, and Simulated

Annealing. Which would you prefer to use? 4. Given the following routing problem, show the vertices that would be visited. Place a

number in each vertex in the order visited by the Lee algorithm. 5. Describe how line routing of the previous example would work.

A

B

1. Break the following routing area into channels. Number each channel. Show the order in which the channels would be routed. Show the channel connectivity graph for this system of channels.

2. Give an outline of the steps used in global routing. 3. Route the following channel using the left-edge algorithm.

3,2,1,6,0,9,8,1,9,2 5,4,3,7,4,9,6,7,5,8

4. Route the following channel using the dog-leg (left-edge) algorithm. 1,7,6,5,3,4,5,5,2 2,5,0,6,1,7,6,4,1

5. Give the steps for the greedy channel router, and explain what each does. 6. Explain the difference between the following timing models, Zero-Delay, Unit-Delay,

Multi-Delay.

1. Define the following terms. a. N -Doping (N -Material...

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