1 COMP541 Sequential Logic Timing Montek Singh Sep 30, 2015.
1 COMP541 Input Devices: Keyboards, Mice and Joysticks Montek Singh Nov 13, 2015.
Transcript of 1 COMP541 Input Devices: Keyboards, Mice and Joysticks Montek Singh Nov 13, 2015.
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COMP541
Input Devices: Keyboards, Mice and Joysticks
Montek Singh
Nov 13, 2015
Keyboard Interface
USB keyboard plugs into the USB port on Nexys 4 boards
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USB to PS/2 emulation Host controller on Nexys boards
talks to USB keyboard on one sidespeaks PS/2 protocol to the FPGA on the other side
PS/2 used to be the dominant keyboard protocol
PS/2 = a synchronous serial protocolWhat does that mean?Each symbol is transmitted bit-by-bit
8 data bits + 3 control bitssynchronized to the keyboard’s clock (slow)
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Physical Interface Two lines
Clock (15-20KHz)DataNormally high, asserted
low Read:
pg. 10 of Nexys 4 manual
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Protocol Bidirectional
Kybd-to-host and host-to-kybd on same wiresCAPS LOCK light for example
Assert lowTo send, keyboard starts clocking
sends successive bit on positive edge of clockhost reads bits on negative edges of clock
For your lab:You shouldn’t need to send anything to keyboard
Protocol 11 bits
a start bit: always 08 bits of data
lsb firstone parity bit (odd)a stop bit: always 1
Clocked by keyboardValue should be latched by FPGA on neg edge of
keyboard clock
6Illustration from http://www.beyondlogic.org/keyboard/keybrd.htm
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What is Sent ASCII is not sent! Scan codes for keys
Most keys have an 8-bit (single byte) scancodeSome have two bytesA few have even more!Most (not all, be careful!) keyboards use these
scancodes:
Illustration from Nexys 3 manual
Our keyboards have slightly different scan codes! Check before using!
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Scan Codes Normally translated by software
You remap your keys, for example Software takes care of
Shift, caps lock, control
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Some Scan Codes Long Two code sequence common
Some special keys use even more……have a look at Break key!
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Even More Complicated Scan code generated when you press And when you release
Extra byte: F0 followed by key scan codeExample:
Space pressed, 29 sentSpace released, F0 29 sent
Resources Information
http://www.beyondlogic.org/keyboard/keybrd.htm
Scan codeshttp://www.barcodeman.com/altek/mule/scandoc.php
Available on the class website:my Verilog for keyboard
keyboard.sv: keyboard controller hardwarekeyboard_test.sv: demo with keyboard and 7-seg display
– displays the scan code of the last event from keyboard
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My Verilog Have Verilog for keyboard
a test/demo which displays data from keyboard onto 7-segment display
have tested it with the FPGA kit; seems to work fine
To use:You will memory-map the character code register
give the keyboard a memory address so the CPU can read it using lw instructions
Handle presses and releases appropriately in softwareEither: Check for a key release before reading a new key
pressOR: Delaying next key read (by, say, 1/4th sec)
– gives you automatic “key repeat” feature!
Mice
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Mouse Very similar interface (clk & data)
But: 3 words sent w/ mouse movement or button press
Readpp. 12-13 of Nexys 4 manual
Verilog I can guide you to modify keyboard.v to read 3 bytes
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Movement Movement is relative
XS, YS are sign (+ is up/right)XY, YY are overflow (too fast)L, R are buttons
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Scroll Wheel, etc. Extensions to original 2 button PS/2 mouse
See http://www.computer-engineering.org/ps2mouse/
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Joystick
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Joystick module 2 axes: x and y
10-bit position values On-board microprocessor
handles debouncingcommunicates with host
Info on class website reference manualVerilog code
demo: feeds joystick output to the 7-seg display
you will modify to feed the output into your memory-mapped I/O unit instead
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Accelerometer
Nexys 4 boards have built-in accelerometer
We are working on a Verilog module for it…
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Keypad
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Keypad module 4x4 keypad
0-9, A-Fone hex character input
Simple interface4-bit row, 4-bit columna ‘0’ means pressed
Info on class website reference manualVerilog code
demo: feeds keypad output to the 7-seg display
you will modify to feed the output into your memory-mapped I/O unit instead
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Stereo Audio Amplifier
Nexys 4 has mono amplifier built-in, but you can also attach a stereo module (read on…)
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Amplifier module Stereo output
headphone jack compatible Very very low-level…!
expects analog waveform oninput!
your design on FPGA will haveto generate an analog valueby rapidly toggling between 0 and 1e.g., 60% of the time ‘1’ value will approximate an analog
value of 0.60V (if range is 0-1V)
Verilog codeWe are working on it …