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CMOS Digital System Design

MOS Transistor DC Operation

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Threshold Voltage Vt

• Vgs

< Vt: nMOS channel is cut off

• Vt < V

gs: nMOS channel conducts

• Vgs

< Vt: pMOS channel conducts

• Vt < V

gs: pMOS channel is cut off

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Enhancement Mode Transistors Depletion Mode Transistors

• Enhancement mode:channel is cut off when V

gs = 0

• Depletion mode:channel conducts when V

gs = 0

• Most CMOS ICs use enhancement-mode transistors.

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n-MOS Channel Layers, Page 1

• When Vgs

= 0,

drain-to-substrate is reverse-biased pn junction.

• When Vgs

> 0,

positive electric field in channel under gate:– repels holes– attracts electrons

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n-MOS Channel Layers, Page 2

• When Vgs

<< Vt:

–Mobile positive holes in p-type channel in substrate are evenly distributed.

–Called accummulation layer

• When Vt < V

gs:

–Holes are repelled, causing a depletion region under the gate.

–Called depletion layer

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n-MOS Channel Layers, Page 3

• When Vt << V

gs:

–Electrons are attracted, causing a conductive layer under the gate.

–Called inversion layer

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n-MOS Operating Regions, Page 1

• When Vds

= 0:

–Depletion and inversion layers uniform depth along length of channel

• When Vds

> 0:

–Depletion and inversion layers same depth at source end of channel as for V

ds = 0

– Inversion layer tapers off linearly toward drain end

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n-MOS Operating Regions, Page 2

• When Vds

< Vgs

– Vt:

– Inversion layer becomes deeper as Vgs

increases

– Ids

depends on both Vgs

and Vds

.

–Called linear region.

–Also called resistive region.

–Also called nonsaturated region.

–Also called unsaturated region.

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n-MOS Operating Regions, Page 3

• When Vds

> Vgs

– Vt:

–Vgd

< Vt.

– Inversion layer pinched-off: no longer reaches drain from source end of channel

–Electrons instead injected into depletion layer, then accelerated toward drain

– Ids

depends only on Vgs

, independent of Vds

.

–Called saturated region

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Body Effect

• When have series-connected nMOS devices, only the bottom one has source connected to GND.

• Others have Vsb

= (Vsource

– Vsubstrate

) > 0

• For those, have greater gate-channel voltage difference

• Increase in Vt.

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Cutoff Region DC Equation

• For Vgs

<= Vt:

• Ids

= 0

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Nonsaturation Region DC Equation

• For 0 < Vds

< Vgs

– Vt:

• Ids

= Beta((Vgs

– Vt)V

ds - V

ds**2 / 2)

• Beta = MOS transistor gain factor

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Saturation Region DC Equation

• For 0 < Vgs

- Vt < V

ds:

• Ids

= Beta(Vgs

– Vt)**2 / 2

• Beta = MOS transistor gain factor= ( (mu)(epsilon) / t

ox )( W / L )

• mu = channel carrier mobility

• epsilon = gate insulator permittivity (SiO2)

• tox

= gate insulator thickness

• W / L = channel dimensions

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LOW Noise Margin

• VIL = LOW input voltage

• NML = LOW noise margin

• Unity gain point, slope = -1

– VIL = 2.3 volts

– NML = 2.3 volts

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HIGH Noise Margin

• VIH

= HIGH input voltage

• NMH = HIGH noise margin

• Unity gain point, slope = -1

– VIH

= 3.3 volts

– NMH = 1.7 volts

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Differential Amplifier, Page 1

• Pair of nMOS transistors,each with a pull-up resistor

• Sources connectedthrough constant-current source to ground

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Differential Amplifier, Page 2

• If Vin1

and Vin2

change equally from Vquiescent

,

Vout1

and Vout2

stay the same.

• If only Vin1

changes:

– current changes one way in resistor 1 and the other way in resistor 2

– So Vout1

changes one way and Vout2

changes

the other.

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Differential Amplifier, Page 3

• Common Mode Gain low

• Differential Gain high

• CMRR = Common Mode Rejection Ratio= Differential Gain/Common Mode

Gain

• Good for rejecting common mode noiseon input pins

• Used in RAM sense amplifiers

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Current Mirror

• Pair of nMOS transistors with gates tied together

• Tie drain of side device to its gateto put it in saturation

• Feed constant current in side transistor

• Identical current will flow in other transistor, since they are in saturation and V

gs1 = V

gs2.

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Tri-State Driver

• Inverter followed by a pass gate

• For same size n- and p-devices, half the speed of inverter alone

• Can omit connection between inverter devices

• Used in bus drivers and latches

• Can be drawn as one gate

• (“Tri-State” is a registered trademark of National Semiconductor Corporation.)

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Junctions and Diodes

• At pn junction, junction diode formed

• At metal-semiconductor junction,creates either:– Ohmic contact, or– Schottky diode (used extensively for high-frequency,

low-noise mixer and switching circuits).– Only ohmic in most CMOS processes

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Diode DC Equation

• I = current in a diode= A

d I

s(exp(qV/kmt) – 1), where:

• Ad = area of the diode

• Is = the saturation current/unit area

• q = the charge of an electron

• k = Boltzmann's constant

• t = temperature

• m = approx. 2.0 for pn-junction diodes, and = approx. 1.2 for Schottky diodes

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BiCMOS Drivers

• With extra processing steps added to a CMOS process, can build useful NPN transistors

• NPN has high current gain

• Can improve output drive of CMOS inverter