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64-Bit AND Gate

Phong NguyenSteve Turner

Harpreet DhillonMahrang Saeed

Advisor: Dave Parent5/8/06

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Agenda

• Abstract• Introduction

– What we learned– What it’s used for– Theory

• Project Summary• Project Details• Results• Time schedule• Conclusions

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Abstract

• Designed a 64 bit AND gate that operates at 400 MHz and occupies an area of 807x320um2.

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Introduction

• By doing this project, we learned how to do a full custom IC design.

• 64-bit AND gate is useful in doing 64-bit processing.

A/32 B/32 Y/1

0 0 0

0 1 0

1 0 0

1 1 1

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Project Summary

• 400 Mhz 64 bit and gate

• 3.65 % error between worst case and best case input vectors

• Tplh equals 2.1ns and Tphl equals 1.57ns• Power = 2.35 mW @ 400 MHz• Power = 1.17 mW @ 200 MHz

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Longest Path CalculationsWn Wp Cint Cload Cint+Cg

8bitcell

nand2 3.00E-04 3.00E-04 5.00E-15 1.51E-14 2.01E-14

nor2 3.00E-04 6.00E-04 5.00E-15 7.55E-15 1.26E-14

nand2 2.25E-04 2.25E-04 5.00E-15 1.01E-14 1.51E-14

last8bitcell

nor2 1.95E-04 4.05E-04 5.00E-15 1.08E-14 1.58E-14

nand2 3.15E-04 3.30E-04 5.00E-15 2.27E-14 2.77E-14

nor2 3.75E-04 9.75E-04 5.00E-15 3.00E-14 3.50E-14

dff

NAND2 (Slave) 8.10E-04 8.10E-04 5.00E-15 1.01E-14 1.51E-14

Driver Mux (Slave) 9.45E-04 5.40E-04 5.00E-15 2.69E-14 3.19E-14

NAND2 (Master) 7.50E-04 8.40E-04 5.00E-15 2.49E-14 2.99E-14

Driver Mux (Master) 7.80E-04 4.35E+00 5.00E-15 2.66E-14 3.16E-14

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Schematic with worst case path

blackcell: flip-flop x 64

redcell: 8bit cell x 8

bluecell: last 8bit cell

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Final Layout

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Verification

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NCVerilog

only time when all bits are 1, output is 1

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Transient Simulation tphl

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Transient Simulation tplh

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Time Schedule

Verifying Timing

Layout

Post Extracted Timing

Verifying Logic

Time

2 Weeks

1 Week

2 Weeks

1 Week

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Lessons Learned

• Before starting layout spend time on making a floor plan

• Using Cell based design makes it easy & It reduces debug time

• Time management is the main key to complete any project

• Also pay attention to best case delay as well• See professor more often, keep updated

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Summary

• It can be used for 64 Bit Processing

• Max. Frequency - 400 Mhz

• Error between worst and best case input vectors is only 3.65 %

• Tplh equals 2.1ns and Tphl equals 1.57ns• Power = 2.35 mW @ 400 MHz• It can be used in a bigger project

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Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab

• Thanks to Professor Parent for his time & guidance