.1 1999©UCB CPSC 161 Lecture 6 Prof. L.N. Bhuyan bhuyan/cs161/index.html.
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Transcript of .1 1999©UCB CPSC 161 Lecture 6 Prof. L.N. Bhuyan bhuyan/cs161/index.html.
.1 1999©UCB
CPSC 161
Lecture 6
Prof. L.N. Bhuyan
http://www.cs.ucr.edu/~bhuyan/cs161/index.html
.2 1999©UCB
° Bits are just bits (no inherent meaning)— conventions define relationship between
bits and numbers
° Binary numbers (base 2)0000 0001 0010 0011 0100 0101 0110 0111
1000 1001...decimal: 0...2n-1
° Of course it gets more complicated:numbers are finite (overflow)fractions and real numbersnegative numberse.g., no MIPS subi instruction; addi can add a
negative number
° How do we represent negative numbers?i.e., which bit patterns will represent which
numbers?
Numbers
.3 1999©UCB
° Sign Magnitude: One's Complement Two's Complement000 = +0 000 = +0 000 = +0001 = +1 001 = +1 001 = +1010 = +2 010 = +2 010 = +2011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4101 = -1 101 = -2 101 = -3110 = -2 110 = -1 110 = -2111 = -3 111 = -0 111 = -1
° Issues: balance, number of zeros, ease of operations
° Which one is best? Why?
Possible Representations
.4 1999©UCB
° 32 bit signed numbers:
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten
maxint
minint
MIPS
.5 1999©UCB
° Negating a two's complement number: invert all
bits and add 1
• remember: “negate” and “invert” are quite different!
° Converting n bit numbers into numbers with more
than n bits:
• MIPS 16 bit immediate gets converted to 32 bits for
arithmetic
• copy the most significant bit (the sign bit) into the other
bits
0010 -> 0000 0010
1010 -> 1111 1010
• "sign extension" (lbu vs. lb)
Two's Complement Operations
.6 1999©UCB
° Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101
° Two's complement operations easy
• subtraction using addition of negative numbers 0111+ 1010
° Overflow (result too large for finite computer word):
• e.g., adding two n-bit numbers does not yield an n-bit number
0111+ 0001 note that overflow term is somewhat
misleading, 1000 it does not mean a carry “overflowed”
Addition & Subtraction
.7 1999©UCB
MIPS ALU Instructions
° Add, AddU, Sub, SubU, AddI, AddIU
• => 2’s complement adder/sub with overflow detection
° And, Or, AndI, OrI, Xor, Xori, Nor• => Logical AND, logical OR, XOR, nor
° SLTI, SLTIU (set less than)
• => 2’s complement adder with inverter, check sign bit of result
.8 1999©UCB
MIPS arithmetic instruction format
R-type:
I-Type:
31 25 20 15 5 0
op Rs Rt Rd funct
op Rs Rt Immed 16
Type op funct
ADDI 10 xx
ADDIU 11 xx
SLTI 12 xx
SLTIU 13 xx
ANDI 14 xx
ORI 15 xx
XORI 16 xx
LUI 17 xx
Type op funct
ADD 00 40
ADDU 00 41
SUB 00 42
SUBU 00 43
AND 00 44
OR 00 45
XOR 00 46
NOR 00 47
Type op funct
00 50
00 51
SLT 00 52
SLTU 00 53
.9 1999©UCB
Refined Requirements(1) Functional Specificationinputs: 2 x 32-bit operands A, B, 4-bit modeoutputs: 32-bit result S, 1-bit carry, 1 bit overflowoperations: add, addu, sub, subu, and, or, xor, nor, slt, sltU
(2) Block Diagram
ALUALUA B
movf
S
32 32
32
4c
.10 1999©UCB
Refined Diagram: bit-slice ALU
° Co = a.b + a.Cin + b.Cin
° Sum =
A B
M
S
32 32
32
4
Ovflw
ALU0
a0 b0m
cincos0
ALU0
a31 b31m
cincos31
.11 1999©UCB
Seven plus a MUX ?
A
B
1-bitFull
Adder
CarryOut
Mu
x
CarryIn
Result
° Design trick 2: take pieces you know (or can imagine) and try to put them together
° Design trick 3: solve part of the problem and extend
add
and
or
S-select
.12 1999©UCB
Additional operations° A - B = A + (– B)
• form two complement by invert and add one
A
B
1-bitFull
Adder
CarryOut
Mu
x
CarryIn
Result
add
and
or
S-selectinvert
Set-less-than? – left as an exercise
.13 1999©UCB
° No overflow when adding a positive and a negative number
° No overflow when signs are the same for subtraction
° Overflow occurs when the value affects the sign:• overflow when adding two positives yields a negative
• or, adding two negatives gives a positive
• or, subtract a negative from a positive and get a negative
• or, subtract a positive from a negative and get a positive
° Consider the operations A + B, and A – B• Can overflow occur if B is 0 ?
• Can overflow occur if A is 0 ?
Detecting Overflow
.14 1999©UCB
° An exception (interrupt) occurs• Control jumps to predefined address for
exception
• Interrupted address is saved for possible resumption
° Details based on software system / language
• example: flight control vs. homework assignment
° Don't always want to detect overflow— new MIPS instructions: addu,
addiu, subu
note: addiu still sign-extends!note: sltu, sltiu for unsigned comparisons
Effects of Overflow
.15 1999©UCB
Overflow Detection° Overflow: the result is too large (or too small) to represent
properly
• Example: - 8 < = 4-bit binary number <= 7
° When adding operands with different signs, overflow cannot occur!
° Overflow occurs when adding:
• 2 positive numbers and the sum is negative
• 2 negative numbers and the sum is positive
° On your own: Prove you can detect overflow by:
• Carry into MSB ° Carry out of MSB
0 1 1 1
0 0 1 1+
1 0 1 0
1
1 1 0 0
1 0 1 1+
0 1 1 1
110
7
3
1
– 6
–4
– 5
7
0
.16 1999©UCB
Overflow Detection Logic° Carry into MSB ° Carry out of MSB
• For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
A0
B0
1-bitALU
Result0
CarryIn0
CarryOut0
A1
B1
1-bitALU
Result1
CarryIn1
CarryOut1
A2
B2
1-bitALU
Result2
CarryIn2
A3
B3
1-bitALU
Result3
CarryIn3
CarryOut3
Overflow
X Y X XOR Y
0 0 0
0 1 1
1 0 1
1 1 0
.17 1999©UCB
But What about Performance?° Critical Path of n-bit Rippled-carry adder is n*CP
A0
B0
1-bitALU
Result0
CarryIn0
CarryOut0
A1
B1
1-bitALU
Result1
CarryIn1
CarryOut1
A2
B2
1-bitALU
Result2
CarryIn2
CarryOut2
A3
B3
1-bitALU
Result3
CarryIn3
CarryOut3
Design Trick: throw hardware at it
.18 1999©UCB
Carry Look Ahead (Design trick: peek)
A B C-out0 0 0 “kill”0 1 C-in “propagate”1 0 C-in “propagate”1 1 1 “generate”
A0
B1
SGP
P = A and BG = A xor B
A
B
SGP
A
B
SGP
A
B
SGP
Cin
C1 =G0 + C0 P0
C2 = G1 + G0 P1 + C0 P0 P1
C3 = G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P2
G
C4 = . . .
P
.19 1999©UCB
Cascaded Carry Look-ahead (16-bit): Abstraction
CLA
4-bitAdder
4-bitAdder
4-bitAdder
C1 =G0 + C0 P0
C2 = G1 + G0 P1 + C0 P0 P1
C3 = G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P2
GP
G0P0
C4 = . . .
C0
.20 1999©UCB
Additional MIPS ALU requirements
° Mult, MultU, Div, DivU (next lecture)=> Need 32-bit multiply and divide, signed and unsigned
° Sll, Srl, Sra (next lecture)=> Need left shift, right shift, right shift arithmetic by 0 to 31 bits
° Nor (leave as exercise to reader)=> logical NOR or use 2 steps: (A OR B) XOR 1111....1111
.21 1999©UCB
° More complicated than addition• accomplished via shifting and addition
° More time and more area
° Let's look at 3 versions based on a gradeschool algorithm
0010 (multiplicand)__x_1011 (multiplier)
° Negative numbers: convert and multiply• there are better techniques, we won’t look at
them
Multiplication
.22 1999©UCB
Multiplication: Implementation
DatapathControl
MultiplicandShift left
64 bits
64-bit ALU
ProductWrite
64 bits
Control test
MultiplierShift right
32 bits
32nd repetition?
1a. Add multiplicand to product and
place the result in Product register
Multiplier0 = 01. Test
Multiplier0
Start
Multiplier0 = 1
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
No: < 32 repetitions
Yes: 32 repetitions
Done
.23 1999©UCB
Final Version
Multiplicand
32 bits
32-bit ALU
ProductWrite
64 bits
Controltest
Shift right
32nd repetition?
Product0 = 01. Test
Product0
Start
Product0 = 1
3. Shift the Product register right 1 bit
No: < 32 repetitions
Yes: 32 repetitions
Done
What goes here?
•Multiplier starts in right half of product
.24 1999©UCB
Floating Point (a brief look)
° We need a way to represent• numbers with fractions, e.g., 3.1416
• very small numbers, e.g., .000000001
• very large numbers, e.g., 3.15576 109
° Representation:• sign, exponent, significand: (–1)sign significand
2exponent
• more bits for significand gives more accuracy
• more bits for exponent increases range
° IEEE 754 floating point standard: • single precision: 8 bit exponent, 23 bit significand
• double precision: 11 bit exponent, 52 bit significand
.25 1999©UCB
IEEE 754 floating-point standard
° Leading “1” bit of significand is implicit
° Exponent is “biased” to make sorting easier
• all 0s is smallest exponent all 1s is largest
• bias of 127 for single precision and 1023 for double precision
• summary: (–1)sign significand) 2exponent – bias
° Example:
• decimal: -.75 = - ( ½ + ¼ )
• binary: -.11 = -1.1 x 2-1
• floating point: exponent = 126 = 01111110
• IEEE single precision: 10111111010000000000000000000000
.26 1999©UCB
Floating point addition
°
Still normalized?
4. Round the significand to the appropriate
number of bits
YesOverflow or
underflow?
Start
No
Yes
Done
1. Compare the exponents of the two numbers.
Shift the smaller number to the right until its
exponent would match the larger exponent
2. Add the significands
3. Normalize the sum, either shifting right and
incrementing the exponent or shifting left
and decrementing the exponent
No Exception
Small ALU
Exponentdifference
Control
ExponentSign Fraction
Big ALU
ExponentSign Fraction
0 1 0 1 0 1
Shift right
0 1 0 1
Increment ordecrement
Shift left or right
Rounding hardware
ExponentSign Fraction
.27 1999©UCB
Floating Point Complexities
° Operations are more complicated (see text)
° In addition to overflow we can have “underflow”
° Accuracy can be a big problem
• IEEE 754 keeps two extra bits, guard and round
• four rounding modes
• positive divided by zero yields “infinity”
• zero divide by zero yields “not a number”
• other complexities
° Implementing the standard can be tricky
° Not using the standard can be even worse• see text for description of 80x86 and Pentium bug!
.28 1999©UCB
Chapter Three Summary
° Computer arithmetic is constrained by limited precision
° Bit patterns have no inherent meaning but standards do exist
• two’s complement
• IEEE 754 floating point
° Computer instructions determine “meaning” of the bit patterns
° Performance and accuracy are important so there are manycomplexities in real machines
° Algorithm choice is important and may lead to hardware optimizations for both space and time (e.g., multiplication)
° You may want to look back (Section 3.10 is great reading!)