1 1 vlsi introduction_overview

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TTM Institute of Technolo gy 1 IC LAYOUT ENGINEERING IC LAYOUT ENGINEERING Introduction to Microelectronics DAY ~ 2

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IC LAYOUT ENGINEERINGIC LAYOUT ENGINEERING

Introduction to

Microelectronics DAY ~ 2

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Evolution Of Microelectronics1947: Three scientists at Bell Telephone Laboratories, William Shockley, Walter Brattain, and John Bardeen demonstrate the first transistor:

•1955: Frosch and Derick at Bell Labs patent the diffusion furnace and develop SiO2 passivation layers for silicon transistors

•1955: Andrus and Bond at Bell Labs pattern oxide layers with photolithography

•1957: Lantrop and Nall (US Army) Pattern 200um leads to connect discrete transistors

1958: Last and Noyce develop the first step and repeat cameras for lithographic processing at Fairchild

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1957/1958: Jean Hoerni at Fairchild conceptualizes the first planer fabrication process for pn junctions using oxide barriers to protect pn junctions underneath. Allowed all of the circuitry required for transistor fabrication to be patterned on 1 side of the wafer.

1959: Fairchild’s Robert Noyce patents the monolithic IC that ties transistors, capacitors, resistors together using micro lithographically patterned aluminum leads deposited on top of Heorni’s protective coating.

•1960:Fairchild sells planer npn transistor device utilizing SiO2 barrier oxide for passivation that was patterned using a lithographic fabrication process

•1960: Fairchild demonstrates the first IC with 4 transistors and 5 resistors

•1961 GCA Corporation commercializes the step and repeat reduction device for optical lithography

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Evolution Of Microelectronics (cont.)

1960: First MOS transistor

•1960: Ian Ross of Bell Labs uses CVD to between the substrate and the collector to raise breakdown voltage and significantly increase the speed of the circuit

•1961: Hoerni demonstrates Silicon transistor that exceeds Ge switching speeds: Computers take off!!

•1963: San and Wanlass of Fairchild showed that p‐and n‐channel MOS transistors arranged into a complementary circuit (CMOS) drew close to zero power in standby mode

1964: Standard logic IC families introduced

•1964: General Microelectronics releases the first commercial MOS IC

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MOS FET Structure

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Evolution Of Microelectronics (cont.)

1965: Fairchild’s Director Gordon Moore introduces Moore’s law which accurately predicts the exponential increase of transistor density in an IC and provides a guide for technological progression that is still in use today

• NSF is now preparing for the demise of Moore’s law reached the limits of optical lithography Single bit logic is fading to quantum computing and the q‐bit

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Moore’s Law1965: Fairchild’s Director Gordon Moore introduces Moore’s law which accurately predicts the exponential increase of transistor density in an IC and provides a guide for technological progression that is still in use today

•NSF is now preparing for the demise of Moore’s lawreached the limits of optical lithography Single bit logic is fading to quantum computing and the q‐bit

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Evolution Of Microelectronics (cont.)

1964: Multi‐chip SLT packaging technology introduced by IBM•1965: Fairchild Engineers develop Dual In‐Line (DIP) chip packaging•1966: Semiconductor bipolar RAM•1966/1967: Computer aided design leads to Application Specific IC (ASIC)•1967: Turnkey equipment supplies such as Applied Materials introduce commercial tooling•1969: Intel enters the scene with commercial tooling, silicon gate technology, and embedded metallic leads

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TTM Institute of Technology 101966 : First 256K Bipolar Ram 1971 : Intel’s 1stMicroprocessor: i4004

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THE GOAL OF ASIC DESIGNER

Meet the market requirement• Satisfying the customer need• Beating the competition• Increasing the functionality• Reducing the cost

Achieved by• Using the next generation Silicon Technologies• New Design concept and Tools• High Level Integration

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Power

Cost

Delay

“Smaller is Better”

THE PERFORMANCE CUBE

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VLSI TECHNOLOGY

Backbone for all IT advancements. A Technology solution and not a product. Packages lot of circuitry ( Millions of Gates] Miniaturisation Confidentiality Low power operation Hand held battery operated gadgets

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APPLICATIONS

High Performance computing

Datacom/ Networking

Telecom/MOBILE/CELL/ WIL

Multimedia

Smart Cards

Remote Controls

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ADVANTAGES OF VLSI

REDUCTION IN

Design cycle time

Product Size

Power Consumption

Cost

INCREASE IN

Speed

Design Security

Productivity

Design Flexibility

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MOORE’S LAW

In 1969, Gorden Moore stated that Silicon Technology will double the number of transistors per chip every 18 months!!!

Gordon MooreIntel Co-Founder and Chairmain Emeritus

Image source: Intel Corporation www.intel.com

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MOORE’S LAW

In 1969, Gorden Moore stated that Silicon Technology will double the number of transistors per chip every 18 months!!!

And it is happening ! ! ! ! ! ! !!!!!!!!

Now Moore’s law has become self sustaning

Gordon MooreIntel Co-Founder and Chairmain Emeritus

Image source: Intel Corporation www.intel.com

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INTEGRATION LEVEL

Year Types gates per chip

60’s - SSI : small-scale integration ~10

70’s – MSI: medium-scale integration ~100–1K

80’s- LSI: large-scale integration ~1K –10K

90’s- VLSI: very large-scale integration ~10K–100K

ULSI: ultra large scale integration ~1M–10M upwards

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Shrinking of Technology

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Technology Definition

• SSI : 2 - 20 GATES

• MSI : 20 - 200 GATES

• LSI : 200 - 2000,000 GATES

• VLSI : OVER 1 MILLION GATES

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Gate & Interconnect Delays with shrinking

0.651989

0.51992

0.351995

0.251998

0.182001

0.132004

0.12007

05

10152025303540

Gate delayInterconnect delay

Source: SIA Roadmap 1997

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Technology DirectionsYear 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35Mtrans/cm2 7 14-26 47 115 284 701Chip size (mm2) 170 170-214 235 269 308 354Signal pins/chip 768 1024 1024 1280 1408 1472Clock rate (MHz) 600 800 1100 1400 1800 2200Wiring levels 6-7 7-8 8-9 9 9-10 10Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6High-perf power (W) 90 130 160 170 174 183Battery power(W) 1.4 2.0 2.4 2.0 2.2 2.4

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Over View Of

VLSI DESIGN METHODOLOGY

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VLSI - OVERVIEW

Customer Specification

Semi -CustomASIC

Gate Array ASIC

FPGA ASIC

VLSI TECHNOLOGY

Full Custom

ASIC

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Silicon ManufacturingAlternatives

Standard Components Application Specific ICs

Fixed Application

Applicationby Programming

SemiCustom

SiliconCompilation

FullCustom

LogicFamilies

HardwareProgramming

(MASK)

SoftwareProgramming

TTLCMOS

PLAROM

MicroprocessorEPROM,EEPROM

PLD

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Design Styles

Complexity of VLSI circuits

Full custom

Performance Size Cost Market time

Standard Cell Gate Array FPGA

Different design styles

Cost ,Flexibility,Performance

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VLSI - OVERVIEW(cont)

Customer Specification

Semi -Custom ASIC

Gate Array ASIC

FPGA ASIC

Full Custom

ASIC

Logic Design/Front EndGate Level

Net List

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behavioral 13

Blocking assignment

always @(A1 or B1 or C1 or M1)// blocking assignments begin: BLOCK_COMB M1 = #3 (A1 & B1); Y1 = #1 (M1 | C1); end

A1

B1

C1

M1

Y1

3 1

LOGIC DESIGN

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VLSI - OVERVIEW

Customer Specification

Semi -Custom ASIC

Gate Array ASIC

FPGA ASIC

Full Custom

ASIC

Logic Design/Front End

Physical Design/Back End

Gate Level Net List

Physical layout

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PHYSICAL DESIGN

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FOUNDRYMasks

Si wafer

Chemicals

ProcessedWafer

Chips

Finished ASIC

ASICprocessing

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ASIC

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Design Summary

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Design Functional Parameters Applications System On Chip

Mobile Communications

Networking

Space/Automobile applications

Signal Processing

Remote Sensing

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Examples :

• SSI : All 74 XX ,54 XX series gates

• MSI: Decoders, mux, shift registers, counters etc.

• LSI: Memories, 8bit UP’s/ UC’s , Peripheral devises etc

• VLSI : X86 to pentium,memories,and fpga’s & ASIC’s

ASIC Products

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Applications Growth.

1971 : Intel 4004 - 2300 transistors, 1 MHz clock

Ultra Sparc III - 16 Million transistors

2001 : Intel P4 - 42 Million, 2 GHz clock

HP PA-8500 - 140 Million transistor

Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s

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Design Characteristics

0.13M12MHz1.5um

CAESystems,Silicon

compilation

7.5M333MHz0.25um

Cycle-basedsimulation,

FormalVerification

3.3M200MHz

0.6um

Top-DownDesign,

Emulation

1.2M50MHz0.8um

HDLs,Synthesis

0.06M2MHz6um

SPICESimulation

Key CAD Capabilities

The Challenges to sustain such an exponential growth to achieve gigascale integration have shifted in a large degree, from the process of manufacturing technologies to the design technology.

VLSI Technology Trend

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Intel 4004 Microprocessor

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Intel Pentium (IV) Microprocessor

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Technology 0.1 umTransistors 200 MLogic gates 40 MSize 520 mm2

Clock 2 - 3.5 GHzChip I/O’s 4,000Wiring levels 7 - 8Voltage 0.9 - 1.2Power 160 WattsSupply current ~160 Amps

PerformancePower consumptionNoise immunityAreaCostTime-to-market

Tradeoffs!!!

The VLSI Chip in 2006

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Design Abstraction Levels

DEVICE

n+S D

n+

G

CIRCUIT

VoutVin

CIRCUIT

VoutVin

GATE

MODULE

+

SYSTEM

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VLSI TECHNOLOGY

Encompasses different Design Domains:

Logic Design - As Code

Physical design - As Layout

Product Fabrication - As product

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DESIGN METHODOLOGIES- Y CHART

Circuit abstraction levelMicro architectureabstraction level

Logic abstraction levelSystem abstraction level

Physical domain

STRUCTURAL DOMAINBEHAVIORAL DOMAIN Synthesis

Chips.MCM,boards

Cells

Chips / modules

Layout transistor

TransistorsLogic gates

ALUs , registers

processors

instructionsSubroutines ,B.equations

programs

Application algorithms

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Overview Of VLSI Design Methodology Summary : * VLSI Design Methodology using Major Activity Blocks

* Explain the Activity in each of the above Block. A) Logic Design. B) Physical design c) Foundry

* Types of libraries appended to Design Flow & its significance * Using HA Truth table derive the following a) Boolean Expression b) Behavioral Model C) Structural Model d) Physical Model e) Gate level Netlist

* With the help of Y-Chart explain Design domains and Levels of Abstraction

DAY ~ 2

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Thank You

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Technology Definition

• SSI : 2 - 20 GATES

• MSI : 20 - 200 GATES

• LSI : 200 - 2000,000 GATES

• VLSI : OVER 1 MILLION GATES

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Semiconductor Product Evolution (cont.)

1925 - MOSFET transistor Heil (England) 1935 - MOSFET transistor – Lilienfeld (Canada) 1947 - Transistor –Bardeen (Bell Labs) 1949 - Bipolar transistor – Shockley 1956 - First bipolar digital logic gate by Harris 1959- First monolithic IC by Jack Kilby 1960 - First commercial IC logic gate by Fairchild

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Semiconductor Product Evolution

1960’s - CMOS – plagued with manufacturing problems 1960’s - PMOS in (calculators) 1962 - 90 - TTL Logic gates 1974 - 80 - ECL Logic gates 1970’s - NMOS in (4004, 8080) – for speed 1980’s - CMOS in – preferred MOSFET technology

because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K, …

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Technology Evolution TECHNOLOGICAL

YEAR ERA BREAKTHROUGH

1920 -- Vacuum Tube - Vacuum Technology -- Glass to metal seal

1948 -- Transistor fabrication -- Crystal growth

1958 -- SSI - Planar technology - Digital Gates -- Photolithography

1962 -- MSI - PMOS Technology - Registers, -- Gate Oxide decoders, muxes 1968 -- LSI - NMOS Technology- Memory -- ION Implantation & CVD

1978 -- VLSI - CMOS Technology -- multi layer interconnect Micro processors Technology

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Evolution Of Microelectronics (cont.)

1960: Fairchild’s first ICDec. 1947: First Transistor

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