08 Simple CMOS Fab

8/3/2019 08 Simple CMOS Fab

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CMOS Fabrication(with extended comments)


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CMOS FABRICATION TECHNOLOGYThe following discussion will concentrate on the well-

established CMOS fabrication technology, which requires that

both n-channel (nMOS) and p-channel (pMOS) transistors be

built on the same chip substrate. To accommodate both nMOSand pMOS devices, special regions must be created in which

the semiconductor type is opposite to the substrate type.

These regions are called wells or tubs. A p-well is created in an

n-type substrate or, alternatively, an n- well is created in a p-

type substrate. In the simple n-well CMOS fabrication

technology, the nMOS transistor is created in the p-typesubstrate, and the pMOS transistor is created in the n-well,

which is built-in into the p-type substrate.

-VSS +VDDSDD S

G G

p+ p+

p-welln+ n+n+ p

+

OxideIsolation

p-MOSFET n-MOSFET


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CMOS FABRICATION TECHNOLOGYThe simplified process sequence for the fabrication of

CMOS integrated circuits on a p- type silicon substrate isshown.

The process starts with the creation of the n-well regions forpMOS transistors, by impurity implantation into the substrate.

Then, a thick oxide is grown in the regions surrounding thenMOS and pMOS active regions.

The thin gate oxide is subsequently grown on the surfacethrough thermal oxidation.

These steps are followed by the creation of n+ and p+regions (source, drain and channel-stop implants).

Finally the metallization is created (creation of metalinterconnects).

-VSS +VDDSDD S

G G

p+ p+

p-welln+ n+n+ p

+

OxideIsolation

Metallization


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Basic Processing StepsNote that each processing step requires that

certain areas are defined on chip by appropriatemasks. Consequently, the integrated circuit may be

viewed as a set of patterned layers of doped silicon,polysilicon, metal and insulating silicon dioxide. Ingeneral, a layer must be patterned before the nextlayer of material is applied on chip. The process usedto transfer a pattern to a layer on the chip is calledlithography.

The sequence starts with the thermal oxidationof the silicon surface, by which an oxide layer of

about 1 micrometer (1000 nm) thickness, forexample, is created on the substrate, see (b). Theentire oxide surface is covered with a layer ofphotoresist, which is a light-sensitive, acid-resistantorganic polymer, initially insoluble in the developingsolution (c). The photoresist material is exposed toultraviolet (UV) light, the exposed areas becomesoluble so that the they are no longer resistant to

etching solvents. To selectively expose thephotoresist, we have to cover some of the areas onthe surface with a mask during exposure. Thus, whenthe structure with the mask on top is exposed to UVlight, areas which are covered by the opaque featureson the mask are shielded. In the areas where theUV light strikes the photoresist, it is exposedand becomes soluble in certain solutes (d).


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PhotoResist

PhotoResist normally comes in powder form, which is insensitive to

light. It is reconstituted into liquid form by adding a solvent, typically

alcohol.

The wafer is mounted on a turntable, spinning slowly, and the

photoresist is discharged into its center. Centrifugal force spreads

the resist outward across the wafer. The thickness that remains on the

wafer is a function of the rate of wafer spin and the viscosity of the

photoresist. The thickness is monitored by light diffraction, which is

used to adjust the spin rate to reach the correct PR thickness.

After the PR is applied, the wafer is heated (~160C) to evaporate the

solvent, leaving a smooth solid coating.

Phase Interference gives

Photoresist Thickness


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PhotoResist

The wafer is protected from light, and is put into the

photo-lithography tool.Lightis focussed on the

wafer, delineating the IC pattern.

The wafer is removed and immersed in a

Developer Solution. If the PR is positive resist,

then those areas which received light will dissolve

away. Negative resist reacts the opposite way, with

those areas which were NOT exposed to light being

dissolved. This step will leave holes in the resistlayer.

The wafer is then heated to harden the patterned

resist so that it will withstand immersion into acids.

A typicalhardening bakeis ~300C.

The wafer then re-enters the processing line, for

eitheretching or deposition in the patternedholes. In rare cases, the photoresist is not

adequate as a mask itself, and the patterns are

processed to make a more robust mask, e.g. of

thick SiO2 (for very high energy implants) or Si3N4

for solvent etches which also attack PR.Photo Lithography

Exposure Tool


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PhotoResist

PhotoResist is used for two functions:

Delineation for Etching. A blanket deposition is made on thewafer, then photoresist patterning covers the areas to be SAVED.

After developing, the wafer is etched and all parts NOT

COVERED by photoresist are removed.

Delineation for Deposition. For ion implantation, areas are

opened for doping the silicon. The photoresist absorbs all ionsexcept for the areas which are open. In these areas (e.g. Drain or

Source wells) the ions penetrate into the silicon.

A second Deposition function for photoresist is for patterning

thin layers which adhere readily to the wafer. For example, a thin

layer of Ti (200A) may be deposited through a PR mask to act asglue. The PR openings are so steep, that the Ti film is

discontinuous at the edges of the openings. When the PR is

removed, it automatically lifts off the blanket Ti deposition, leaving

behind Ti only in the PR holes. This process is called deposition

processing by LiftOff.


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Basic Processing StepsThe type of photoresist which is initially

insoluble and becomes soluble after exposureto UV light is called positive photoresist.

Following the UV exposure step, theunexposed portions of the photoresist can beremoved by a solvent. Now, the silicon dioxideregions which are not covered by hardenedphotoresist can be etched away either by usinga chemical solvent (HF acid) or by using a dry

etch (plasma etch) process (e). Note that at theend of this step, we obtain an oxide windowthat reaches down to the silicon surface (f). Theremaining (unexposed) photoresist can bestripped from the silicon dioxide surface byusing another solvent, leaving the patternedsilicon dioxide feature on the surface, see (g).

The fabrication of semiconductor devicesrequires several such pattern transfers to beperformed on silicon dioxide, polysilicon, andmetal. The basic patterning process used in allfabrication steps, however, is quite similar tothe one shown.examined.


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Basic Processing StepsThe result of a single lithographic

patterning sequence on silicon dioxide,

without showing the intermediate steps.Compare the unpatterned structure(top) and the patterned structure(bottom). It took 9 steps to make thissimple hole:

1. Oxidize silicon surface

2. Deposit photoresist

3. Anneal photoresist

4. Mount mask above silicon

5. Expose to UV light

6. Develop photoresist7. Etch photoresist exposed to UV

8. Etch SiO2 through photoresist hole

9. Remove photoresist


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Making a CMOS Device - 1 The process starts with the oxidation of the siliconsubstrate (a), in which a relatively thick silicon dioxidelayer (5000A), also called field oxide, is created on

the surface (b). Then, the field oxide is selectivelyetched to expose the silicon surface on which the MOStransistor will be created (c). Following this step, thesurface is covered with a thin, high-quality oxide layer(25A), which will eventually form the gate oxide of theMOS transistor (d). On top of the thin oxide, a layer ofpolysilicon (polycrystalline silicon, 3000A) is deposited(e). Polysilicon is used both as gate electrode material

for MOS transistors and also as an interconnectmedium in silicon integrated circuits. Undopedpolysilicon has relatively high resistivity. The resistivityof polysilicon can be reduced, however, by doping itwith impurity atoms.

After deposition, the polysilicon layer is patternedand etched to form the interconnects and the MOStransistor gates (f). The thin gate oxide not covered bypolysilicon is also etched away, which exposes the baresilicon surface on which the source and drain junctionsare to be formed (g). The entire silicon surface is thendoped with a high concentration of impurities, eitherthrough diffusion or ion implantation (in this case withdonor atoms to produce n-type doping).


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Making a CMOS Device - 2

(h) shows that the doping penetratesthe exposed areas on the silicon surface,ultimately creating two n-type regions

(source and drain junctions) in the p-typesubstrate. The impurity doping alsopenetrates the polysilicon on the surface,reducing its resistivity. Note that thepolysilicon gate, which is patterned beforedoping actually defines the precise location

of the channel region and, hence, thelocation of the source and the drainregions. Since this procedure allows veryprecise positioning of the two regionsrelative to the gate, it is also called a self-aligned process. Once the source and drain regions are

completed, the entire surface is againcovered with an insulating layer of silicondioxide (i). The insulating oxide layer isthen patterned in order to provide contactwindows for the drain and source junctions(j).


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Making a CMOS Device - 3

The surface is covered with evaporated aluminum (5000A) which willform the interconnects (k). Finally, the metal layer is patterned and etched,completing the interconnection of the MOS transistors on the surface (l).

Usually, a second (and third) layer of metallic interconnect (>5000A) canalso be added on top of this structure by creating another insulating oxidelayer, cutting contact (via) holes, depositing, and patterning the metal.


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CMOS n-Well Process We have covered (1) the basic processsteps for pattern transfer through lithography,and (2) gone through the fabrication procedureof a single n-type MOS transistor. Now we

consider the fabrication sequence of n-wellCMOS integrated circuits. Shown are both thetop view of the lithographic masks and a cross-sectional view of the relevant areas.

The n-well CMOS process starts with amoderately doped (impurity concentration~1016/cm3) p-type silicon substrate. Then, an

initial thick f ield oxide layer (5000A) is grownon the entire surface. The first lithographic maskdefines the n-well region. Donor atoms, usuallyphosphorus, are implanted through this windowin the oxide. Once the n-well is created, theactive areas of the nMOS and pMOS transistorscan be defined. The next figures show the

significant milestones that occur during thefabrication process of a CMOS inverter.

Following the creation of the n-well region,a thick field oxide is grown around the transistoractive regions, and a thin gate oxide (25A) isgrown on top of the active regions.


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CMOS n-Well The polysilicon layer(3000A) is deposited usingchemical vapor deposition(CVD) and patterned by dryplasma etching. The createdpolysilicon lines will function asthe gate electrodes of thenMOS and the pMOStransistors and theirinterconnects. Also, the

polysilicon gates act as self-aligned masks for thesource and drain implantationsthat follow this step

Polysilicon Gate Connections


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CVD Chemical Reactions SiH4(gas) + O2(gas) SiO2(solid) + 2H2 (gas)

SiH4(gas) + H2(gas) +SiH2(gas)

2H2(gas) + PolySilicon (solid)

Continuous gas flow

Deposited film

Silicon substrate

Boundary layer

Diffusion ofreactants


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CMOS n-WellUsing a set of two masks, then+ and p+ Source and Drainregions are implanted into thesubstrate and into the n- well,respectively.

The ohmic contacts to thesubstrate and to the n-well areimplanted in this process step.

(If a doped silicon region ispartially doped to >1018/cm3,then metal contacts to thatvolume are almost alwaysohmic (no Shottkey Barriereffect). The possibility of aShottkey Barrier effect isalways possible, and care must

be made of the selection ofdoping and metal contacts.)

I solation layer(discussed later)


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CMOS n-Well An insulating silicon dioxidelayer is deposited over the entirewafer using CVD (5000A). This isforpassivation, the protectionof all the active components fromcontamination.

The contacts are defined andetched away to expose thesilicon or polysilicon contactwindows. These contact windows

are necessary to complete thecircuit interconnections using themetal layer, which is patterned inthe next step.

(CVD = Chemical Vapor

Deposition, where reactive gasescollide above the wafer, andchemical reaction products thenfall onto the wafer creating a newlayer.)


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CMOS n-Well Metal (aluminum, >5000A)is deposited over the entirechip surface using metalevaporation, and the metallines are patterned throughetching. Since the wafersurface is non-planar, thequality and the integrity of themetal lines created in this stepare very critical and are

ultimately essential for circuitreliability.

Since the metal connectstwo separate devices, it iscalled Local Interconnect.The connection of adjacent

devices is often called LI-1, asbeing the lowest level ofinterconnection.


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Interconnection Materials

Polysilicon interconnects are used to connect

Gates and other short-distance connections whichhave minimal currents. Polysilicon is a very stablematerial that rarely interacts with nearby materials.

Metal interconnects have 3-5x the speed of

polysilicon (electron mobility is higher) and lessresistance. However, metals may react with nearbymaterials, and may have to be encapsulated usingnitrides (e.g. Si3N4 or TiN) to prevent unwanted

reactions, or partial erosion in subsequent etchingprocedures. This is expensive. In Upper Metallurgy(not local interconnects) metal is always usedbecause processing is simple: only Metal + SiO2.


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CMOS n-Well The composite layout andthe resulting cross-sectionalview of the chip, showing onenMOS and one pMOStransistor (built-in n-well), thepolysilicon and metalinterconnections.

The final step is to deposita full SiO2passivation layer(5000A), for protection, over the

chip, except for wire-bondingpad areas.

If the wafer will be storedfor some months, a final thinblanket layer of Si3N4 may beapplied to prevent penetration

by water vapor. CompletedFEOL wafers are sometimesstored for more than a yearbefore processing in a BEOLfactory.

ll


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CMOS n-WellThe patterning process by the use of a succession of masks and processsteps is conceptually summarized below. It is seen that a series of

SEVEN masking steps and 34 process stepsmust be sequentially performed for the desired patterns to be created on

the wafer surface. An example of the end result of this sequence is shownas a cross-section on the right.

Ad d CMOS T h l i


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Advanced CMOS TechnologiesTwin-Tub (Twin-Well) CMOS Process

This technology provides the basis for separate optimization of thenMOS and pMOS transistors, thus making it possible for threshold voltage,

body effect and the channel transconductance of both types of transistorsto be tuned independently. Generally, the starting material is a n+ or p+substrate, with a lightly doped epitaxial layer (~1015/cm3)on top.This epitaxial layer provides the actual substrate on which the n-well andthe p-well are formed. Since two independent doping steps are performedfor the creation of the well regions, the dopant concentrations can becarefully optimized to produce the desired device characteristics.

In the conventional n-well CMOS process, the doping of the wellregion is typically about one order of magnitude higher than the substrate,which, among other effects, results in unbalanced drain parasitics(possible latchup). The twin-tub process, below, avoids this problem.

Ad d CMOS T h l i


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Advanced CMOS TechnologiesSubstrate for Twin-Well MOS Technogy

For inexpensive and low-performance chips, one may use a heavily doped substrate

and omit one well. The substrate should be doped to about 1016/cm3, with a resistivityof about 1 -cm. This allows simpler construction, with good Ground Potential

distribution, but the devices are not optimal and there is a chance of latch-up if the

voltages are pushed hard.

For high-performance chips, one uses a low doped substrate, 1015/cm3, 10 -cm, and

then constructs Two Wells at optimum doping levels (called Tubs in the diagram).

Since the substrate is lightly doped, there is less chance for latch-up because of the high

resistivity.

Ad d CMOS T h l i


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Advanced CMOS TechnologiesSilicon-on-Insulator (SOI) CMOS Process

Rather than using silicon as the substrate material, an insulating substratewill improve process characteristics such as speed and latch-up

susceptibility. The SOI CMOS technology allows the creation ofindependent, completely isolated nMOS and pMOS transistors virtuallyside-by-side on an insulating substrate. The main advantages of thistechnology are the higher integration density (because of the absence ofwell regions), complete avoidance of the latch-up problem, and lowerparasitic capacitances compared to the conventional n-well or twin-tubCMOS processes. A cross-section of nMOS and pMOS devices in createdusing SOI process is shown below.


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References

CMOS Digital Integrated Circuit Design - Analysis and

Design by S.M. Kang and Y. Leblebici W. Maly, Atlas of IC Technologies, Menlo Park, CA:

Benjamin/Cummings, 1987.

A. S. Grove, Physics and Technology of Semiconductor

Devices, New York, NY: John Wiley & Sons, Inc., 1967. G. E. Anner, Planar Processing Primer, New York, NY:

Van Nostrand Rheinhold, 1990.

T. E. Dillinger, VLSI Engineering, Englewood Cliffs, NJ:

Prentice-Hall, Inc., 1988. S.M. Sze, VLSI Technology, New York, NY: McGraw-

Hill, 1983.


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New Concepts in this Lecture Single Well ConstructionOnly need to construct one well if

use p+ or n+ substrate. (2,3)

Photoresist 5 step process for application and patterning.Can be used for Deposition, Etching or Deliniation (4-7)

Self aligned Gate Make Gate structure so it automaticallyaligns source/drain. (10,11)

Field Oxide General protection to devices is given bydepositing thick SiO2 layer at beginning (13)

Interconnects Basic devices may be connected togetherwith either metal or polysilicon bands, depending on the

expected signal current. (19)

Twin-Tub CMOS Uses p or p- substrates to prevent latchupand cross-talk, but requires separate tubs for the pMOS and

nMOS devices (22)

CMOS on SOI By putting CMOS circuits on SOI (silicon oninsulator) the substrate capacitance is eliminated (2x increase

in speed) and cross-talk/latchup is eliminated. (24)

08 Simple CMOS Fab

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