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Influence of metal coverage on transistor mismatch and variability

in copper damascene based CMOS technologies

Nicole Wils, Hans Tuinhout, Maurice Meijer

NXP Semiconductors Central R&D/Research

High Tech Campus 37, 5656AE Eindhoven, The Netherlands

Abstract

This paper summarizes a comprehensive study on the effectof asymmetrical metal coverage on matching performance

for a 45 nm copper damascene based CMOS process. We

demonstrate that random mismatch fluctuations are not

affected by metal layout asymmetries and we provide

valuable new insights about the magnitude of systematic

mismatches that can be expected due to asymmetricallayouts and CMP tiling. For the first time we also present

results on the impact of temperature increases on bothsystematic as well as random drain current mismatches.

Introduction

Matched devices (supposedly identical IC elements) are

essential for accurate analogue and mixed signal circuits.Design for good matching not only requires that the

transistor area is optimized to obtain required matching, but

also the complete layout of the devices should be identical

in order to avoid systematic mismatch effects (e.g. due to adifference in well proximity effect or STI stress effect in

case of MOS transistors [1,2]). Moreover, the environment

near matched devices should be as symmetrical as possible.

For aluminium based metallization processes it has been

shown that asymmetric metal coverage of matched MOSdevices can result in significant drain current mismatch on

the order of a few percent [3]. This was attributed to local

mechanical stress differences. In advanced CMOS processes(120 nm and beyond), Al-metallization is replaced by

copper damascene metallization, which is essentially

different in terms of deposition temperatures and material

characteristics. This could potentially result in a

substantially different impact on mismatch and variability.This study presents a dedicated set of matched pair test

structures to study the effect on matching of Cu-damascene

based metallization in a 45 nm state-of-the-art technology.The effect on both systematic as well as on random drain

current mismatch is investigated. Furthermore we tested the

impact of temperature increase on these mismatches to

further assess a possible mechanical stress effect.

Test structures and analysis

Test structure layout

Our study is based on a new set of 45 nm CMOS technologynode matched pair test structures. The layout of the basic

matched pair test structure and probe pad configuration is

shown in Figure 1. Extreme care was taken to assure that allpossible (undesired) effects due to asymmetric metallization

layout and unequal access resistances are avoided. Also note

the relatively large separation between the STI edge and the

gated area to mitigate STI stress effects [1]. A special set of

matched pair test structures is used for this metal coveragestudy. MOS transistor dimensions are chosen relatively

large (W/L=2.4/4), for two reasons: 1) large transistors are

representative for relatively well matching device pairs in

high precision analogue MOS circuits, and 2) dimensionsshould be large enough to avoid that natural random dopant

fluctuations overshadow the investigated systematic

mismatch effect. An intentional asymmetry in the metal

coverage between both transistors of the pair is applied

(Figure 2): the left transistor of the pair (T1) has no metalcoverage, while the right transistor (T2) is partly or

completely covered with metal. To avoid undesired metal

coverage on top of the transistors due to CMP dummy tileinsertion, no-tile masks are placed over the transistor

areas. Note that the metal plate is connected to the source; a

dummy metal bar is also added to T1to improve the layoutenvironment symmetry. The metal on top of T2 has been

varied in shape (plate, lines, tiles) as well as in level (metal

1, 2, 3 or 4), see Table 1. For one variant, the no-tile maskswere omitted to assess the impact of automatic tiling. As

reference, a completely symmetrical matched pair without

metal coverage is available. As with any properly designed

matched pair, the effects of parametric wafer gradients andother process spreads are mitigated due to the relatively

close spacing. This allows for independent assessment ofmicroscopic device architecture fluctuations and systematic

mismatch effects due to intentional environmental

asymmetries.

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8.22010 IEEE International Conference on Microelectronic Test Structures, March 22-25, Hiroshima, Japan.

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Figure 1: ideal MOSFET matched pair layout.

Figure 2: example of matched pair with intentional asymmetry in

metal coverage: T2has been covered with a metal-2 plate which is

connected to the source.

Analysis

For quick qualitative as well as proper quantitative

evaluation of our 45 nm CMOS mismatch performances we

measure complete linear region (Vds=50 mV) Id-Vgscurvessimultaneously on both transistors of each pair. The numberof measured pairs on the wafer (population size) was 119. A

complete voltage sweep allows us to generate so called

mismatch sweeps, showing the relative drain current

mismatch median and standard deviation (_Id/Id and

_Id/Id) as a function of gate voltage [1]. These sweeps

immediately reveal a possible effect on the drain current

(offset as well as fluctuations) in different operating regions,going from weak to strong inversion. The main transistor

parameters Vt and were derived from the original linear

region Id-Vgs curves using fixed overdrive three-point-

extractions [4]. Subsequently for each pair the Vtdifference

(Vt) and the relative current factor difference () werecalculated. The median of the Vt difference (Vt) and

relative current factor difference () between TT1 and

TT2 are indicative for the amount of systematic mismatch

between the two transistors of the pair and thus for theinfluence of metal coverage (since this is the only layout

difference between the two). The standard deviations of the

Vtdifference and the current factor difference (Vt and

) are a measure for the random mismatch

fluctuations. For intentionally asymmetric pairs, the

standard deviation may also include a component related to

the (deterministic) change of the impact of the asymmetry.

If the mechanical stress associated with the metal coverage

is not constant across the wafer, this would increase theobserved mismatch standard deviation for these pairs.

G2G1 S D2well

D1 G2G1 S D2well

D1

variant name T2covered with source connection

reference - -

M1 plate metal 1 plate yes




M1 lines width = space = 70 nm yes




M3/M4 grid grid of metal 3 and metal 4 lines yes

tiles small metal 1 tiles (20 X 0.40 x 0.40) no

tiles large metal 1 tiles (4 X 1.3 x 1.3) no

automatic tiling automatic tiling allowed no

Table1: list of different variants.

variant name T2covered with source connection

reference - -









M3/M4 grid grid of metal 3 and metal 4 lines yes

tiles small metal 1 tiles (20 X 0.40 x 0.40) no

tiles large metal 1 tiles (4 X 1.3 x 1.3) no

automatic tiling automatic tiling allowed no

Table1: list of different variants.

source connection

Gate1

Drain1

T1

Gate2

Drain2

T2

Metal 2

Metal 1

Poly silicon

Active

source connection

Gate1

Drain1

T1

Gate2

Drain2

T2

Metal 2

Metal 1

Poly silicon

Active

source connection

Gate1

Drain1

T1

Gate2

Drain2

T2

Metal 2

Metal 1

Metal 2

Metal 1

Poly silicon

Active

Poly silicon

ActiveResults

Results at room temperature

Figure 3 shows the relative drain current mismatch

fluctuation sweeps for the reference and for the pair where

T2was covered with metal-1 lines. 3 error bars obtained

from bootstrapping indicate the statistical uncertainty due to

the limited population size (N=119). It is clear that over thecomplete voltage range there is no significant difference

between the reference and the pair with asymmetric metal

coverage.

0.1

1

10

100

0.00 0.25 0.50 0.75 1.00 1.25

Vgs [V]

Figure 3: example of mismatch fluctuation sweeps (Id/Id as a

function of Vgs) for the reference matched pair (no metal coverage)

and the matched pair where T2 is covered with metal-1 lines.

error bars indicate statistical uncertainty.

Vtand mismatch fluctuation values (Vtand )

for the different NMOS variants (table 1) are shown in

Figure 4. For the reference matched pair an extra data point

I

/Id

d

2.4/4 NMOS

Vds=50 mV

[%]

reference

M1 lines on T2

Id(T1) IdT2) Id/Id [%] = x 200Id(T1) + Id(T2)

0.1

1

10

100

0.00 0.25 0.50 0.75 1.00 1.25

Vgs [V]

d

d

I

/I[%]

0.1

1

10

100

0.00 0.25 0.50 0.75 1.00 1.25

Vgs [V]

d

d

2.4/4 NMOS

Vds=50 mV

I

/I[%]

reference

M1 lines on T2

reference

M1 lines on T2



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(open triangle) has been added to show the repeatability of

the measurement (same population). From these figures we

can conclude that there is no statistically significant

influence of metal coverage on random fluctuations. This

implies that -a mechanical stress related- systematicmismatch (if present), is homogeneous across the wafer.

Figure 4: mismatch fluctuations as a function of variant (table1).Top: threshold voltage mismatch fluctuations (Vt) and bottom:

relative current factor mismatch fluctuations (). errorbars indicate statistical uncertainty. The extra point (open triangle)

for the reference indicates the repeatability of the measurement.

The drain current mismatch median sweeps for the

reference and for the asymmetrically covered pairs withmetal-1 or metal-3 lines are shown in Figure 5. In weak

inversion, possible effects of the metal coverage on drain

current fluctuations are overshadowed by the random

fluctuations and the associated statistical uncertainty. In

strong inversion however, the metal-1 lines cause asignificant drain current offset of 0.6%. There is no

significant influence of the metal-3 lines. These results are

reflected in the current factor mismatch values. The

mediansof the relative mismatch values () for the

different NMOS variants (table1) are presented in Figure 6.For some variants the metal covered (right) transistor T2has

a significantly lower current factor compared to the left

transistor T1. In particular, the first metal can cause a offset of up to 1.5% (metal-1 lines), but for the third and

fourth metal we must consider the effect not statistically

significant.

[%]

I/I

Figure 5: example of mismatch median sweeps (Id/Id as a

function of Vgs) for the reference matched pair (no metal coverage)

and the matched pair where T2 is covered with metal-1 lines or

metal-3 lines. error bars indicate statistical uncertainty. Theinset shows the right part of the characteristic with adjusted y-axis.

Figure 6: median of relative current factor mismatch () as

a function of variant. error bars indicate statisticaluncertainty. The extra point (open triangle) for the referenceindicates the repeatability of the measurement.

Large metal tiles have an impact comparable to the full

metal plate, which is no surprise since the four large tiles

almost completely cover the transistor area, whereas the

total coverage of the small tiles is substantially less (Figure7). From Figure 8, which shows the median of the threshold

voltage mismatch (Vt) as a function of variants, we

conclude that the effect of metal coverage on the threshold

voltage of NMOS devices can be neglected for all variants.

The maximum offset (median) that is observed is limited to

1.5 mV (_Vt=437 mV), which is significantly different

from zero, but it is still less than the random mismatch

fluctuations of 2 mV (figure 4, top).

d

d

-10

-5

0

5

10

0.00 0.25 0.50 0.75 1.00 1.25

Vgs [V]

-1.0

-0.5

0.0

0.5

1.0

0.50 0.75 1.00 1.25

reference

M1 lines on T2

M3 lines on T2

d

d

I

/I[%]

-10

-5

0

5

10

0.00 0.25 0.50 0.75 1.00 1.25

Vgs [V]

d

d

-10

-5

0

5

10

0.00 0.25 0.50 0.75 1.00 1.25

Vgs [V]

-1.0

-0.5

0.0

0.5

1.0

0.50 0.75 1.00 1.25-1.0

-0.5

0.0

0.5

1.0

0.50 0.75 1.00 1.25

I

/I[%]

reference

M1 lines on T2

M3 lines on T2

reference

M1 lines on T2

M3 lines on T2

Vt=Vt(T1) Vt(T2) 2.4/4 NMOSVds=50 mV

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

V

t[mV]

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Vt=Vt(T1) Vt(T2)Vt=Vt(T1) Vt(T2)Vt=Vt(T1) Vt(T2) 2.4/4 NMOSVds=50 mV

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

t

V

[mV]

0.0

0.5

1.0

1.5

2.0

2.5

3.0

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

t

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V

[mV]

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%]

0.0

0.2

0.4

0.6

0.8

1.0

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

[%]

-0.5

0.0

0.5

1.0

1.5

2.0

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%] = (T1) (T2)(T1) + (T2)

[%]

2.4/4 NMOS-0.5

0.0

0.5

1.0

1.5

2.0

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%] = (T1) (T2)(T1) + (T2)

[%]

-0.5

0.0

0.5

1.0

1.5

2.0

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%]

-0.5

0.0

0.5

1.0

1.5

2.0

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%]

-0.5

0.0

0.5

1.0

1.5

2.0

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%] = (T1) (T2)(T1) + (T2) [%] =(T1) (T2)(T1) + (T2) [%] =(T1) (T2)(T1) + (T2)(T1) (T2)(T1) + (T2)

[%]

2.4/4 NMOS

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For PMOS devices, similar observations as found for

NMOS devices were encountered, albeit substantially

smaller in magnitude. This is illustrated in Figure 12, where

the median of the current factor mismatch is shown as a

function of the different PMOS variants (table1), forT=25C and T=125C. In all cases the median offset is less

than 0.5%. Also note that, although small, the effect is

opposite to the effect observed for the NMOS devices: in

case of PMOS the strained device (T2) has a higher current

factor (higher mobility) than the unstrained device (T1).

Note the similarity with the impact of STI stress [1].Furthermore, the effect is reduced or again even reverses

sign at 125C.

Figure 12: median of relative current factor mismatch () asa function of variant (PMOS). Results for T=25 and T=125C arecompared. Note that the scale is different from figure 9 (NMOS).

Comparable to the NMOS devices, no statisticallysignificant effects of the metal coverage on the mismatch

fluctuations of the PMOS devices are seen. This is

illustrated in Figure 13 and 14, where respectively thethreshold voltage mismatch fluctuations and the relative

current factor mismatch fluctuations are shown for the

different PMOS variants. In the same graphs the results of

measurements at T=125C can be found: also for the PMOS

devices a slight reduction in fluctuations is seen at highertemperature.

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

V

t[mV]

T=125C

T=25C

0.4

0.6

0.8

1.0

1.2

1.4

2.4/4 PMOS Vt=|Vt(T1)| |Vt(T2)|

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

V

t[mV]

T=125C

T=25C

T=125C

T=25C

0.4

0.6

0.8

1.0

1.2

1.4

2.4/4 PMOS Vt=|Vt(T1)| |Vt(T2)|Vt=|Vt(T1)| |Vt(T2)|

Figure 13: threshold voltage mismatch fluctuations (Vt) as afunction of variant (PMOS). Results for T= 25C and T=125C are

compared. error bars indicate statistical uncertainty. The extra

points (triangles) for the reference indicate the repeatability of themeasurements.

2.4/4 PMOS

= (T1)||(T2)|(T1)| +|(T2)|

Figure 14: relative current factor mismatch fluctuations ()as a function of variant (PMOS). Results for T= 25C and

T=125C are compared. error bars indicate statisticaluncertainty.

T=125C

T=25C

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%]

0.10

0.14

0.18

0.22

0.26

0.30

0.34

2.4/4 PMOS

= (T1)||(T2)|(T1)|+|(T2)| T=125CT=25C

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%]

0.10

0.14

0.18

0.22

0.26

0.30

0.34

2.4/4 PMOS

T=125C

T=25C

T=125C

T=25C

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%]

0.10

0.14

0.18

0.22

0.26

0.30

0.34

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

[%]

0.10

0.14

0.18

0.22

0.26

0.30

0.34

2.4/4 PMOS

= (T1)||(T2)|(T1)|+|(T2)| =(T1)||(T2)|(T1)|+|(T2)|

[%]

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

T=125C

T=25C

2.4/4 PMOS

= (T1)||(T2)|(T1)| +|(T2)| =(T1)||(T2)|(T1)| +|(T2)|

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

reference

M1plate

M2plate

M3plate

M4plate

M1lines

M2lines

M3lines

M4lines

M3/M4grid

smalltiles

largetiles

automatic

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

[%]

T=125C

T=25C

T=125C

T=25C

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Conclusions

We present a comprehensive set of carefully designed

matched pair test structures for studying metal coverage

effects in a 45 nm state-of-the-art CMOS technology withCu damascene processing. We report substantial offsets in

drain currents of up to 1.5% for NMOS devices. Theseoffsets are attributed to mobility differences associated with

mechanical stress. At higher wafer temperatures (125 C)this stress effect apparently reduces significantly. To the

best of our knowledge this has not been reported before.

For most digital ULSI applications, an offset of a few

percents is generally considered negligible compared to thetotal process variability. It is therefore reassuring that this

study confirms that there will be no substantial contribution

to digital circuit variability due to (even arbitrary) placement

of metal routing and CMP tiles. For high precision analogue

and mixed signal applications however, it is (still) highlyrecommendable to avoid the use of first and second metal on

top of the matching devices. At least it should be made sure

that metal coverage and dummy tiling is always assymmetrical as possible on supposedly identical devices.

References[1] N. Wils, H. Tuinhout and M. Meijer, Characterization of STI

Edge Effects on CMOS Variability; IEEE Transactions onSemiconductor Manufacturing 2009, vol.22, no.1, pp.59-65[2] P.G. Drennan et al, Implications of Proximity Effects forAnalog Design; Proceedings IEEE CICC 2006, pp.169-176

[3] H.P. Tuinhout and M. Vertregt, Test structures forinvestigation of metal coverage effects on MOSFET matching;Proc.IEEE ICMTS 1997, pp.179-183[4] J.A. Croon et al, A comparison of extraction techniques forthreshold voltage mismatch; Proceedings IEEE ICMTS 2002,

pp.235-240[5] P. Andricciola and H.P. Tuinhout, The temperaturedependence of mismatch in deep-submicron bulk MOSFETs;IEEE Electron Device Letters 2009, vol.30, no.6, pp.690-692

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